CN107958905B - Power semiconductor module substrate - Google Patents

Abstract

The invention discloses a power semiconductor module substrate. The power switch comprises a plurality of power semiconductor chips which are connected in parallel and connected to adjacent power potential areas; a first auxiliary potential area is arranged between the first power potential area and the second power potential area, a second auxiliary potential area is arranged at a position adjacent to the second power potential area along the direction opposite to the first direction and the second direction, a third auxiliary potential area and a fourth auxiliary potential area are arranged in the third power potential area, and the first auxiliary potential area and the second auxiliary potential area are electrically connected with each other. The power semiconductor module provided by the invention has the advantages that the compact arrangement of the power module substrate is realized, so that the power density is improved, and meanwhile, the uniformity of stray parameters among all chip control loops of the power module is realized, so that the optimized switching characteristic is obtained, and the reliability is improved.

Description

Power semiconductor module substrate

Technical Field

The present invention relates to a substrate and a power semiconductor module, and in particular to a power semiconductor module substrate and a power semiconductor module composed of the power semiconductor module substrate.

Background technique

The terminal elements of the power semiconductor module that contact the external circuit can usually be divided into power terminals and control terminals. Sufficient spacing is usually required between the power terminals and control terminals and the contact area of the module substrate to meet the needs of different terminal welding equipment and processes. The reasonable arrangement of the power terminals and control terminals on the substrate and the position of the power semiconductor chip is conducive to improving the utilization rate of the module substrate, thereby improving the power density of the module.

The current carrying capacity of a single power semiconductor chip is limited. In order to expand the power processing capacity of the power semiconductor module, a large-capacity power semiconductor module usually uses a multi-chip parallel arrangement to form a bridge arm switch. The switch of the parallel-arranged chip is usually controlled by a pair of control terminals, and its switch circuit is shown in Figure 2.

Among them, Cge1 and Cge2 represent the gate capacitance of two power semiconductor chips in parallel, and the current carrying capacity of the power semiconductor chip is positively correlated with the voltage on the gate capacitance. Tg and Te are the ports connecting the power semiconductor module to the external drive circuit, which are used to receive the drive signal. Rg0 and Lg0 are the stray resistance and stray inductance of the common part of the drive circuit of each chip. Rg1, Lg1 and Rg2, Lg2 are the separate stray resistance and stray inductance caused by the position distribution of the two power semiconductor chips. During the opening process of the power semiconductor module, the driving voltage applied to Tg and Te changes from a specific negative value to a positive value. Due to the effect of the stray parameters of the drive circuit, the voltage across the gate capacitance increases, thereby increasing the power current passing through the power semiconductor chip; during the shutdown process, the driving voltage applied to Tg and Te changes from a specific positive value to a negative value, and the voltage across the gate capacitance decreases, thereby decreasing the power current passing through the power semiconductor chip.

If the stray inductance in the circuit is large, it is easy to cause voltage oscillation between the stray inductance and the chip's own capacitance during the switching process. If the oscillating voltage across the gate capacitor is lower than the threshold voltage that turns on the chip during the turn-on process, it will cause the chip to be turned off by mistake; if the oscillating voltage across the gate capacitor is higher than the threshold voltage that turns on the chip during the turn-off process, it will cause the chip to be turned on by mistake. Both of the above phenomena are not conducive to the normal operation of the chip. Since the gate capacitance is determined by the characteristics of the chip itself, the stray inductance of the drive circuit needs to be minimized during the design of the power module, thereby reducing the risk of false turn-on and false turn-off at high switching speeds.

If the individual stray parameters of the parallel chips are inconsistent, the gate capacitance charging or discharging speed will be inconsistent, which will cause uneven power current passing through the chip during the switching process. Since the voltage across the semiconductor chip is usually established before the current changes during the switching process, the uneven transient current will cause inconsistent losses on the power semiconductor chip, which will eventually be reflected in the inconsistent temperature between chips. When the power semiconductor module is working at full power, overtemperature and overcurrent caused by uneven chip current distribution may cause failure of semiconductor components and affect the normal operation of the module.

From the above description, it can be seen that the reasonable design of the terminal and substrate contact area and chip layout, the reduction of the stray inductance of the power semiconductor chip drive circuit and the balance of the stray parameters between parallel chips are three important considerations for module substrate design.

Summary of the invention

Taking the above technical points into consideration, the present invention provides a power semiconductor module substrate and a power semiconductor module thereof, which improves substrate utilization, reduces the total stray inductance of the drive circuit, reduces the risk of chip mis-switching, and improves power module reliability by optimizing the layout of the terminal area, chip and its control circuit.

The technical solution adopted by the present invention is:

1. The present invention protects a power semiconductor module substrate:

It includes four power potential regions and auxiliary potential regions, the four power potential regions are a second power potential region, a first power potential region, a third power potential region and a fourth power potential region which are arranged in sequence and spaced apart along a second direction; a plurality of power switches are installed on the first power potential region and the third power potential region; a hollow region is arranged inside the third power potential region, and the third and fourth auxiliary potential regions which are isolated and insulated are arranged in the hollow region.

The multiple power switches arranged in the third power potential area include two types of first power switches and second power switches, each power switch is composed of multiple power semiconductor chips, the first power switch is composed of switch-controllable transistor chips, and the second power switch is composed of diode chips with unidirectional conduction characteristics; for each first power switch arranged in the third power potential area, its control electrode is electrically connected to the third auxiliary potential area through its own first auxiliary connecting device, and the third auxiliary connecting device is used to electrically connect a second power switch in the middle of the third power potential area to the fourth auxiliary potential area.

The multiple power switches arranged on the first power potential area include two types of first power switches and second power switches, each power switch is composed of multiple power semiconductor chips, the first power switch is composed of switch-controllable transistor chips, and the second power switch is composed of diode chips with unidirectional conduction characteristics; a first auxiliary potential area is arranged between the first power potential area and the second power potential area, and a second auxiliary potential area is arranged near the corner position of the second power potential area in the opposite direction of the first direction and the opposite direction of the second direction; for each first power switch arranged in the first power potential area, its control electrode is electrically connected to the first auxiliary potential area through its respective first auxiliary connecting device, and the first auxiliary potential area is electrically connected to the second auxiliary potential area by the second auxiliary connecting device.

Only one potential region of the first auxiliary potential region is arranged between the first power potential region and the second power potential region, and no passive components and other potential regions are arranged; and the first auxiliary potential region is electrically connected only to the control electrode of each first power switch on the first power potential region through a first auxiliary connecting device and to the second auxiliary potential region through a second auxiliary connecting device.

The multiple power semiconductor chips in each power switch are connected in parallel to each other and are connected to a power potential region adjacent to the power potential region where the power semiconductor chips are located through a power connection device.

The present invention reduces the stray inductance in the substrate loop of the upper bridge arm and reduces the unevenness of the stray inductance between chips through the first auxiliary potential region and the related arrangement structure, and is verified by experiments.

The present invention reduces the stray inductance in the substrate loop of the lower bridge arm through the third and fourth auxiliary potential regions and their related arrangement structures, greatly reduces the total stray inductance and is verified by experiments.

A plurality of power switches on the first power potential region and the third power potential region are arranged at intervals along the first direction, and the first power switches and the second power switches are arranged alternately along the first direction, and the installation and arrangement direction of each power switch is consistent with the second direction.

The first auxiliary potential region is arranged in parallel with the first direction, and is as close as possible to the first power switch on the first power potential region while being insulated from the first power potential region.

The second auxiliary connection device has two connection points, the first connection point is located on the first auxiliary potential region, and the second connection point is located on the second auxiliary potential region.

The first connection point is located on the end region of the first auxiliary potential zone in the opposite direction of the first direction, and the edge of the end region of the first auxiliary potential zone in the opposite direction of the first direction is aligned with the side of the first auxiliary potential zone in the opposite direction of the power semiconductor chip closest to the first direction.

The fourth auxiliary potential region is adjacent to the second power switch located in the middle of the third power potential region along the first direction, and is as close as possible to the second power switch on the third power potential region while being insulated from the third power potential region.

The third auxiliary connecting device has two connections, the first connection is located on the fourth auxiliary potential area, and the second connection is located on the second power switch in the middle of the third power potential area; the second power semiconductor chip is a semiconductor chip located in the middle of the two first power switches.

The third auxiliary potential region is adjacent to the fourth auxiliary potential region in the opposite direction of the second direction, and the third auxiliary potential region is as close as possible while being insulated from the fourth auxiliary potential region.

A first control terminal is provided on the second auxiliary potential region, and a second control terminal is provided on the second power potential region. The first control terminal and the second control terminal are used to control the switching of the power semiconductor chip in the first power switch on the first power potential region, and are as close as possible while ensuring insulation.

A third control terminal is provided on the third auxiliary potential region, and a fourth control terminal is provided on the fourth auxiliary potential region. The third control terminal and the fourth control terminal are used to control the switching of the power semiconductor chip in the first power switch on the third power potential region, and are as close as possible while ensuring insulation.

The second and third auxiliary connection devices are metal connection wires, resistors, inductors and other elements with connection functions.

2. The present invention also protects a power semiconductor module comprising the above-mentioned power semiconductor module substrate.

The beneficial effects of the present invention are:

The present invention improves the utilization rate of the power semiconductor module substrate by optimizing the control terminal position and chip layout; and optimizes and reduces the total stray inductance of the drive loop by arranging a separate auxiliary potential area and a connecting device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a switching circuit diagram of a power semiconductor chip.

FIG. 2 is a top view of a single substrate of the power semiconductor module.

FIG. 3 is a top view of the bridge arm chip driving circuit on the power semiconductor module substrate.

FIG. 4 is a bottom view of the bridge arm chip driving circuit on the power semiconductor module substrate.

Table 1 is the simulation results of the embodiment.

In the figure: power potential areas 10, 11, 12, 13, power switches 20, 21, power connection devices 30, power terminal elements 41, 42, 43, directions 51, 52, auxiliary potential areas 61, 62, 63, 64, auxiliary connection devices 70, 71, 72, control terminals 44, 45, 46, 47.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

As shown in FIG2 , the substrate 1 specifically implemented in the present invention includes four power potential regions 10, 11, 12, 13 and four auxiliary potential regions 61, 62, 63, 64. The four power potential regions 10, 11, 12, 13 are a second power potential region 11, a first power potential region 10, a third power potential region 12, and a fourth power potential region 13 arranged in sequence.

A plurality of power switches 20, 21 are installed on both the first power potential region 10 and the third power potential region 12, each of the power switches 20, 21 is composed of a plurality of power semiconductor chips, wherein the first power switch 20 is composed of a switch-controllable transistor chip, and the second power switch 21 is composed of a diode chip with unidirectional conduction characteristics, and a plurality of power semiconductor chips in each of the two power switches are connected in parallel with each other and connected to a power potential region adjacent to the power potential region where the power switch is located through a power connection device 30. Specifically, as shown in FIG1 , the two power switches 20, 21 on the first power potential region 10 are connected to the second power potential region 11 and the third power potential region 12 through a power connection device 30, and the power switches 20, 21 on the third power potential region 12 are connected to the fourth power potential region 13 through a power connection device 30.

A first auxiliary potential region 61 is arranged between the first power potential region 10 and the second power potential region 11, and a second auxiliary potential region 62 is arranged near the corner position of the second power potential region 11 in the opposite direction of the first direction 51 and the second direction 52. For each power switch 201, 202 arranged in the first power potential region 10, its control electrode 801, 802 is electrically connected to the first auxiliary potential region 61 through the first auxiliary connecting device 701, 702, and the first auxiliary potential region 61 is electrically connected to the second auxiliary potential region 62 through the second auxiliary connecting device 71.

A hollow area is set inside the third power potential area 12, and the third and fourth auxiliary potential areas 63, 64 are set in the hollow area. For each power switch 203, 204 arranged in the third power potential area 12, its control electrode 803, 804 is electrically connected to the third auxiliary potential area 63 through the first auxiliary connecting device 703, 704, and the power switch 214 is electrically connected to the fourth auxiliary potential area 64 through the auxiliary connecting device 72.

In the present invention, the multiple power potential regions 10-13 and the multiple power switches 20, 21 and multiple power terminals 41-43 mounted thereon are arranged in the following manner:

The first power potential region 10 , in a specific implementation, two first power switches 20 and two second power switches 21 are arranged on the first power potential region 10 , the bottoms of the power switches 20 , 21 are mounted on the first power potential region 10 , and the two types of first power switches 20 and second power switches 21 are alternately arranged along the first direction 51 .

The second power potential region 11 is arranged beside the first power potential region 10 , adjacent to the first power potential region 10 in the opposite direction of the second direction 52 , and is connected to the power electrodes on the top of the power switches 20 , 21 on the first power potential region 10 through the power connection device 30 .

The third power potential region 12 is arranged beside the first power potential region 10, adjacent to the first power potential region 10 in the second direction 52, and connected to the power electrodes on the top of the power switches 20, 21 on the first power potential region 10 through the power connection device 30. In a specific implementation, two first power switches 20 and two second power switches 21 are arranged on the third power potential region 12, the bottoms of the power switches 20, 21 are mounted on the third power potential region 12, and the two types of first power switches 20 and second power switches 21 are alternately arranged along the first direction 51.

The fourth power potential region 13 is arranged beside the first power potential region 10 , adjacent to the third power potential region 12 in the second direction 52 , and connected to the power electrodes on top of the power switches 20 , 21 on the third power potential region 12 via the power connection device 30 .

The present invention reduces the commutation loop area through the above commutation loop configuration, thereby reducing the overall stray inductance.

The first power potential region 10 has a first extension structure protruding beyond the third power potential region 12 and the fourth power potential region 13 in the first direction 51 and the opposite direction of the first direction 51. The first extension structure enables the first power potential region 10 to protrude beyond the third power potential region 12 and the fourth power potential region 13 in the first direction 51 and the opposite direction of the first direction 51, and the portion of the first extension structure protruding beyond the third power potential region 12 and the fourth power potential region 13 further extends along the second direction 52 toward the third power potential region 12 and the fourth power potential region 13 to form a second extension structure, and the extension length of the second extension structure is such that at least the extension portion exceeds the third power potential region 12; and the portions of the second extension structures on both sides protruding beyond the third power potential region 12 and the fourth power potential region 13 further extend toward the middle along the first direction 52/the opposite direction of the first direction 52 to form a third extension structure.

Two positive power terminals 41 are respectively arranged at the farthest ends of the two third extension structures. One negative power terminal 42 is arranged at the edge of the fourth power potential region 13 along the second direction 52, and the positive power terminal 41 and the negative power terminal 42 are arranged on the same straight line along the first direction 51. The AC power terminal 43 is arranged at the edge of the second power potential region 11 opposite to the second direction 52 and close to the edge of the first direction 51.

By setting the above-mentioned extension structure, the direction of the current flowing through the extension structure is opposite to the direction of the turn-off current flowing through the first first power potential region 10, the third third power potential region 12 and the fourth fourth power potential region 13 inside the extension structure, and the generated magnetic fields can offset each other, further reducing the overall stray inductance of the commutation loop. The extension structures arranged along the second direction 52 on both sides provide two symmetrical commutation loops, which can help reduce the difference in commutation paths of each chip due to the spatial position distribution for the power semiconductor chips arranged laterally along the first direction 51, thereby reducing the difference in stray inductance of each chip.

As shown in FIG. 2 , the present invention is equivalent to a half-bridge topology structure, and the upper and lower bridge arms are respectively composed of power semiconductor chips 20 and 21 of two rows of power switches installed thereon, and all power semiconductor chips of each row of power switches are connected in parallel.

As shown in FIG3 , for the power semiconductor chip of the first power switch 20 constituting the upper bridge arm, the power electrode at the bottom thereof is directly welded on the first power potential region 10 in the positive potential region, the top power electrode is connected to the second power potential region 11 and the third power potential region 12 in the AC potential region through the power connection device 30, and the control electrode 80 of the first power switch 20 is located on the top of the chip. The control terminal 44 of the upper bridge arm of the module is arranged on the second auxiliary potential region 62 adjacent to the second power potential region 11 in the opposite direction of the first direction 51 and the opposite direction of the second direction 52, and the control terminal 45 is directly arranged on the second power potential region 11, and the control terminal 45 provides a reference potential for the control terminal 44.

As shown in FIG4 , for the power semiconductor chip of the first power switch 20 constituting the lower bridge arm, the power electrode at the bottom is directly welded on the third power potential region 12 of the AC potential region, and the power electrode at the top is connected to the fourth power potential region 13 of the negative potential region through the power connection device 30, and the control electrode of the first power switch 20 is located at the bottom of the chip. The control terminals 46 and 47 of the lower bridge arm of the module are arranged inside the third power potential region 12, at the top of the power semiconductor chip of the lower bridge arm, i.e., in the reverse position of the direction 52.

Through the above configuration, the control terminals 44, 45 of the upper bridge arm and the AC power terminal 43, the control terminals 46, 47 of the lower bridge arm and the positive power terminal 41, the negative power terminal 42 have sufficient spacing to ensure the welding processing of the terminals, and the layout is compact, while being able to reduce the total stray inductance of the upper and lower bridge arm power semiconductor chip drive circuits.

Upper bridge arm: As shown in FIG3 , for the power semiconductor chips 201 and 202 constituting the upper bridge arm. First, a first auxiliary potential region 61 is provided above the power semiconductor chips 201 and 202, and the first auxiliary potential region 61 is in the shape of a long strip arranged along the first direction 51. Each power switch is provided with auxiliary connecting devices 701 and 702 of the same length and diameter, which are used to connect the first auxiliary potential region 61 and the control electrodes 801 and 802 of the power semiconductor chips 201 and 202 of the first power switch to ensure that the stray parameters of the path are consistent. Secondly, a second auxiliary connecting device 71 is used to connect the auxiliary potential region 61 and the second auxiliary potential region 62 where the control terminal 44 is located. The second auxiliary connecting device 71 has two connections 901 and 902, the first connection 901 is located on the first auxiliary potential region 61, and the second connection 902 is located on the second auxiliary potential region 62. As shown in FIG. 2 , the first connection 901 is arranged on one side of the first auxiliary potential region 61 along the first direction 51, i.e., the right side, and the right edge of the right side area of the first auxiliary potential region 61 is in the same straight line as the right side edge of the rightmost power semiconductor chip 202. The arrangement of the second auxiliary connection device 71 increases the stray inductance of the common part of the parallel chip drive circuit, which helps to reduce the difference in stray inductance of each chip drive circuit. In addition, another control terminal 45 is directly arranged on the second power potential region 11 to provide a reference potential for the control terminal 44. Through this arrangement, the control circuit of the power semiconductor chips 201 and 202 can use the power connection device 30 and the second power potential region 11 with small stray inductance, thereby further reducing the stray inductance of the control circuit.

According to the configuration of the embodiment, the present invention implements the simulation of the stray inductance of the driving circuit of each chip of the upper bridge arm using the Q3D software package of the Ansys software, and the simulation results are shown in the following Table 1. It can be seen from the results that for the chips belonging to the same bridge arm, the difference in the stray inductance of the control circuit does not exceed 35%, and the maximum stray inductance of the control circuit does not exceed 15nH.

Table 1

Chip location Stray inductance value (nH) Upper bridge chip 201 13.30 Upper bridge chip 202 8.52

Lower bridge arm: As shown in FIG4 , for the power semiconductor chips 203 and 204 constituting the lower bridge arm. First, the two control terminals 46 and 47 are arranged beside the two power semiconductor chips 203 and 204 of the first power switch 20 in the third power potential region 12 along the second direction 52. The two control terminals 46 and 47 are not at the same potential as the third power potential region 12, and the third and fourth auxiliary potential regions 63 and 64 insulated from each other are arranged to cooperate with the installation of the control terminals 46 and 47. The power semiconductor chips 203 and 204 of each power switch 20 are provided with first auxiliary connecting devices 703 and 704 of the same length and diameter, which are used to connect the third auxiliary potential region 63 and the control electrodes 803 and 804 of the power semiconductor chips 203 and 204.

A hollow area is provided inside the third power potential area 12, and the third and fourth auxiliary potential areas 63 and 64 are provided in the hollow area, which are isolated and insulated. The third auxiliary potential area 63 is provided with extension structures of unequal length in the positive and negative directions of the first direction 51, so as to cooperate with the connection of the first auxiliary connecting devices 703 and 704 of equal length. The stray inductance of the first auxiliary connecting device 70 is much larger than that of the third auxiliary potential area 63. The above measures can reduce the unevenness of the stray inductance from the control terminal 46 to the control electrodes 803 and 804 of the power semiconductor chips 203 and 204, reduce the stray inductance of the control loop, and reduce the total stray inductance of the upper and lower bridge arm power semiconductor chip drive loops.

The fourth auxiliary potential region 64 is arranged between the third auxiliary potential region 63 and the power semiconductor chip 214 of the second power switch 21, and the power semiconductor chip 214 of the second power switch 21 is located in the middle of the power semiconductor chips 203 and 204 of the two first power switches 20. The third auxiliary connection device 72 is used to connect the top power electrode of the power semiconductor chip 214 and the fourth auxiliary potential region 64. Through the above configuration, the control circuit of the power semiconductor chips 203 and 204 uses the power connection device 30 and the fourth power potential region 13 with small stray inductance, so as to further reduce the stray inductance of the control circuit and reduce the total stray inductance of the upper and lower bridge arm power semiconductor chip drive circuits.

According to the configuration of the embodiment, the present invention implements the simulation of the stray inductance of the driving circuit of each chip of the lower bridge arm using the Q3D software package of the Ansys software, and the simulation results are shown in the following Table 2. It can be seen from the results that for the chips belonging to the same bridge arm, the difference in the stray inductance of the control circuit does not exceed 35%, and the maximum stray inductance of the control circuit does not exceed 10nH.

Table 2

Chip location Stray inductance value (nH) Lower bridge arm chip 203 6.02 Lower bridge arm chip 204 9.31

It can be seen that the power semiconductor module provided by the present invention has the advantage of making the control loop stray inductance of each power switch chip small and uniform, and has its outstanding and significant technical effect.

Claims (8)

1. A power semiconductor module substrate characterized by:

Comprises four power potential areas (10, 11, 12, 13) and an auxiliary potential area, wherein the four power potential areas (10, 11, 12, 13) are a second power potential area (11), a first power potential area (10), a third power potential area (12) and a fourth power potential area (13) which are sequentially arranged at intervals along a second direction (52); a plurality of power switches (20, 21) are mounted on both the first power potential region (10) and the third power potential region (12); a hollowed-out area is arranged in the third power potential area (12), third and fourth auxiliary potential areas (63, 64) which are isolated and insulated are arranged in the hollowed-out area, the power semiconductor module substrate is equivalent to a half-bridge topological structure, an upper bridge arm and a lower bridge arm are respectively composed of power switches (20, 21) of two rows of power switches arranged on the upper bridge arm, and all power semiconductor chips of each row of power switches are mutually connected in parallel;

The plurality of power switches (20, 21) arranged on the first power potential region (10) comprises two types of first power switches (20) and second power switches (21), the plurality of power switches (20, 21) arranged on the third power potential region (12) comprises two types of first power switches (20) and second power switches (21), each power switch (20, 21) is composed of a plurality of power semiconductor chips, the first power switch (20) is composed of a switch-controllable transistor chip, and the second power switch (21) is composed of a diode chip with unidirectional conduction characteristics;

A first auxiliary potential area (61) is arranged between the first power potential area (10) and the second power potential area (11), and a second auxiliary potential area (62) is arranged near the corner position of the second power potential area (11) which is opposite along the first direction (51) and opposite along the second direction (52); for each first power switch (20) arranged in a first power potential region (10), its control electrode (801, 802) is electrically connected to the first auxiliary potential region (61) by means of a respective first auxiliary connection (701, 702), and the first auxiliary potential region (61) is electrically connected to the second auxiliary potential region (62) by means of a second auxiliary connection (71).

2. A power semiconductor module substrate according to claim 1, characterized in that:

For each first power switch (20) arranged in the third power potential region (12), its control electrode (803, 804) is electrically connected to the third auxiliary potential region (63) by means of a respective first auxiliary connection (703, 704), and a second power switch (21) in the middle on the third power potential region (12) is electrically connected to the fourth auxiliary potential region (64) by means of a third auxiliary connection (72).

3. A power semiconductor module substrate according to claim 1, characterized in that:

Only one potential region of the first auxiliary potential region (61) is provided between the first power potential region (10) and the second power potential region (11), and no passive elements and other potential regions are arranged; and, the first auxiliary potential region (61) is electrically connected only with the control electrode (801, 802) of each first power switch (20) on the first power potential region (10) through the first auxiliary connection means (701, 702) and with the second auxiliary potential region (62) through the second auxiliary connection means (71).

4. A power semiconductor module substrate according to claim 1, characterized in that:

The power semiconductor chips in each power switch (20, 21) are connected in parallel to each other and to a power potential region adjacent to the power potential region in which they are located by means of a power connection device (30).

5. A power semiconductor module substrate according to claim 1, characterized in that:

The plurality of power switches (20, 21) on the first power potential region (10) and the third power potential region (12) are arranged at intervals along a first direction (51), and the first power switches (20) and the second power switches (21) are alternately arranged along the first direction (51), and the mounting arrangement direction of each power switch (20, 21) coincides with the second direction (52).

6. A power semiconductor module substrate according to claim 1, characterized in that:

the first auxiliary potential region (61) is arranged in a parallel first direction (51) and is made as close as possible to the first power switch (20) on the first power potential region (10) when the first auxiliary potential region (61) is insulated from the first power potential region (10).

7. A power semiconductor module substrate according to claim 1, characterized in that:

The fourth auxiliary potential region (64) is adjacent to the second power switch (21) located in the middle on the third power potential region (12) in the first direction (52), and the fourth auxiliary potential region (64) is made to be as close as possible to the second power switch (21) on the third power potential region (12) while being insulated from the third power potential region (12).

8. A power semiconductor module, characterized by:

a power semiconductor module substrate according to any of the preceding claims 1-7.