CN107968051B - Dielectric layer rough grinding method, memory manufacturing method, memory and electronic equipment - Google Patents
Dielectric layer rough grinding method, memory manufacturing method, memory and electronic equipment Download PDFInfo
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- CN107968051B CN107968051B CN201711194490.3A CN201711194490A CN107968051B CN 107968051 B CN107968051 B CN 107968051B CN 201711194490 A CN201711194490 A CN 201711194490A CN 107968051 B CN107968051 B CN 107968051B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
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Abstract
The invention provides a rough grinding method of a multilayer interlayer dielectric layer, a manufacturing method of a three-dimensional memory, the three-dimensional memory and electronic equipment. The rough grinding method of the multilayer interlayer dielectric layer comprises the following steps: providing a target wafer on which a plurality of interlayer dielectric layers are deposited; and carrying out rough grinding on the target wafer by taking the motor torque of the grinding equipment as a basis until the target dielectric layer is ground. Compared with the coarse grinding method based on grinding duration in the prior art, the coarse grinding method for the multilayer interlayer dielectric layer provided by the invention can effectively improve the grinding accuracy, improve the controllability of a coarse grinding process and reduce the workload of subsequent steps such as fine grinding.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a rough grinding method of a multilayer interlayer dielectric layer, a manufacturing method of a three-dimensional memory, the three-dimensional memory and electronic equipment.
Background
With the increasing demands for integration and storage capacity, memory technology is advancing, and as the size of two-dimensional planar memories is reduced to the order of tens of nanometers (16nm, 15nm and even 14nm), each memory cell becomes very small, so that only a few electrons exist in each cell, the material has a reduced ability to control electrons, and the resulting cross-talk problem makes it difficult and uneconomical to further reduce the size of the memory cell. Therefore, a three-dimensional memory has come to be a new product based on a planar memory, and the storage capacity is expanded by three-dimensional stacking of storage units.
The three-dimensional memory is generally manufactured by forming an active layer on a substrate, the active layer having a three-dimensional memory cell and a peripheral circuit therein, forming a plurality of Interlayer Dielectric layers (ILD) and metal wiring layers on the active layer, and electrically connecting the metal wiring and the three-dimensional memory cell and the peripheral circuit in the active layer by using a conductive via penetrating through the ILD layer.
The planar surface ILD layer facilitates subsequent deposition and patterning of metal wiring layers, electrical isolation between metal wiring and underlying semiconductor devices, formation of multiple metal wiring interconnections, and improved mechanical strength and reliability of semiconductor devices due to the absence of voids and other defects. In order to form a planar ILD layer, after the deposition of the ILD layer, the ILD layer is further subjected to a Chemical Mechanical Polishing (CMP).
CMP can be classified into coarse grinding and fine grinding, and in actual production, it is often necessary to perform stepwise grinding in combination with the coarse grinding and the fine grinding to gradually grind to a target thickness. The rough grinding is based on time, for example, grinding can be started by setting a designated grinding duration and grinding parameters, and grinding is stopped after the time is over. Because the thickness and height of each dielectric layer in the multi-layer interlayer dielectric layer are not completely consistent between wafers, between batches and between batches, the grinding method often causes the conditions of insufficient grinding or excessive grinding, the process accuracy is poor, the difficulty is brought to the subsequent steps of fine grinding and the like, and the workload of the subsequent grinding step is increased.
In view of the above problems, there is a need to provide a rough grinding process for a multi-layer interlayer dielectric layer, so as to improve the precision of the rough grinding process, reduce the workload of the subsequent steps, improve the production efficiency and improve the product quality.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a rough grinding method of a multilayer interlayer dielectric layer, a manufacturing method of a three-dimensional memory, the three-dimensional memory and electronic equipment, so as to improve the precision of a rough grinding process, reduce the workload of subsequent steps, improve the production efficiency and improve the product quality.
In a first aspect, the present invention provides a rough grinding method for a multi-layered interlayer dielectric layer, including: providing a target wafer on which a plurality of interlayer dielectric layers are deposited;
and carrying out rough grinding on the target wafer by taking the motor torque of the grinding equipment as a basis until the target dielectric layer is ground.
In a modified embodiment of the present invention, the rough grinding of the target wafer based on the motor torque of the polishing apparatus until the target dielectric layer is polished comprises:
placing the target wafer into grinding equipment for coarse grinding;
determining motor torque of a driving motor of a target grinding disc, wherein the target grinding disc is a grinding disc for grinding a target wafer in grinding equipment;
determining a dielectric layer currently being polished according to a motor torque of the driving motor;
if the dielectric layer currently being polished is the target dielectric layer, the polishing is stopped.
In one modified embodiment of the present invention, the determining of the motor torque of the drive motor of the target polishing disk includes:
collecting a driving current signal of a driving motor of a target grinding disc;
determining a motor torque of the drive motor from the drive current signal.
In one modified embodiment of the present invention, the multilayered interlayer dielectric layer includes: multiple dielectric layers with different friction resistances or multiple dielectric layers with different change trends of friction resistance along with the grinding time.
In one modified embodiment of the present invention, the multilayered interlayer dielectric layer includes: a silicon nitride layer and a silicon oxide layer.
In a modified embodiment of the present invention, the determining a dielectric layer currently being polished according to a motor torque of the driving motor includes:
and determining the dielectric layer currently being ground according to the variation trend of the motor torque of the driving motor.
In a modified embodiment of the present invention, the number of the interlayer dielectric layers is two, and the two interlayer dielectric layers are a silicon nitride layer and a silicon oxide layer;
the determining the dielectric layer currently being ground according to the variation trend of the motor torque of the driving motor comprises the following steps:
if the change trend of the motor torque is gradually reduced, judging that the dielectric layer which is currently ground is a silicon oxide layer;
if the change trend of the motor torque is gradually increased, judging that the dielectric layer which is currently ground is a silicon nitride layer;
if the change trend of the motor torque is changed from gradual reduction to gradual increase, the dielectric layer which is currently polished is judged to be the interface of the silicon oxide layer and the silicon nitride layer.
In a second aspect, the present invention provides a method for manufacturing a three-dimensional memory, including:
forming an active layer on a substrate, the active layer including a three-dimensional memory cell and a peripheral circuit;
forming a multi-layered interlayer dielectric layer over the active layer;
the coarse grinding method of the multilayer interlayer dielectric layer is adopted to perform coarse grinding on the multilayer interlayer dielectric layer;
carrying out fine grinding on the multi-layer interlayer dielectric layer after coarse grinding by adopting a fine grinding process;
forming a metal wiring layer on the finely ground multilayer interlayer dielectric layer;
and forming contact lines of the metal wiring in the metal wiring layer, the three-dimensional memory cells in the active layer and peripheral circuits.
In a third aspect, the invention provides a three-dimensional memory, which is manufactured according to the manufacturing method of the three-dimensional memory provided in the second aspect of the invention.
In a fourth aspect, the invention provides an electronic device, in which the three-dimensional memory provided by the invention is disposed.
In view of the above, the first aspect of the present invention provides a method for rough grinding a multi-layered interlayer dielectric layer, in which a target wafer is rough ground based on a motor torque of a grinding apparatus, so as to grind the target wafer to a target dielectric layer more accurately. Compared with the coarse grinding method based on the grinding duration in the prior art, the method has the advantages that the grinding accuracy can be effectively improved, the controllability of a coarse grinding process is improved, and the workload of subsequent steps such as fine grinding is reduced; in addition, the method can improve the precision of rough grinding, so that a smoother interlayer dielectric layer can be prepared, the deposition and patterning of a metal wiring layer are facilitated, the electrical insulation between the metal wiring and a semiconductor device on the lower layer is facilitated, the formation of multiple metal wiring interconnections is facilitated, and the mechanical strength and the reliability of a final product are further effectively improved.
The method for fabricating a three-dimensional memory according to the second aspect of the present invention, which uses the rough grinding method for the multi-layered interlayer dielectric layer according to the first aspect of the present invention, has the same advantages as the rough grinding method for the multi-layered interlayer dielectric layer.
The three-dimensional memory provided by the third aspect of the invention is manufactured according to the manufacturing method of the three-dimensional memory provided by the second aspect of the invention, and has the same beneficial effects with the manufacturing method of the three-dimensional memory, and has better reliability compared with the existing three-dimensional memory.
The three-dimensional memory provided by the invention has the same beneficial effects as the three-dimensional memory.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a flow chart illustrating a method for rough grinding a dielectric layer between layers according to an embodiment of the invention;
fig. 2 is a flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.
In addition, the terms "first" and "second" are used to distinguish different objects, and are not used to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Embodiments of the present invention provide a rough grinding method for a multi-layer interlayer dielectric layer, a manufacturing method for a three-dimensional memory, and an electronic device, and embodiments of the present invention are described below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of a rough grinding method for a multi-layered interlayer dielectric layer according to an embodiment of the invention is shown. As shown in fig. 1, the rough grinding method of the multi-layered interlayer dielectric layer comprises the following steps:
step S101: a target wafer having a plurality of interlevel dielectric layers deposited thereon is provided.
The target wafer refers to a wafer to be roughly ground, wherein three-dimensional memory cells and peripheral circuits are formed, and a multilayer interlayer dielectric layer is deposited.
In a modified implementation of the embodiment of the present invention, the target wafer is a wafer on which a three-dimensional NAND memory is to be fabricated.
Step S102: and carrying out rough grinding on the target wafer by taking the motor torque of the grinding equipment as a basis until the target dielectric layer is ground.
In a modified embodiment of the present invention, the rough grinding of the target wafer based on the motor torque of the polishing apparatus until the target dielectric layer is polished comprises:
placing the target wafer into grinding equipment for coarse grinding;
determining motor torque of a driving motor of a target grinding disc, wherein the target grinding disc is a grinding disc for grinding a target wafer in grinding equipment;
determining a dielectric layer currently being polished according to a motor torque of the driving motor;
if the dielectric layer currently being polished is the target dielectric layer, the polishing is stopped.
The polishing apparatus may be a CMP apparatus manufactured by the application materials company (AMAT), such as LK Reflection or LK Prime.
Specifically, the determining of the motor torque of the drive motor of the target abrasive disc includes:
collecting a driving current signal of a driving motor of a target grinding disc;
determining a motor torque of the drive motor from the drive current signal.
In a modified embodiment of the present invention, the multilayered interlayer dielectric layer includes: multiple dielectric layers with different friction resistances or multiple dielectric layers with different change trends of friction resistance along with the grinding time.
Specifically, the multilayered interlayer dielectric layer may include: a silicon nitride layer and a silicon oxide layer.
Because different dielectric layer materials have different friction forces or friction force variation trends during grinding, and a driving current signal of a driving motor of a grinding disc changes along with the variation of the friction force, the motor torque calculated according to the driving current signal of the driving motor can intuitively reflect the magnitude or the variation trend of the friction force of the dielectric layer materials during the grinding process, for example, the friction force of a silicon oxide material is reduced along with the increase of the grinding time during the grinding process, namely the motor torque of the driving motor is correspondingly reduced; in the process of polishing silicon nitride material, the friction force will increase along with the increase of the polishing time, that is, the motor torque of the driving motor will also increase correspondingly; therefore, whether the dielectric layer currently polished is silicon oxide or silicon nitride can be judged according to the variation trend of the motor torque of the driving motor. In addition, the friction force of different dielectric layer materials in the grinding process may also be different, which can be reflected by the magnitude of the motor torque, so as to determine the material of the dielectric layer currently ground according to the motor torque of the driving motor.
Based on the above description, in a modified embodiment of the present invention, the determining a dielectric layer currently being polished according to a motor torque of the driving motor includes:
and determining the dielectric layer currently being ground according to the variation trend of the motor torque of the driving motor.
Taking the number of the interlayer dielectric layers as two layers, i.e. a silicon nitride layer and a silicon oxide layer as an example, the determining the dielectric layer currently being polished according to the variation trend of the motor torque of the driving motor may include:
if the change trend of the motor torque is gradually reduced, judging that the dielectric layer which is currently ground is a silicon oxide layer;
if the change trend of the motor torque is gradually increased, judging that the dielectric layer which is currently ground is a silicon nitride layer;
if the change trend of the motor torque is changed from gradual reduction to gradual increase, the dielectric layer which is currently polished is judged to be the interface of the silicon oxide layer and the silicon nitride layer.
As described above, in the rough grinding method for a dielectric layer between layers according to the embodiments of the present invention, the target wafer is rough ground based on the motor torque of the grinding apparatus, so as to more precisely grind the target dielectric layer. Compared with the coarse grinding method based on the grinding duration in the prior art, the method has the advantages that the grinding accuracy can be effectively improved, the controllability of a coarse grinding process is improved, and the workload of subsequent steps such as fine grinding is reduced; in addition, the method can improve the precision of rough grinding, so that a smoother interlayer dielectric layer can be prepared, the deposition and patterning of a metal wiring layer are facilitated, the electrical insulation between the metal wiring and a semiconductor device on the lower layer is facilitated, the formation of multiple metal wiring interconnections is facilitated, and the mechanical strength and the reliability of a final product are further effectively improved.
Referring to fig. 2, a flowchart of a three-dimensional memory manufacturing method according to an embodiment of the invention is shown. As shown in fig. 2, the method for manufacturing the three-dimensional memory includes the following steps:
step S201: an active layer including a three-dimensional memory cell and peripheral circuitry is formed on a substrate.
In the embodiments of the present invention, a substrate is first provided, and the material of the substrate may include bulk silicon (bulk Si), bulk germanium (bulk ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate, such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations thereof. In one embodiment of the present invention, a substrate of silicon-containing material, such as Si, SOI, SiGe, or SiC, is used for compatibility with existing IC fabrication processes.
In this step, the method for forming the peripheral circuit may adopt any one of the methods for manufacturing the peripheral circuit provided in the prior art, which is not described herein again, for example, in an alternative implementation of the embodiment of the present invention, the main process for forming the peripheral circuit may include: and forming a high-voltage region P well and an N well, a high-voltage region gate oxide layer, a shallow trench isolation region, a low-voltage region P well and an N well, a low-voltage region gate oxide layer, a polysilicon gate, tungsten silicide, a drain region and a silicon oxide protective layer.
In this step, the method for forming the three-dimensional memory cell may adopt any one of the methods for manufacturing a three-dimensional memory cell provided in the prior art, for example, a method for manufacturing a 3D NAND flash memory (such as BiCS, TCAT, and other manufacturing processes), a method for manufacturing a 3D NOR flash memory, a method for manufacturing a DRAM memory, a method for manufacturing a 3D Xpoint flash memory, and the like, so as to manufacture a corresponding form and a three-dimensional memory cell, which is not particularly limited in the embodiment of the present invention.
In a modified implementation of the embodiment of the present invention, the main process for forming the three-dimensional memory cell may include:
forming an alternating stacked ladder structure of silicon nitride and silicon oxide;
forming vertical channel holes in the alternately stacked stepped structures;
and depositing silicon oxide, silicon nitride, silicon oxide and polysilicon in the channel hole to form the three-dimensional storage unit.
It should be noted that, in order to avoid interference between the three-dimensional memory cell and the peripheral circuit, the first isolation layer may be formed on the whole surface after the three-dimensional memory cell is formed before the peripheral circuit is formed, and the first isolation layer may be planarized on the whole surface; wherein, the first isolation layer can be formed by depositing oxide such as silicon oxide, and the overall planarization can be realized by adopting a chemical mechanical polishing process. It is understood that the first isolation layer may also be formed together when the alternating stacked step structure is formed, and may be planarized entirely after being formed.
Step S202: a multi-layered interlayer dielectric layer is formed over the active layer.
The multilayer interlayer dielectric layer may be two interlayer dielectric layers or more than three interlayer dielectric layers. The material of the interlayer dielectric layer can be silicon oxide, silicon nitride and other dielectrics. The interlayer dielectric may be formed by a Deposition process, for example, by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a Furnace tube Chemical Vapor Deposition (Fur CVD) method.
Step S203: the multi-layer interlayer dielectric layer is subjected to rough grinding by adopting the rough grinding method of the multi-layer interlayer dielectric layer provided by the invention.
In this step, the rough grinding method for the multi-layer interlayer dielectric layer provided in the foregoing embodiment may be adopted to realize the rough grinding for the multi-layer interlayer dielectric layer, and relevant contents may be understood with reference to the description of the embodiment of the rough grinding method for the multi-layer interlayer dielectric layer, which is not described herein again.
Step S204: and carrying out fine grinding on the multi-layer interlayer dielectric layer after coarse grinding by adopting a fine grinding process.
Step S205: and forming a metal wiring layer on the finely ground multilayer interlayer dielectric layer.
Step S206: and forming contact lines of the metal wiring in the metal wiring layer, the three-dimensional memory cells in the active layer and peripheral circuits.
As described above, the flow of the method for manufacturing a three-dimensional memory according to the embodiment of the present invention is illustrated, and the method for manufacturing a three-dimensional memory according to the embodiment of the present invention has the same beneficial effects as the method for rough grinding a multi-layered interlayer dielectric layer according to the same inventive concept as the method for rough grinding a multi-layered interlayer dielectric layer.
In the embodiment, a method for manufacturing a three-dimensional memory is provided, and accordingly, the invention also provides the three-dimensional memory manufactured according to the method for manufacturing the three-dimensional memory.
In a further variation of the embodiment of the present invention, the three-dimensional memory may further be provided with a data interface, such as SATA, m.2, PCI-E, mSATA, etc., to facilitate communication with external electronic devices.
The invention also provides electronic equipment, wherein the three-dimensional memory provided by the invention is arranged in the electronic equipment, and the electronic equipment can be any equipment capable of storing data, such as a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server and the like. The electronic device provided by the embodiment of the invention has the same beneficial effects as the three-dimensional memory due to the arrangement of the three-dimensional memory provided by the invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an alternate embodiment," "an example," "a specific example," or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (7)
1. A rough grinding method for a multilayer interlayer dielectric layer is characterized by comprising the following steps:
providing a target wafer on which a plurality of interlayer dielectric layers are deposited;
placing the target wafer into grinding equipment for coarse grinding;
determining motor torque of a driving motor of a target grinding disc, wherein the target grinding disc is a grinding disc for grinding a target wafer in grinding equipment;
determining a dielectric layer currently being polished according to a motor torque of the driving motor;
if the dielectric layer which is currently being polished is the target dielectric layer, stopping polishing;
wherein the determining a dielectric layer currently being polished according to a motor torque of the driving motor comprises: determining a dielectric layer currently being polished according to the variation trend of the motor torque of the driving motor;
wherein, if the number of the interlayer dielectric layers is two, namely a silicon nitride layer and a silicon oxide layer, the determining the dielectric layer currently being polished according to the variation trend of the motor torque of the driving motor comprises:
if the change trend of the motor torque is gradually reduced, judging that the dielectric layer which is currently ground is a silicon oxide layer;
if the change trend of the motor torque is gradually increased, judging that the dielectric layer which is currently ground is a silicon nitride layer;
if the change trend of the motor torque is changed from gradual reduction to gradual increase, the dielectric layer which is currently polished is judged to be the interface of the silicon oxide layer and the silicon nitride layer.
2. The method of rough grinding of inter-layer dielectric layers as claimed in claim 1, wherein the determining of the motor torque of the drive motor of the target grinding disk comprises:
collecting a driving current signal of a driving motor of a target grinding disc;
determining a motor torque of the drive motor from the drive current signal.
3. The rough grinding method of the multilayer interlayer dielectric layer according to claim 1, wherein the multilayer interlayer dielectric layer comprises: multiple dielectric layers with different friction resistances or multiple dielectric layers with different change trends of friction resistance along with the grinding time.
4. The rough grinding method of the multilayer interlayer dielectric layer according to claim 3, wherein the multilayer interlayer dielectric layer comprises: a silicon nitride layer and a silicon oxide layer.
5. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
forming an active layer on a substrate, the active layer including a three-dimensional memory cell and a peripheral circuit;
forming a multi-layered interlayer dielectric layer over the active layer;
rough grinding the multilayered interlayer dielectric layer using the method of rough grinding the multilayered interlayer dielectric layer of any one of claims 1 to 4;
carrying out fine grinding on the multi-layer interlayer dielectric layer after coarse grinding by adopting a fine grinding process;
forming a metal wiring layer on the finely ground multilayer interlayer dielectric layer;
and forming contact lines of the metal wiring in the metal wiring layer, the three-dimensional memory cells in the active layer and peripheral circuits.
6. A three-dimensional memory fabricated according to the method of claim 5.
7. An electronic device characterized in that the three-dimensional memory according to claim 6 is provided therein.
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