CN107968071B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: and forming a stress epitaxial layer in a source/drain region in the NMOS region, wherein the stress epitaxial layer comprises a second stress epitaxial layer with a first width positioned at the bottom and a third stress epitaxial layer positioned on the second stress epitaxial layer, the third stress epitaxial layer comprises a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width positioned above the top surface of the second gap wall from bottom to top, the first width is smaller than the second width, and the second width is smaller than the third width, so that the top of the stress epitaxial layer is enlarged, the contact area is larger, the stress epitaxial layer has lower external resistance, and furthermore, because the volume of the bottom stress epitaxial layer is not increased, the short channel effect is well controlled, and the performance and the yield of the device are improved.

Description

A semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

In the field of semiconductor technology, with the rapid development of nanofabrication technology, the feature size of transistors has entered the nanoscale. The method of improving the performance of the current mainstream silicon CMOS devices by scaling down is subject to more and more physical and technological constraints. In order to improve the performance of NMOS and PMOS transistors in CMOS devices, stress engineering has received increasing attention in the industry.

Stress affects the mobility of carriers in semiconductors. In general, the mobility of electrons in silicon increases with increasing tensile stress along the direction of electron migration and decreases with increasing compressive stress. Conversely, the mobility of positively charged holes in silicon increases with increasing compressive stress in the direction of hole movement and decreases with increasing tensile stress. Therefore, the hole mobility of PMOS and the electron mobility of NMOS can be improved respectively by introducing appropriate compressive stress and tensile stress in the channel, for example, the performance of PMOS can be improved by silicon germanium (SiGe) process, and the performance of PMOS can be improved by silicon-phosphorus (SiP) process. ) process to improve the performance of NMOS.

Source/drain (S/D) epitaxy profiles are critical to improving the performance and yield of FinFET devices. For the preparation process of the SiP stress epitaxy layer of NMOS devices, the SiP merged epitaxy layer is not the ideal structure we want, which is not conducive to the improvement of device performance, but if the design requires lower external resistance (external resistance), Then, the stress epitaxial layer needs to have a larger volume, so it is necessary to reasonably balance the volume and profile of the epitaxy, thereby improving the performance of the device. In addition, the larger SiP epitaxy is not conducive to the control of the short-channel effect, because the lateral diffusion ability of phosphorus is too poor.

Therefore, it is necessary to propose a semiconductor device and its fabrication method to reasonably balance the volume and profile of the source/drain epitaxy, thereby further improving the performance of the device.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In view of the deficiencies of the prior art, the first embodiment of the present invention provides a method for manufacturing a semiconductor device, including:

A semiconductor substrate is provided, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;

forming a first dummy gate structure and a second dummy gate structure spanning a part of the first fin structure and a part of the second fin structure in the PMOS region and the NMOS region, respectively;

growing a first stress epitaxial layer in the source/drain regions of the first fin structure on both sides of the first dummy gate structure;

forming first spacers on sidewalls of the second fin structure on both sides of the second dummy gate structure;

performing a first etch back on the exposed source/drain regions of the second fin structure to remove part of the second fin structure to form a first groove;

thinning the thickness of the first spacer to expand the width of the first groove to a first width;

A second stressed epitaxial layer is grown on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stressed epitaxial layer is the first width ;

forming second spacers on sidewalls of the second fin structure and the second stressed epitaxial layer;

a second etch back to remove part of the second stress epitaxial layer to form a second groove;

reducing the thickness of the second spacer to expand the width of the second groove to a second width;

A third stressed epitaxial layer is grown on the surface of the second stressed epitaxial layer to fill the second recess and overflow to the top surface of the remaining second spacers, wherein the second recess is The width of the third stressed epitaxial layer in the groove is the second width, and the third stressed epitaxial layer located above the top surface of the second spacer has a third width, wherein the first width is smaller than The second width is smaller than the third width.

Further, after forming the first dummy gate structure and the second dummy gate structure, and before forming the first stress epitaxial layer, the following steps are further included:

depositing a first layer of spacer material to cover the PMOS region and the NMOS region;

forming a patterned first photoresist layer to cover the NMOS region and expose the PMOS region;

Using the patterned first photoresist layer as a mask, etching and removing part of the first spacer material layer located on the top surface of the first fin structure and on the surface of the semiconductor substrate;

Etching back removes part of the first fin structure in the source/drain regions on both sides of the first dummy gate structure and part of the first spacer material layer on the first fin structure.

Further, after forming the first stressed epitaxial layer and before forming the first spacer, the method further includes a step of: performing an oxidation treatment to form a first oxide layer on the exposed surface of the first stressed epitaxial layer.

Further, the method for forming the first spacer includes the following steps:

depositing a second layer of spacer material to cover the PMOS region and the NMOS region;

forming a patterned second photoresist layer to cover the PMOS region and expose the NMOS region;

Etching and removing the first spacer material layer and the second spacer material layer on the top surface of the second fin structure and the surface of the semiconductor substrate in the NMOS region, so that the second fin structure is The first spacer is formed on the sidewall of the fin, and part of the top surface of the second fin structure is exposed.

Further, after the first etching back step and before reducing the thickness of the first spacer, the method further includes a step of: oxidizing the exposed surface of the second fin structure to form a second oxide layer , and after the step of reducing the thickness of the second spacer, the second oxide layer is pre-cleaned and removed.

Further, the process of forming the second spacer includes the following steps:

depositing a third layer of spacer material to cover the PMOS region and the NMOS region;

forming a patterned third photoresist layer to cover the PMOS region and expose the NMOS region;

Etching and removing part of the third spacer material layer on the top surface of the second stressed epitaxial layer and the semiconductor substrate in the NMOS region, so that the second fin structure and the second stress The second spacer is formed on the sidewall of the epitaxial layer.

Further, the thickness of the first spacer is in the range of 60-120 angstroms.

Further, the depth range of the first etching back is 20-40 nm.

Further, after the first spacer is thinned, the thickness of the remaining first spacer ranges from 2 to 6 nm.

Further, after the second spacer is thinned, the thickness of the remaining second spacer ranges from 2 to 6 nm.

Further, the depth range of the second etching back is 10-20 nm.

Further, the materials of the second stressed epitaxial layer and the third stressed epitaxial layer both include SiP.

Further, the thinning of the first spacer and the thinning of the second spacer are realized by using a wet etching method.

Further, the wet etching uses an etchant including phosphoric acid.

Further, the method also includes:

forming a contact hole etch stop layer on surfaces of the semiconductor substrate, the first stressed epitaxial layer, the third stressed epitaxial layer and the second spacer;

An interlayer dielectric layer is deposited on the contact hole etch stop layer, and the interlayer dielectric layer is planarized.

Further, the material of the first stressed epitaxial layer includes SiGe.

The second embodiment of the present invention provides a semiconductor device, including:

a semiconductor substrate, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;

A first gate structure and a second gate structure spanning a part of the first fin structure and a part of the second fin structure are respectively formed in the PMOS region and the NMOS region;

A first stress epitaxial layer is formed in the source/drain regions of the first fin structure on both sides of the first gate structure;

A second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a The third stress epitaxial layer with three widths, wherein the first width is smaller than the second width, and the second width is smaller than the third width;

Spacers are formed on sidewalls of the second fin structure, the second stressed epitaxial layer, and the third stressed epitaxial layer of the second width.

Further, a first oxide layer is also formed on the surface of the first stressed epitaxial layer.

Further, a spacer material layer is formed on the surface of the first oxide layer, the sidewall of the first fin structure and the surface of the semiconductor substrate in the PMOS region.

Further, the materials of the second stressed epitaxial layer and the third stressed epitaxial layer both include SiP.

Further, it also includes:

A contact hole etch stop layer is formed on the surface of the semiconductor substrate, the first stressed epitaxial layer, the third stressed epitaxial layer and the spacer;

An interlayer dielectric layer is deposited on the contact hole etch stop layer.

Further, the material of the first stressed epitaxial layer includes SiGe.

The third embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

According to the manufacturing method of the present invention, the spacer is used as a guide when the stress epitaxial layer is grown in the source/drain regions of the NMOS region, so no merged epitaxial layer (merged epitaxy) is formed. The contact area is larger, so the stress epitaxial layer has lower external resistance, and since the volume of the bottom stress epitaxial layer is not substantially increased, the short channel effect is also well controlled, so , according to the manufacturing method of the present invention, the volume and contour of the source/drain stress epitaxial layer are reasonably balanced, and the performance and yield of the device are improved.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

1 to 18 are cross-sectional views of structures formed by related steps of a method for manufacturing a semiconductor device in an embodiment of the present invention;

FIG. 19 shows a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 20 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

For a thorough understanding of the present invention, detailed steps and detailed structures will be proposed in the following description to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Example 1

In view of the problems existing in the prior art, the present invention provides a method for manufacturing a semiconductor device, as shown in FIG. 20 , which mainly includes the following steps:

Step S201, providing a semiconductor substrate, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;

Step S202, forming a first dummy gate structure and a second dummy gate structure spanning part of the first fin structure and part of the second fin structure in the PMOS region and the NMOS region respectively;

Step S203, growing a first stress epitaxial layer in the source/drain regions of the first fin structure on both sides of the first dummy gate structure;

Step S204, forming first spacers on both sidewalls of the second fin structure on both sides of the second dummy gate structure;

Step S205, performing a first etch back on the exposed source/drain regions of the second fin structure to remove part of the second fin structure to form a first groove;

Step S206, reducing the thickness of the first spacer to expand the width of the first groove to a first width;

Step S207, growing a second stress epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stress epitaxial layer is the first width;

Step S208, forming second spacers on the sidewalls of the second fin structure and the second stress epitaxial layer;

Step S209, a second etch back to remove part of the second stress epitaxial layer to form a second groove;

Step S210, reducing the thickness of the second spacer to expand the width of the second groove to a second width;

Step S211, growing a third stress epitaxial layer on the surface of the second stress epitaxial layer to fill the second groove and overflow the top surface of the remaining second spacers, wherein the The width of the third stressed epitaxial layer in the second groove is the second width, and the third stressed epitaxial layer located above the top surface of the second spacer has a third width, wherein the first A width is smaller than the second width, and the second width is smaller than the third width.

According to the manufacturing method of the present invention, a spacer is used as a guide when growing the stressed epitaxial layer in the source/drain regions of the NMOS region, so that a merged epitaxial layer is not formed. In addition, since the top of the stressed epitaxial layer is enlarged, the contact The area of the stress epitaxial layer is larger, so the stress epitaxial layer has lower external resistance. Furthermore, since the volume of the stress epitaxial layer at the bottom is not substantially increased, the short channel effect is also well controlled. Therefore, according to the present invention The manufacturing method reasonably balances the volume and contour of the source/drain stress epitaxial layer, and improves the performance and yield of the device.

Hereinafter, the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to FIGS. 1 to 18 , wherein FIGS. 1 to 18 illustrate the formation of Cutaway view of the structure.

Specifically, first, as shown in FIG. 1 , a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a first semiconductor substrate 100 is formed on the PMOS region and the NMOS region respectively. Fin structure 1011 and second fin structure 1012 .

Specifically, the semiconductor substrate 100 may be at least one of the following mentioned materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes these semiconductor components multi-layer structures, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI) Wait. In this embodiment, the semiconductor substrate 100 is preferably a silicon substrate.

A first fin structure 1011 is formed on the semiconductor substrate 100 in the PMOS region, and a second fin structure 1012 is formed on the semiconductor substrate 100 in each of the NMOS regions.

In one example, the method of forming the first fin structure 1011 and the second fin structure 1012 includes the following steps:

A patterned mask layer is formed on the surface of the semiconductor substrate 100, and the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including fins The width, length and position, etc. of the patterned mask layer are used as a mask, and the semiconductor substrate 100 is etched to form the first fin structure 1011 and the second fin structure 1012 . The mask layer can generally include any of several mask materials including, but not limited to, hard mask materials and photoresist mask materials. The above-mentioned etching may be performed by methods such as dry etching or wet etching, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods. A single etching method may also be used, or more than one etching method may be used.

It should be noted that, the methods of forming the first fin structure 1011 and the second fin structure 1012 are only exemplary, and are not limited to the above methods.

The widths of the fin structures are all the same, or the fins are divided into a plurality of fin structure groups with different widths, and the lengths of the fin structures may also be different.

An isolation structure 102 is also formed on the semiconductor substrate 100. The isolation structure 102 may be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. In this embodiment, the isolation structure 102 is preferably shallow trench isolation structure. The top surface of the isolation structure 102 is lower than the top surfaces of the first fin structure 1011 and the second fin structure 1012 . Various well structures are also formed in the semiconductor substrate 100 , for example, an N-type well is formed in the PMOS region, and a P-type well is formed in the NMOS region, which are omitted from the illustration for simplicity.

Next, as shown in FIG. 3 , a first dummy gate structure and a second dummy gate are formed in the PMOS region and the NMOS region respectively across a part of the first fin structure 1011 and a part of the second fin structure 1012 structure.

Exemplarily, both the first dummy gate structure and the second dummy gate structure include a dummy gate dielectric layer 1031 and a dummy gate material layer 1032 .

It should be pointed out that the term "span" used in the present invention, for example, spans the gate structure (eg, the dummy gate structure) of the fin structure (eg, the first fin structure, the second fin structure, etc.) , means that a gate structure is formed on both the upper surface and the side surface of a part of the fin structure, and the gate structure is also formed on a part of the surface of the semiconductor substrate.

In one example, as shown in FIG. 2 , a dummy gate dielectric layer 1031 may be formed by sequentially depositing on the semiconductor substrate 100 first.

The dummy gate dielectric layer 1031 may be silicon oxide (SiO ₂ ) or silicon oxynitride (SiON). The dummy gate dielectric layer 1031 made of silicon oxide may be formed by an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like. Performing a nitridation process on silicon oxide can form silicon oxynitride, wherein the nitridation process can be high temperature furnace tube nitridation, rapid thermal annealing nitridation or plasma nitridation, of course, other nitridation processes can also be used, I won't go into details here. The dummy gate dielectric layer 1031 may also be formed for other chemical vapor deposition methods, physical vapor deposition methods, and the like.

In one example, a dummy gate dielectric layer 1031 is formed on all surfaces of the exposed first fin structure 1011 and the second fin structure 1012 .

Next, as shown in FIG. 3 , a dummy gate material layer 1032 is formed on the dummy gate dielectric layer 1031 , and chemical mechanical polishing is performed to obtain a flat surface.

The dummy gate material layer 1032 can be selected from semiconductor materials commonly used in the field, such as polysilicon, etc., which is not limited to one, and will not be listed here.

The deposition method of the dummy gate material layer includes chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), generally similar methods such as sputtering and physical vapor deposition (PVD) can also be used.

The dummy gate dielectric layer 1031 and the dummy gate material layer 1032 are then patterned to form a first dummy gate structure and a second dummy gate structure. Specifically, a hard mask layer 11 is formed on the dummy gate material layer, then a photoresist layer is formed on the hard mask layer 11, and then exposed and developed to form openings, and then the photoresist layer is used as The hard mask layer 11 and the dummy gate material layer 1032 are mask etched.

Afterwards, optionally, offset spacers (not shown) are formed on the sidewalls of the first dummy gate structure and the second dummy gate structure.

Specifically, the offset spacers may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the offset spacers are composed of silicon oxide and silicon nitride. The specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a first silicon nitride layer on a semiconductor substrate. The silicon dioxide layer is then etched to form offset spacers. It is also possible to form a spacer material layer on both the top surface and the sidewall of the dummy gate structure, and in a subsequent step, the spacer material layer on the top surface is removed by a planarization method, such as chemical mechanical polishing, to form only a Offset side wall on side wall.

Subsequently, LDD ion implantation is performed on the PMOS region and the NMOS region, respectively.

Among them, LDD ion implantation to form a lightly doped drain (LDD) structure in the source/drain regions can reduce the electric field and can significantly improve the hot electron effect.

Exemplarily, LDD ion implantation is performed on the first fin structures 1011 on both sides of the first dummy gate structure in the PMOS region to form a P-type lightly doped drain (LDD), and the implanted ions can be any P-type Doping ions, including but not limited to boron (B) ions, indium (In) ions.

Then, LDD ion implantation is performed on the second fin structures 1012 on both sides of the second dummy gate structure in the NMOS region to form an N-type lightly doped drain (LDD). The implanted ions can be any suitable N-type dopant. Ions, including but not limited to phosphorus (P) ions, arsenic (As) ions.

Next, as shown in FIG. 4 , a first spacer material layer 104 is deposited to cover the PMOS region and the NMOS region.

Specifically, the first spacer material layer 104 is formed on the surface of the exposed isolation structure 102 , the top surfaces and sidewalls of the first and second dummy gate structures, and the first dummy gate Sidewalls and top surfaces of the first fin structure 1011 and the second fin structure 1012 on both sides of the structure and the second dummy gate structure.

The first spacer material layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the first spacer material layer 104 is silicon nitride.

The first spacer material layer 104 may be formed using methods including, but not limited to, chemical vapor deposition methods and physical vapor deposition methods.

Next, as shown in FIG. 5 , a patterned first photoresist layer 1051 is formed to cover the NMOS region and expose the PMOS region.

Specifically, the patterned first photoresist layer 1051 is formed by a photolithography process (including coating photoresist, exposure and development, etc.), and the patterned first photoresist layer 1051 is exposed in the PMOS region The first spacer material layer 104 .

Then, using the patterned first photoresist layer 1051 as a mask, etching and removing the top surface of the first fin structure 1011 and the surface of the semiconductor substrate 100 (ie, the surface of the isolation structure 102 ) (top) part of the first spacer material layer 104, retaining the first spacer material layer 104 on the sidewall of the first dummy gate structure and on the sidewall of the first fin structure 1021 on both sides of the first dummy gate structure A spacer material layer 104 .

The etching method can use any suitable dry etching or wet etching method known to those skilled in the art.

Subsequently, as shown in FIG. 5 , part of the first fin structure 1011 and part of the first fin structure 1011 in the source/drain regions on both sides of the first dummy gate structure are removed by etching back The first spacer material layer 104 .

The etch-back may use any suitable dry etching or wet etching method known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. Dry etching is preferably performed by one or more RIE steps.

After that, the patterned first photoresist layer 1051 is removed. The first photoresist layer 1051 may be removed using an ashing method.

Next, as shown in FIG. 6 , a first stress epitaxial layer 106 is grown in the source/drain regions of the first fin structure 1011 on both sides of the first dummy gate structure.

The first stress epitaxial layer 106 can be grown on the surface of the exposed first fin structure 1011 using a selective epitaxial growth method, and the selective epitaxial growth can adopt low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) and Molecular Beam Epitaxy (MBE).

The material of the first stressed epitaxial layer 106 may include SiGe or other suitable materials that can provide compressive stress. Specifically, SiGe can be grown by chemical vapor deposition method or gas source molecular beam epitaxy method, using silane or disilane as a silicon source, and adding a certain amount of germane at the same time. For example, select GeH ₄ and SiH ₂ Cl ₂ as the reactive gas, and select H ₂ as the carrier gas, wherein the flow ratio of the reactive gas and the carrier gas is 0.01-0.1, and the deposition temperature is 300-1000 ℃, preferably 650-750 °C, the gas pressure is 1-50 Torr, preferably 20-40 Torr.

A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying the compressive stress to the PMOS.

Wherein, preferably, the cross-sectional shape of the first stress epitaxial layer 106 is preferably a "Σ" shape.

Next, as shown in FIG. 7 , an oxidation treatment is performed to form a first oxide layer 107 on the exposed surface of the first stressed epitaxial layer 106 .

The first oxide layer 107 of silicon oxide can be formed by using an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), and in-situ steam oxidation (ISSG).

Next, as shown in FIG. 7 , a second spacer material layer 1081 is deposited to cover the PMOS region and the NMOS region.

The second spacer material layer 1081 may use the same material as the aforementioned first spacer material layer 104, and the second spacer material layer 1081 may be composed of one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the second spacer material layer 1081 is silicon nitride.

The second spacer material layer 1081 may be formed using methods including, but not limited to, chemical vapor deposition methods and physical vapor deposition methods.

Wherein, in the PMOS region, the second spacer material layer 1081 covers the surface of the first stress epitaxial layer 106, is located on the first oxide layer 107, and is in the first fin structure 1011 in the PMOS region A second spacer material layer 1081 is formed on the sidewall of the isolation structure 102 and on the surface of the isolation structure 102 .

Next, as shown in FIG. 8 , a patterned second photoresist layer 1052 is formed to cover the PMOS region to expose the NMOS region, and the patterned second photoresist layer 1052 is used as a mask to etch and remove all the The first spacer material layer and the second spacer material layer on the top surface of the second fin structure 1012 and the surface of the semiconductor substrate 100 in the NMOS region, so that the second fin structure 1012 The first spacers 108 are formed on the sidewalls of the fins, and part of the top surface of the second fin structure 1012 is exposed.

Specifically, the patterned second photoresist layer 1052 is formed by using a photolithography process (including processes such as coating photoresist, exposure and development, etc.), and the patterned second photoresist layer 1052 is exposed in the NMOS region of the second spacer material layer.

The first spacer material layer and the second spacer material layer on the surface of the semiconductor substrate 100 in the NMOS region are removed, that is, the first gap on the surface of the isolation structure 102 in the NMOS region is removed a layer of wall material and the second layer of spacer material.

The etching method can use any suitable dry etching or wet etching method known to those skilled in the art, preferably, a dry etching method is used.

Exemplarily, the thickness of the first spacer 108 may range from 60 to 120 angstroms. The above thickness range is only an example, and other suitable ranges are also applicable to the present invention.

Next, as shown in FIG. 9, using the patterned second photoresist layer 1052 as a mask, the exposed source/drain regions of the second fin structure 1012 are etched back for a first time to remove part of the exposed source/drain regions of the second fin structure 1012. The second fin structure 1012 forms the first groove 109 .

In one example, the first etch back also simultaneously removes the dummy gate dielectric layer 1031 on the sidewalls of the second fin structure 1012 .

The first etching back can use any suitable dry etching or wet etching or a combination thereof known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. Dry etching is preferably performed by one or more RIE steps.

After that, the patterned patterned second photoresist layer 1052 is removed. The patterned second photoresist layer 1052 may be removed using an ashing method.

Exemplarily, the depth range of the first etching back is 20˜40 nm, that is, the depth range of the etching back from the top surface of the second fin structure 1012 is 20˜40 nm, and the depth range is only used as an example.

Next, as shown in FIG. 10 , the exposed surface of the second fin structure 1012 is oxidized to form a second oxide layer 110 .

Specifically, the surface of the second fin structure 1012 exposed from the first groove 109 is oxidized to form the second oxide layer 110 . The second oxide layer 110 serves as an etch stop layer when the first spacer is etched later.

The second oxide layer 110 of silicon oxide can be formed by using an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like.

Next, as shown in FIG. 11 , the thickness of the first spacer 108 is reduced to expand the width of the first groove 109 to a first width L1 .

Exemplarily, the thinning of the first spacer 108 is achieved by using a wet etching method.

In one example, when the material of the first spacer 108 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve thinning of the first spacer 108, the phosphoric acid It can also be a hot phosphoric acid solution, which has a high etch rate for silicon nitride and a low etch rate for oxides and the like.

Wherein, in this embodiment, after the first spacer 108 is thinned, the thickness of the remaining first spacer 108 ranges from 2 to 6 nm, but is not limited thereto.

It is worth mentioning that, in the process of thinning the first spacer 108 by the wet etching, the second spacer material layer in the PMOS region is also etched and thinned at the same time.

Subsequently, the second oxide layer 110 is removed by pre-cleaning to expose the top surface of the second fin structure 1012 in the first groove 109 . Illustratively, the pre-cleaning can employ a hydrofluoric acid solution, such as buffer oxide etchant (BOE) or buffer solution of hydrofluoric acid (BHF).

Next, as shown in FIG. 12 , a second stress epitaxial layer 111 is grown on the second fin structure 1012 exposed in the first groove 109 to fill the first groove, wherein the second stress epitaxial layer 111 is formed. The width of the stressed epitaxial layer 111 is the first width L1.

The second stress epitaxial layer 111 can be grown on the surface of the exposed second fin structure 1012 using a selective epitaxial growth method, and the selective epitaxial growth can adopt low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) and Molecular Beam Epitaxy (MBE).

In NMOS, the second stressed epitaxial layer 111 generally has tensile stress. The material of the second stress epitaxial layer 111 can be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stress epitaxial layer. Specifically, the SiP can be grown by chemical vapor deposition method or gas source molecular beam epitaxy method, using silane or disilane as the silicon source, and phosphine as the phosphorus source.

Wherein, the top surface of the second stressed epitaxial layer 111 may also be higher than the top surface of the first spacer 108 on the sidewall. The first grooves between the first spacers grow upward.

The exposed surface of the second stressed epitaxial layer can also be selectively oxidized to form an oxide layer, and the oxide layer can be used as an etch stop layer when etching the spacer material layer later.

Next, as shown in FIG. 13 , a third spacer material layer 1121 is deposited to cover the PMOS region and the NMOS region.

The third spacer material layer 1121 may be one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the third spacer material layer 1121 is silicon nitride.

The third spacer material layer 1121 may be formed using methods including, but not limited to, chemical vapor deposition methods and physical vapor deposition methods.

Next, as shown in FIG. 14, a patterned third photoresist layer 1053 is formed to cover the PMOS region to expose the NMOS region, and the patterned third photoresist layer 1053 is used as a mask to remove the A part of the third spacer material layer 1121 on the top surface of the second stressed epitaxial layer 111 and on the semiconductor substrate 100 in the NMOS region, so that the second fin structure 1012 and the second The second spacers 112 are formed on the sidewalls of the stressed epitaxial layer 111 .

Specifically, the patterned third photoresist layer 1053 is formed by a photolithography process (including processes such as coating photoresist, exposure and development, etc.), and the patterned third photoresist layer 1053 is exposed in the NMOS region The third spacer material layer 1121.

The third spacer material layer 1121 on the surface of the semiconductor substrate 100 in the NMOS region is removed, that is, the third spacer material layer 1121 on the surface of the isolation structure 102 in the NMOS region is removed.

The etching method can use any suitable dry etching or wet etching method known to those skilled in the art, preferably, a dry etching method is used.

In one example, when an oxide is formed on the second stressed epitaxial layer 111 , the oxide can also be removed to expose the top surface of the second stressed epitaxial layer 111 .

Next, as shown in FIG. 15 , using the patterned third photoresist layer 1053 as a mask, part of the second stress epitaxial layer 111 is removed by a second etching back to form the second groove 113 .

The second etch back may use any suitable dry etching or wet etching or a combination thereof known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. Dry etching is preferably performed by one or more RIE steps.

Exemplarily, the wet etching may use an etching method having a high etching rate for the second stressed epitaxial layer 111 and a low etching rate for the spacers and isolation structures.

Exemplarily, the depth range of the second etch back is 10-20 nm, that is, the depth range of the etch back from the top surface of the second stressed epitaxial layer is 10-20 nm, and the depth range is only used as an example.

After that, the patterned patterned third photoresist layer 1053 is removed. The patterned third photoresist layer 1053 may be removed using an ashing method.

Next, as shown in FIG. 16 , the thickness of the second spacer 112 is reduced to expand the width of the second groove 113 to a second width L2 .

Exemplarily, the thinning of the second spacer 112 is achieved by using a wet etching method.

In one example, when the material of the second spacer 112 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve thinning of the second spacer 112 , the phosphoric acid It can also be a hot phosphoric acid solution, which has a high etch rate for silicon nitride and a low etch rate for oxides and the like.

Wherein, in this embodiment, after the second spacer 112 is thinned, the thickness of the remaining second spacer 112 ranges from 2 to 6 nm, but is not limited thereto.

It is worth mentioning that, in the process of thinning the second spacer 1128 by the wet etching, the third spacer material layer 1121 in the PMOS region is also etched and thinned at the same time.

Next, as shown in FIG. 17 , a third stress epitaxial layer 114 is grown on the surface of the second stress epitaxial layer 111 to fill the second groove and overflow to the remaining second spacers 112 On the top surface, wherein the width of the third stress epitaxial layer 112 in the second groove is the second width L2, and the third stress epitaxial layer located above the top surface of the second spacer 112 Layer 114 has a third width L3, wherein the first width L1 is less than the second width L2, and the second width L2 is less than the third width L3.

It is worth mentioning that the first width, the second width and the third width refer to cutting the second stress epitaxial layer and the surface perpendicular to the surface of the semiconductor substrate and perpendicular to the extending direction of the fin structure. The width of the corresponding section obtained by the third stressed epitaxial layer.

The third stressed epitaxial layer 114 can be grown on the exposed surface of the second stressed epitaxial layer 111 by a method of selective epitaxial growth, and the selective epitaxial growth can adopt low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) and Molecular Beam Epitaxy (MBE).

In NMOS, the third stressed epitaxial layer 114 typically has tensile stress. The material of the third stress epitaxial layer 114 can be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the third stress epitaxial layer 114 . Specifically, the SiP can be grown by chemical vapor deposition method or gas source molecular beam epitaxy method, using silane or disilane as the silicon source, and phosphine as the phosphorus source.

Wherein, when the third stressed epitaxial layer 114 is epitaxially grown, the second spacer 112 has a guiding effect on the growth of the third stressed epitaxial layer 114, and controls it to grow upward in the second groove between the second spacers 112 .

Through the above method, a SiP stress epitaxial layer is formed in the source/drain regions of the NMOS region, the stress epitaxial layer includes a second stress epitaxial layer with a first width at the bottom, and a third stress epitaxial layer on the second stress epitaxial layer. The epitaxial layer, wherein the third stressed epitaxial layer includes from bottom to top a third stressed epitaxial layer of a second width and a third stressed epitaxial layer of a third width located above the top surface of the second spacer, wherein the first width is smaller than the third stress epitaxial layer. The second width is smaller than the third width, so the top of the stress epitaxial layer is enlarged and the contact area is larger, so that the stress epitaxial layer has lower external resistance. volume, so that the short channel effect is also well controlled.

Next, as shown in FIG. 18 , a contact hole etch stop layer is formed on the surfaces of the semiconductor substrate 100 , the first stressed epitaxial layer 106 , the third stressed epitaxial layer 114 and the second spacer 112 . 115 ; depositing an interlayer dielectric layer 116 on the contact hole etch stop layer 115 , and planarizing the interlayer dielectric layer 116 .

A contact hole etch stop layer (CESL) 115 is formed on the substrate. The contact hole etch stop layer may include a dielectric material such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like.

Contact hole etch stop layer 115 may include any two of several etch stop materials. Non-limiting examples include conductor etch stop materials, semiconductor etch stop materials, and dielectric etch stop materials. For reasons that will become more apparent in the additional description below, the etch stop layer includes an etch stop material that is susceptible to local changes, which provides region-specific etch selectivity to the etch stop layer. In the present invention, the contact hole etch stop layer 115 is composed of two layers, including an oxide layer and a nitride layer outside the oxide layer, wherein the oxide can be selected from SiO ₂ , so The nitride can be selected from one of SiCN, SiN, SiC, SiOF, and SiON, but the contact hole etching stop layer is not limited to the above examples.

An interlayer dielectric layer 116 is then deposited and planarized. Non-limiting examples of the planarization process include mechanical planarization methods and chemical mechanical polishing (CMP) planarization methods.

The interlayer dielectric layer 116 can be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS) or boron-doped of tetraethoxysilane (BTEOS).

So far, the introduction of the main steps of the semiconductor device manufacturing method of the present invention has been completed, and other preceding steps, intermediate steps or subsequent steps are required for the fabrication of a complete device, which will not be repeated here.

According to the manufacturing method of the present invention, a spacer is used as a guide when growing the stressed epitaxial layer in the source/drain regions of the NMOS region, so that a merged epitaxial layer is not formed. In addition, since the top of the stressed epitaxial layer is enlarged, the contact The area of the stress epitaxial layer is larger, so the stress epitaxial layer has lower external resistance. Furthermore, since the volume of the stress epitaxial layer at the bottom is not substantially increased, the short channel effect is also well controlled. Therefore, according to the present invention The manufacturing method reasonably balances the volume and contour of the source/drain stress epitaxial layer, and improves the performance and yield of the device.

Embodiment 2

The present invention also provides a semiconductor device prepared by using the method in the first embodiment.

Specifically, as shown in FIG. 17 and FIG. 18 , the semiconductor device of the present invention includes a semiconductor substrate 100, the semiconductor substrate 100 includes a PMOS region and an NMOS region, and the semiconductor substrate 100 in the PMOS region and the NMOS region A first fin structure 1011 and a second fin structure 1012 are respectively formed thereon.

Specifically, the semiconductor substrate 100 may be at least one of the following mentioned materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes these semiconductor components multi-layer structures, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI) Wait. In this embodiment, the semiconductor substrate 100 is preferably a silicon substrate.

A first fin structure 1011 is formed on the semiconductor substrate 100 in the PMOS region, and a second fin structure 1012 is formed on the semiconductor substrate 100 in each of the NMOS regions.

In one example, the method of forming the first fin structure 1011 and the second fin structure 1012 includes the following steps:

A patterned mask layer is formed on the surface of the semiconductor substrate 100, and the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including fins The width, length and position, etc. of the patterned mask layer are used as a mask, and the semiconductor substrate 100 is etched to form the first fin structure 1011 and the second fin structure 1012 . The mask layer can generally include any of several mask materials including, but not limited to, hard mask materials and photoresist mask materials. The above-mentioned etching may be performed by methods such as dry etching or wet etching, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods. A single etching method may also be used, or more than one etching method may be used.

It should be noted that, the methods of forming the first fin structure 1011 and the second fin structure 1012 are only exemplary, and are not limited to the above methods.

The widths of the fin structures are all the same, or the fins are divided into a plurality of fin structure groups with different widths, and the lengths of the fin structures may also be different.

An isolation structure 102 is also formed on the semiconductor substrate 100. The isolation structure 102 may be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. In this embodiment, the isolation structure 102 is preferably shallow trench isolation structure. The top surface of the isolation structure 102 is lower than the top surfaces of the first fin structure 1011 and the second fin structure 1012 . Various well structures are also formed in the semiconductor substrate 100 , for example, an N-type well is formed in the PMOS region, and a P-type well is formed in the NMOS region, which are omitted from the illustration for simplicity.

Further, a first gate structure and a second gate structure spanning a part of the first fin structure 1011 and a part of the second fin structure 1012 are respectively formed in the PMOS region and the NMOS region.

Both the first gate structure and the second gate structure include a bottom-up gate dielectric layer 1031 and a gate layer 1032 .

Gate Dielectric Layer 1031 The gate dielectric layer may be formed by thermal oxidation, nitridation or oxynitridation. The above processes may also be used in combination when forming the gate dielectric layer. _The gate dielectric layer may comprise any conventional dielectric such as _{: SiO2} , _Si3N4 , _SiON , _SiON2 , such as _TiO2 , _Al2O3 , _ZrO2 , _HfO2 , _{Ta2O5 , La2O3} and other similar oxides including, but not limited to, perovskite oxides. Typically, high-k dielectrics can withstand high temperature (900°C) annealing. The gate dielectric layer may also include any combination of the above-described dielectric materials.

The gate layer 1032 is formed on the gate dielectric layer 1031 . In one embodiment, the gate layer is composed of polysilicon material, and generally, metal, metal nitride, metal silicide or similar compounds can be used as the material of the gate layer.

In one example, a first stressed epitaxial layer 106 is formed in the source/drain regions of the first fin structure 1011 on both sides of the first gate structure, and a surface of the first stressed epitaxial layer 106 is further formed with The first oxide layer 107, a spacer material is formed on the surface of the first oxide layer 107, the sidewall of the first fin structure 1011 and the surface of the semiconductor substrate 100 in the PMOS region Layer 1121.

The material of the first stressed epitaxial layer 106 may include SiGe or other suitable materials that can provide compressive stress.

A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying the compressive stress to the PMOS.

Wherein, preferably, the cross-sectional shape of the first stress epitaxial layer 106 is preferably a "Σ" shape.

Exemplarily, the first oxide layer 107 is silicon oxide formed using an oxidation process.

The spacer material layer 1121 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the spacer material layer 1121 is silicon nitride.

Further, the semiconductor device of the present invention further includes a second stress epitaxy having a first width L1 formed from bottom to top in the source/drain regions of the second fin structure 1012 on both sides of the second gate structure layer 111, a third stressed epitaxial layer 114 of a second width L2, and the third stressed epitaxial layer 114 of a third width L3, wherein the first width L1 is smaller than the second width L2, the second width L2 is smaller than the third width L3 , and spacers 112 are formed on the sidewalls of the second fin structure 1012 , the second stressed epitaxial layer 111 , and the third stressed epitaxial layer 114 of the second width.

The spacer 112 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the spacer 112 is silicon nitride.

In NMOS, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 generally have tensile stress. The materials of the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 . Specifically, the SiP can be grown by chemical vapor deposition method or gas source molecular beam epitaxy method, using silane or disilane as the silicon source, and phosphine as the phosphorus source.

Exemplarily, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may also be different materials with tensile stress.

In the semiconductor device of the present invention, a SiP stress epitaxial layer is formed in the source/drain regions of the NMOS region, the stress epitaxial layer includes a second stress epitaxial layer with a first width at the bottom, and a stress epitaxial layer on the second stress epitaxial layer. A third stressed epitaxial layer, wherein the third stressed epitaxial layer includes from bottom to top a third stressed epitaxial layer of a second width and a third stressed epitaxial layer of a third width located above the top surface of the second spacer, wherein the first stressed epitaxial layer The width is smaller than the second width, and the second width is smaller than the third width, so the top of the stress epitaxial layer is enlarged and the contact area is larger, so the stress epitaxial layer has lower external resistance, and furthermore, the bottom stress is not increased. The volume of the epitaxial layer enables the short channel effect to be well controlled.

Further, a contact hole etch stop layer 115 is formed on the surfaces of the semiconductor substrate 100 , the first stressed epitaxial layer 106 , the third stressed epitaxial layer 114 and the spacer 112 ; An interlayer dielectric layer 116 is deposited on the hole etch stop layer 115 .

A contact hole etch stop layer (CESL) 115 is formed on the substrate. The contact hole etch stop layer may include a dielectric material such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like.

Contact hole etch stop layer 115 may include any two of several etch stop materials. Non-limiting examples include conductor etch stop materials, semiconductor etch stop materials, and dielectric etch stop materials. For reasons that will become more apparent in the additional description below, the etch stop layer includes an etch stop material that is susceptible to local changes, which provides region-specific etch selectivity to the etch stop layer. In the present invention, the contact hole etch stop layer 115 is composed of two layers, including an oxide layer and a nitride layer outside the oxide layer, wherein the oxide can be selected from SiO ₂ , so The nitride can be selected from one of SiCN, SiN, SiC, SiOF, and SiON, but the contact hole etching stop layer is not limited to the above examples.

The interlayer dielectric layer 116 may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS), or boron-doped of tetraethoxysilane (BTEOS).

For a complete device, it also includes other structural components, which will not be repeated here.

Since the semiconductor device of the present invention is prepared by the aforementioned method, it has the same advantages.

The semiconductor device of the present invention uses a spacer as a guide when growing the stress epitaxy layer in the source/drain regions of the NMOS region, so no merged epitaxy layer is formed. In addition, since the semiconductor device of the present invention includes an enlarged stress epitaxy The top of the layer makes the contact area larger, so the stress epitaxial layer has a lower external resistance. Furthermore, since the volume of the bottom stress epitaxial layer is not substantially increased, the short channel effect is also well controlled. The volume and profile of the source/drain stress epitaxial layer are reasonably balanced, and therefore, the performance of the semiconductor device according to the present invention is higher.

Embodiment 3

The present invention also provides an electronic device, including the semiconductor device described in the second embodiment, and the semiconductor device is prepared according to the method described in the first embodiment.

The electronic device in this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, MP3, MP4, PSP, etc. A product or device can also be any intermediate product that includes a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

Among them, FIG. 20 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302 included in a casing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

The mobile phone includes the semiconductor device described in Embodiment 2, and the semiconductor device mainly includes:

a semiconductor substrate, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;

A first gate structure and a second gate structure spanning a part of the first fin structure and a part of the second fin structure are respectively formed in the PMOS region and the NMOS region;

A first stress epitaxial layer is formed in the source/drain regions of the first fin structure on both sides of the first gate structure;

A second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a The third stress epitaxial layer with three widths, wherein the first width is smaller than the second width, and the second width is smaller than the third width;

Spacers are formed on the sidewalls of the second fin structure, the second stressed epitaxial layer, and the third stressed epitaxial layer of the second width.

The electronic apparatus of the present invention includes the aforementioned semiconductor device and thus also has the same advantages.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (23)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;

forming a first dummy gate structure and a second dummy gate structure respectively crossing a portion of the first fin structure and a portion of the second fin structure in the PMOS region and the NMOS region;

growing a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first dummy gate structure;

forming first gap walls on the side walls of the second fin structures at two sides of the second dummy gate structure;

performing first back etching on the exposed source/drain regions of the second fin structures to remove part of the second fin structures to form first grooves;

thinning the thickness of the first gap wall to enlarge the width of the first groove to a first width;

growing a second stress epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stress epitaxial layer is the first width;

forming second spacer walls on the second fin structures and the side walls of the second stress epitaxial layer;

a second etching back step is carried out to remove part of the second stress epitaxial layer so as to form a second groove;

thinning the thickness of the second gap wall to enlarge the width of the second groove to a second width;

and growing a third stress epitaxial layer on the surface of the second stress epitaxial layer to fill the second groove and overflow to the top surface of the rest second gap wall, wherein the width of the third stress epitaxial layer in the second groove is the second width, and the third stress epitaxial layer above the top surface of the second gap wall has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming the first dummy gate structure and the second dummy gate structure and before forming the first stress epitaxial layer, the steps of:

depositing a first spacer material layer to cover the PMOS region and the NMOS region;

forming a patterned first photoresist layer to cover the NMOS region and expose the PMOS region;

etching and removing a part of the first spacer material layer on the top surface of the first fin structure and on the surface of the semiconductor substrate by taking the patterned first photoresist layer as a mask;

and etching back to remove a part of the first fin structure in the source/drain regions at two sides of the first dummy gate structure and a part of the first spacer material layer on the first fin structure.

3. The method of manufacturing of claim 1 or 2, wherein after forming the first stressed epitaxial layer and before forming the first spacer, further comprising the steps of: and carrying out oxidation treatment to form a first oxide layer on the exposed surface of the first stress epitaxial layer.

4. The method of manufacturing according to claim 2, wherein the method of forming the first spacer comprises the steps of:

depositing a second spacer material layer to cover the PMOS region and the NMOS region;

forming a patterned second photoresist layer to cover the PMOS region and expose the NMOS region;

and etching and removing the first gap wall material layer and the second gap wall material layer on the top surface of the second fin structure and the surface of the semiconductor substrate in the NMOS area so as to form the first gap wall on the side wall of the second fin structure and expose part of the top surface of the second fin structure.

5. The method of manufacturing of claim 1, wherein after the first etch-back step, before thinning the thickness of the first spacer, further comprising the steps of: and oxidizing the exposed surface of the second fin structure to form a second oxide layer, and after the step of thinning the thickness of the second spacer, pre-cleaning and removing the second oxide layer.

6. The manufacturing method according to claim 1, wherein the process of forming the second spacer includes the steps of:

depositing a third spacer material layer to cover the PMOS region and the NMOS region;

forming a patterned third photoresist layer to cover the PMOS region and expose the NMOS region;

and etching and removing part of the third spacer material layer on the top surface of the second stress epitaxial layer and the semiconductor substrate in the NMOS region so as to form the second spacers on the second fin structures and the side walls of the second stress epitaxial layer.

7. The method of claim 1, wherein the first spacer has a thickness in a range of 60 to 120 angstroms.

8. The method according to claim 1, wherein the depth of the first etch-back is in a range of 20nm to 40 nm.

9. The method according to claim 1, wherein a thickness of the first spacer remaining after the thinning of the first spacer is in a range of 2 to 6 nm.

10. The method according to claim 1, wherein a thickness of the second spacer remaining after the thinning of the second spacer is in a range of 2 to 6 nm.

11. The manufacturing method according to claim 1, wherein a depth of the second etch-back is in a range of 10 to 20 nm.

12. The method of manufacturing of claim 1 wherein the material of the second stressed epitaxial layer and the third stressed epitaxial layer each comprise SiP.

13. The manufacturing method according to claim 1, wherein the thinning of the first spacer and the thinning of the second spacer are achieved using a wet etching method.

14. The manufacturing method according to claim 13, wherein the wet etching uses an etchant including phosphoric acid.

15. The method of manufacturing of claim 1, further comprising:

forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the second gap wall;

and depositing an interlayer dielectric layer on the contact hole etching stop layer, and flattening the interlayer dielectric layer.

16. The method of manufacturing of claim 1, wherein the material of the first stressed epitaxial layer comprises SiGe.

17. A semiconductor device, comprising:

the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;

forming a first gate structure and a second gate structure respectively crossing a part of the first fin structure and a part of the second fin structure in the PMOS region and the NMOS region;

forming a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first gate structure;

a second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width are formed in the source-drain regions of the second fin structures on two sides of the second gate structure from bottom to top, wherein the first width is smaller than the second width, the second width is smaller than the third width, and the first width is larger than the width of the second fin structures;

and forming gap walls on the side walls of the second fin structure, the second stress epitaxial layer and the third stress epitaxial layer with the second width.

18. The semiconductor device of claim 17, wherein a first oxide layer is also formed on a surface of the first stress epitaxial layer.

19. The semiconductor device of claim 18, wherein a layer of spacer material is formed on a surface of the first oxide layer, on sidewalls of the first fin structures, and on a surface of the semiconductor substrate within the PMOS region.

20. The semiconductor device of claim 17, wherein the material of the second stressed epitaxial layer and the third stressed epitaxial layer each comprises SiP.

21. The semiconductor device according to claim 17, further comprising:

forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the gap wall;

an interlayer dielectric layer is deposited on the contact hole etching stop layer.

22. The semiconductor device of claim 17, the material of the first stressed epitaxial layer comprising SiGe.

23. An electronic device comprising the semiconductor device according to any one of claims 17 to 22.

Images