CN107968121B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN107968121B CN107968121B CN201610915984.5A CN201610915984A CN107968121B CN 107968121 B CN107968121 B CN 107968121B CN 201610915984 A CN201610915984 A CN 201610915984A CN 107968121 B CN107968121 B CN 107968121B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
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- 229910021389 graphene Inorganic materials 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 41
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- 239000000463 material Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
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- 238000009832 plasma treatment Methods 0.000 claims description 6
- 230000007935 neutral effect Effects 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 239000011701 zinc Substances 0.000 claims description 2
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- 238000010586 diagram Methods 0.000 description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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- 229910000365 copper sulfate Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
- H10D62/882—Graphene
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- Thin Film Transistor (AREA)
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The invention provides a method for manufacturing a semiconductor structure, which comprises the steps of providing a fin structure; forming an initial graphene layer on the fin structure; forming a patterned metal layer on the initial graphene layer, removing the patterned metal layer and forming grooves in a portion of the initial graphene layer below the patterned metal layer to convert the initial graphene layer into a bi-layer graphene structure; carrying out hydrogenation treatment on the double-layer graphene structure to enable the double-layer graphene to generate an energy band gap; a gate dielectric layer is formed on the double-layer graphene structure. The semiconductor structure obtained by the method has double-layer graphene with energy band gaps, so that the electron mobility of the obtained semiconductor structure can be obviously improved, the instability of pinch-off voltage is improved, and the production quality is favorably improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
In the Complementary Metal Oxide Semiconductor (CMOS) industry, with the advent of a size of 22nm and less, a Fin Field-effect transistor (FinFET) is widely used due to its unique structure in order to improve a short channel effect and improve device performance.
A FinFET is a special type of metal oxide semiconductor field effect transistor whose structure is usually formed on a silicon-on-insulator substrate, comprising narrow, individual strips of silicon as vertical channel structures, also called fins, on both sides of which gate structures are provided. As shown in fig. 1 in detail, a FinFET structure in the prior art includes: substrate 10, source 11, drain 12, fin 13, and gate structure 14 surrounding fin 13 on both sides and above fin 13.
However, how to improve the FinFET in the prior art to obtain better performance is a direction of attack at present.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which can improve the performance of a FinFET.
To solve the above technical problem, the present invention provides a method for manufacturing a semiconductor structure, comprising:
providing a fin structure;
forming an initial graphene layer on the fin structure;
forming a patterned metal layer on the initial graphene layer, removing the patterned metal layer and forming grooves in a portion of the initial graphene layer below the patterned metal layer to convert the initial graphene layer into a bi-layer graphene structure;
carrying out hydrogenation treatment on the double-layer graphene structure to enable the double-layer graphene structure to generate an energy band gap;
a gate dielectric layer is formed on the double-layer graphene structure.
Optionally, with respect to the method for manufacturing the semiconductor structure, after providing a fin structure and before forming an initial graphene layer on the fin structure, the method further includes:
and carrying out plasma treatment on the fin structure.
Optionally, with respect to the method for manufacturing the semiconductor structure, the forming a preliminary graphene layer on the fin structure includes:
forming a copper layer on the fin structure;
forming a layer of graphene film on the copper layer by adopting a chemical vapor deposition process;
covering polymethyl methacrylate, and performing wet etching on the copper layer;
and removing the polymethyl methacrylate, so that the graphene film is transferred to the fin structure to form the initial graphene layer.
Optionally, for the method of manufacturing the semiconductor structure, the thickness of the initial graphene layer is
Optionally, in the method for manufacturing a semiconductor structure, the material of the patterned metal layer is zinc metal.
Optionally, for the method of manufacturing the semiconductor structure, hydrochloric acid is used to remove the patterned metal layer.
Optionally, with respect to the method for manufacturing the semiconductor structure, after removing the patterned metal layer and before performing a hydrogenation treatment on the double-layer graphene structure, the method further includes:
and cleaning the double-layer graphene structure by adopting hydrofluoric acid.
Optionally, for the method of fabricating the semiconductor structure, the hydrogen treatment is implantation by generating a hydrogen atom beam from a neutral beam at a pressure of 10-9Torr-10-7Torr at 100 deg.C or below, current of 50-200A, and ion source power of 5-50 Kev.
Optionally, for the method for manufacturing the semiconductor structure, after the gate dielectric layer is formed on the double-layer graphene structure, the method further includes:
forming dielectric layers on two sides of the lower half part of the fin type structure;
forming a grid electrode crossing the fin structure on the dielectric layer;
and forming a source electrode and a drain electrode on two sides of the grid electrode in the fin structure.
The present invention also provides a semiconductor structure comprising:
a fin structure;
a double-layer graphene structure on the fin structure, the double-layer graphene having an energy bandgap;
a gate dielectric layer on the double-layer graphene structure.
Optionally, for the saidThe thickness of the double-layer graphene is less than or equal to
Optionally, for the semiconductor structure, the method further includes:
the dielectric layers are positioned on two sides of the lower half part of the fin type structure;
a gate located on the dielectric layer across the fin structure; and
and the source and the drain are positioned at two sides of the grid in the fin structure.
The invention provides a method for manufacturing a semiconductor structure, which comprises the steps of providing a fin structure; forming an initial graphene layer on the fin structure; forming a patterned metal layer on the initial graphene layer, removing the patterned metal layer and forming grooves in a portion of the initial graphene layer below the patterned metal layer to convert the initial graphene layer into a bi-layer graphene structure; carrying out hydrogenation treatment on the double-layer graphene structure to enable the double-layer graphene to generate an energy band gap; a gate dielectric layer is formed on the double-layer graphene structure. The semiconductor structure obtained by the method has double-layer graphene with energy band gaps, so that the electron mobility of the obtained semiconductor structure can be obviously improved, the instability of pinch-off voltage is improved, and the production quality is favorably improved.
Drawings
Fig. 1 is a schematic diagram of a prior art FinFET device structure;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure according to the present invention;
FIG. 3 is a schematic diagram of a fin structure provided in an embodiment of the present invention;
4-5 are schematic diagrams of the formation of an initial graphene layer on a fin structure in an embodiment of the invention;
6-7 are schematic diagrams of converting an initial graphene layer to a bi-layer graphene structure in one embodiment of the present invention;
fig. 8-9 specifically disclose the process of converting the initial graphene layer into a double-layered graphene structure in fig. 6-7;
FIG. 10 is a schematic illustration of hydrotreating carried out in an embodiment of the present invention;
FIG. 11 is a schematic diagram of a subsequent process after hydrotreating in accordance with an embodiment of the present invention.
Detailed Description
The semiconductor structure and the method of fabricating the same of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The perfect graphene is an ideal two-dimensional crystal, has a two-dimensional periodic honeycomb lattice structure consisting of carbon six-membered rings, has the thickness of only one carbon atom, and is the thinnest material in the world at present. Carbon atoms constituting the two-dimensional structure of graphene in sp2The method is hybridized, the rest p orbital electrons are contributed to form delocalized pi bonds, and the pi electrons can freely move in a plane, so that the graphene is endowed with excellent conductivity; and due to the thickness of only one carbon atom, graphene also behaves as a typical two-dimensional quantum material. The mobility of electrons in graphene can reach 15000cm at most2V · s is 10 times or more higher than that of silicon material and is hardly affected by temperature change. In addition, the nano-composite material has a series of excellent physical properties such as high heat conduction capacity, super-large specific surface area, zero-mass dirac-fermi behavior, abnormal quantum Hall effect and the like, so that the nano-composite material has great application potential in the field of nano-electronic devices, and at present, in semiconductor devices such as fin field effect transistors and the like, the nano-composite material is openedGraphene has begun to be used.
However, unlike semiconductor silicon, graphene has no energy band gap between the valence band and the conduction band. The band gap is critical for electronic applications because it enables the material to switch the electron current on and off. The inventors found in long-term research that graphene generation of a band gap can be achieved through a hydrogenation process, and the band gap can be adjusted according to the hydrogenation degree, so that, in a FinFET, formation of such graphene having a band gap on a fin structure can bring about advantages such as greatly improving instability of pinch-off voltage Vt.
Accordingly, the present invention provides a method for manufacturing a semiconductor structure, comprising:
step S11, providing a fin structure;
step S12, forming an initial graphene layer on the fin structure;
step S13, forming a patterned metal layer on the initial graphene layer, removing the patterned metal layer and forming a groove in a portion of the initial graphene layer below the patterned metal layer to convert the initial graphene layer into a double-layer graphene structure;
step S14, performing hydrogenation treatment on the double-layer graphene structure, so that the double-layer graphene structure generates an energy band gap; and
step S15, forming a gate dielectric layer on the double-layer graphene structure.
Please refer to fig. 2 in conjunction with fig. 3-11, which will be described in detail.
Specifically, in step S11, referring to fig. 3, the fin structure 21 may be formed by etching the oxide layer 20 to form a protrusion with a narrow top and a wide bottom, and the cross section (i.e. the plane of the paper in fig. 3) of the protrusion is trapezoidal, more specifically, isosceles trapezoidal, as the fin structure 21. Further, the oxide layer 20 is formed on a substrate (not shown).
Preferably, after obtaining the fin structure 21, the fin structure 21 is subjected to plasma treatment. For example, nitrogen plasma treatment may be used, and the subsequent graphene attachment may be optimized by the plasma treatment.
Specifically, in step S12, referring to fig. 4, a first metal layer 22 is first formed on the fin structure 21, for example, the first metal layer 22 is made of copper and may be formed by a sputtering process or an Atomic Layer Deposition (ALD) process.
Then, a graphene film 23 is formed on the first metal layer 22, for example, by a Chemical Vapor Deposition (CVD) process.
And then, covering polymethyl methacrylate (PMMA) so that the PMMA completely covers the graphene film 23, and performing wet etching on the first metal layer 22, where, for the case that the first metal layer 22 is copper, for example, a mixed solution of copper sulfate, hydrochloric acid, and water may be used to etch and remove the first metal layer 22, or the first metal layer 22 may be removed by other methods, for example, by electrochemical corrosion.
After the first metal layer 22 is removed, the graphene film 23 is attached to the fin structure 21, and since plasma treatment is performed before, poor attachment can be effectively prevented.
Referring to fig. 5, after the first metal layer 22 is removed, PMMA is further removed, for example, by soaking with acetone or the like, so that the graphene film 23 is transferred onto the fin structure 21, and the initial graphene layer 24 is formed. The thickness of the initial graphene layer 24 may be, for example
Specifically, in step S13, referring to fig. 6, a patterned metal layer 25 is formed on the initial graphene layer 24, and in an embodiment, the material of the patterned metal layer 25 is zinc (Zn), and may be formed by a sputtering process.
In more detail, referring to fig. 8, wherein fig. 8 is a schematic diagram of a portion of the original graphene layer 24 on any one surface of the fin structure 21 in fig. 6 after forming the patterned metal layer 25, it can be seen that, in the present embodiment, the patterned metal layer 25 is in a strip shape, and partially covers the original graphene layer 24.
The patterned metal layer 25 is then removed, and hydrochloric acid (HCl) is used to remove the patterned metal layer 25, as shown in fig. 9, after removing the patterned metal layer 25, a groove 26 is formed in the original graphene layer 14 where the patterned metal layer 25 covers, so that the graphene layer is bi-layered, and a bi-layered graphene structure 24' is obtained (as shown in fig. 7) with a thickness of less than or equal to the thickness of the graphene layer
Specifically, where there are no recesses 26, the thickness is substantially the same as the thickness of the original graphene layer 24, i.e., is
And at the recesses 26 the thickness is less than the thickness of the original graphene layer 24.
Preferably, after obtaining the double-layered graphene structure 24', the double-layered graphene structure 24' is washed with hydrofluoric acid (DHF) to further remove reaction residues.
Specifically, in step S14, referring to fig. 10, the bi-layer graphene structure 24 'is hydrogenated (illustrated by an arrow in fig. 10), so that the bi-layer graphene structure 24' generates an energy band gap. The hydrogen treatment is performed by generating hydrogen atom beam from neutral beam (neutral beam) and implanting at 10 deg.C-9Torr-10-7Torr at 100 deg.C or below, current of 50-200A, and ion source power of 5-50 Kev. The process is a neutral beam implantation technique, and those skilled in the art can perform the above-described process under the conditions provided by the present invention. Further, the band gap can be adjusted by changing the band gap according to the degree of the hydrogenation treatment (for example, by adjusting the above-mentioned parameters) to achieve a desired band gap. Thus, the double-layer graphene structure 24' with the energy band gap can be applied to a semiconductor device, and the electrical performance of the semiconductor device can be obviously improved.
Specifically, in step S15, referring to fig. 11, a gate dielectric layer 27 is formed on the double-layer graphene structure 24', where the gate dielectric layer 27 may be silicon oxide, aluminum oxide, or an ONO type structure, and may be performed according to the prior art.
Further, with reference to fig. 11, dielectric layers 28 are formed on two sides of the lower half portion of the fin structure 21; and, a gate may also be formed on the dielectric layer 28 across the fin structure 21; and forming a source and a drain on both sides of the gate (i.e., in a direction perpendicular to the paper surface in fig. 11) in the fin structure 21, so as to realize the fabrication of the FinFET.
With the method according to the invention, a semiconductor structure can be obtained, which can be seen in fig. 11, and comprises:
a fin structure 21, wherein the fin structure 21 is made of an oxide layer 20, that is, a structure having a protrusion with a narrow top and a wide bottom is obtained by etching the oxide layer 20, and the cross section (i.e., the plane of the paper in fig. 3) of the fin structure is trapezoidal, more specifically, isosceles trapezoid, and further, the oxide layer 20 is made on a substrate (not shown);
the double-layer graphene structure 24' on the fin structure 21 has an energy band gap (i.e. not 0). in the present invention, the energy band gap is generated by performing a hydrogenation treatment on the double-layer graphene structure 24', and the degree of hydrogenation can be changed according to specific requirements, thereby achieving an adjustment of the energy band gap of the double-layer graphene structure 24 '; specifically, the thickness of the double-layer graphene is less than or equal to
A gate dielectric layer 27 located on the double-layer graphene structure 24', wherein the gate dielectric layer 27 may be silicon oxide, aluminum oxide, or an ONO type structure, and may be selected according to actual needs;
a gate (not shown) located on the dielectric layer 28 and crossing the fin structure 21, which may be a structure in the prior art and is not described in detail herein; and
and source and drain electrodes positioned at two sides of the gate electrode in the fin structure 21.
In summary, the method for fabricating a semiconductor structure according to the present invention includes providing a fin structure; forming an initial graphene layer on the fin structure; forming a patterned metal layer on the initial graphene layer, removing the patterned metal layer and forming grooves in a portion of the initial graphene layer below the patterned metal layer to convert the initial graphene layer into a bi-layer graphene structure; carrying out hydrogenation treatment on the double-layer graphene structure to enable the double-layer graphene to generate an energy band gap; a gate dielectric layer is formed on the double-layer graphene structure. The semiconductor structure obtained by the method has double-layer graphene with energy band gaps, so that the electron mobility of the obtained semiconductor structure can be obviously improved, the instability of pinch-off voltage is improved, and the production quality is favorably improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103165449A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105322018A (en) * | 2014-06-13 | 2016-02-10 | 台湾积体电路制造股份有限公司 | Thin-Sheet FinFET Device |
| CN105575814A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor (FET) and formation method thereof |
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| CN103165449A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105322018A (en) * | 2014-06-13 | 2016-02-10 | 台湾积体电路制造股份有限公司 | Thin-Sheet FinFET Device |
| CN105575814A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor (FET) and formation method thereof |
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