CN108052307B - A look-ahead computing method and system for the number of leading zeros in a floating-point unit of a processor - Google Patents

Abstract

The invention discloses a method and a system for advanced operation of leading zero quantity of a floating point unit of a processor. The method comprises the following steps of decoding operation to obtain the leading zero number of each 8-bit data: the data bit is 8n bit data A [8n-1:0]Sequentially dividing the high order into 8-bit groups according to the sequence from high order to low order, and decoding the number B of leading zeros in n 8-bit data through n 8-4 decoders respectively_m[3:0](ii) a Wherein, B_mRepresenting the leading zero number of the m-th group of 8-bit data, wherein m is 1-n, and n is 1-8; obtaining data A [8n-1:0] by advanced operation and logic judgment of each stage of three stages]The number of leading zeros is that each level will carry out two bisection pairs to the input data, and the operation is carried out in parallel between each pair; where n is an odd number, the last pair has only one input data. The invention solves the problem of long time consumption of multi-group data accumulation and achieves the effect of rapidly giving the number of leading zeros.

Description

A look-ahead computing method and system for the number of leading zeros in a floating-point unit of a processor

technical field

The invention belongs to the field of floating-point operations, and in particular relates to a method and system for the advance operation of the number of leading zeros in a floating-point unit of a processor.

Background technique

Leading zeros refer to the number of 0s that appear between the most significant bit of binary data and the first 1. The purpose of determining the number of leading zeros is to keep the length of the characters consistent and to facilitate string sorting. Leading zero prediction reduces the time required for normalized shift operations by predicting the leading zeros of the mantissa subtraction result, requiring the use of a leading zero counting component.

Chinese Patent Publication No. CN 102664637A, the publication date is September 12, 2012, and the title is "Method and Device for Determining the Number of Leading Zeros in Binary Data". For a 32-bit data leading zero operation, a more general , The easy way is to divide it into 4 groups from high to low, 8-digit group is a group, the data of each group passes through an encoder, and the output of the encoder represents the number of leading zeros of each 8-bit data, Next, judge whether the output of these four encoders is 8 in turn, and then obtain the number of leading zeros through accumulation operation. The accumulation operation is a more commonly used method in the operation of leading zeros, and its disadvantage is that it takes a long time to accumulate multiple data.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a method and system for the advance calculation of the number of leading zeros in the floating-point unit of a processor, to solve the problem that the accumulation of multiple groups of data takes a long time, and to achieve a fast delivery time. out the effect of the number of leading zeros.

The object of the present invention is achieved by the following technical solutions: According to one aspect of the present invention, a method for calculating the number of leading zeros in the floating point unit of a processor is provided, the method includes the following steps: Step 100: decoding operation, obtaining each The number of leading zeros of 8-bit data: Divide the data A[8n-1:0] whose data bits are 8n bits into 8-bit groups in order from high to low, and pass through n 8-4 decoders respectively Decode the number of leading zeros in the n 8-bit data B _m [3:0]; wherein, B _m represents the number of leading zeros in the mth group of 8-bit data, m=1～n, n=1～8; Step 200: Obtain the number of leading zeros of the data A[8n-1:0] through the advance operation and logical judgment of each of the three levels, and in each level, the input data will be paired in twos, and each pair will be matched. The operations are performed in parallel between them; among them, when n is an odd number, the last pair has only one input data.

In the above calculation method for the number of leading zeros in the floating point unit of the processor, step 200 includes the following steps: Step 210: the first stage input is the result of the decoding operation B _m [3:0], and the output is every 16 bits or 8 bits. The number of leading zeros B _jk [4:0] of the data, the logic judgment is based on the highest bit B _m [3] of each pair of input data, and the result from the advance operation and/or the lower three bits of the input data B _m [2 :0]; wherein, k=j+1, j=1, 3, 5, 7 and j≤n; Step 220: The second stage input is the result B _jk [4:0] of the first stage output, and the output is The number of leading zeros B _jkrs [5:0] of each 32-bit, 16-bit or 8-bit data, the logical judgment is based on the highest bit B _jk [4] of each pair of input data, and the result and/or input from the look-ahead operation are output. The lower four bits of the data B _jk [3:0]; wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n; Step 230: third-level input It is the result B _jkrs [5:0] output by the second stage, and the output is the leading zero number B of the 8n-bit data; the logic judgment is based on the highest bit B _jkrs [5] of each pair of input data, and the output comes from the result of the advance operation. and/or the lower four bits of the input data B _jkrs [4:0]; wherein, n=1˜8.

In the preceding calculation method of the number of leading zeros in the floating-point unit of the above-mentioned processor, the decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8'b00000001 , the output data is 4'b0111; when the input data is 8'b0000001x (x=0 or 1), the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b000001xx When the data is 8'b00001xxx, the output data is 4'b0100; when the input data is 8'b0001xxxx, the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is When 8'b01xxxxxx, the output data is 4'b0001; when the input data is 8'b1xxxxxxx, the output data is 4'b0000.

In the preceding operation method for the number of leading zeros in the floating-point unit of the processor, the operation formula of the data B _m [3:0] is:

B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]);

B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]);

B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]);

B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]);

Among them, A[p] is the p+1th bit of the data A, and _Bm [q] (q=0～3) is the q+1th bit of the data Bm; wherein, _p =0～7.

In the preceding operation method for the number of leading zeros in the floating-point unit of the above-mentioned processor, in each level of logic judgment, the method for pairing the data is as follows: when n=1, B ₁ is the number of leading zeros in the operation, and the operation ends. ; When 1<n≤8, divide B _m into pairs from high to low, and carry out the first-level operation in parallel between each pair. When n is an odd number, the last pair is less than two data, then keep B _n does not perform operation, the value of B _n is directly transmitted to the next stage, and the high-order zeros are filled when the number of digits is insufficient; or when n=2, the operation result B ₁₂ of B ₁ and B ₂ is the number of leading zeros of the operation. End; when 2<n≤8, enter the second-level logic judgment, and the output result of the first-level logic judgment B _jk (where k=j+1; j=1, 3, 5, 7 and j≤n) Two pairs from high to low are divided into a pair, and the second-level logic judgment is carried out in parallel between each pair. If the last pair has less than two data, one data is reserved without operation and directly passed to the next level. When the number of digits is insufficient High-order zero-fill, where k=j+1; j=1, 3, 5, 7 and j≤n; or when 2<n≤4, B ₁₂₃₄ is the number of leading zeros in the operation, and the operation ends; when 4< When n≤8, enter the third-level logic judgment, and perform operations on the two operation results of the second-level logic judgment.

In the above-mentioned advanced operation method for the number of leading zeros in the floating-point unit of the processor, each stage of the advanced operation includes: in the first-level advanced operation, if the high-order value B _j <8, then the number of leading zeros of the pair of data is B _jk = 5'b{00,B _j [2:0]}; if the high-order value B _j = 8, and the low-order value B _k <8, then the number of leading zeros in the pair of data is B _jk =5'b{01,B _k [2:0]}; if the high-order value B _j = 8, and the low-order value B _k = 8, the number of leading zeros of the pair of data is B _jk = 5'b{10,000}; when n is an odd number, the last A pair only has B _n , only need to fill the high-order zeros to output B _jk =5'b{0,B _n [3:0]}; among them, k=j+1, j=1,3,5,7 And j≤n; in the second-level look-ahead operation, if the high-order value B _jk <16, the number of leading zeros of the pair of data is B _jkrs = 6'b{00,B _jk [3:0]}; if the high-order value The value B _jk = 16, and the low-order value B _rs <16, then the number of leading zeros in the pair of data is B _jkrs = 6'b{01, B _rs [3:0]}; if the high-order value B _jk = 16, and The low-order value B _rs = 16, then the number of leading zeros in the pair of data is B _jkrs = 6'b{100,000}; when the last pair has only one data B _jk , just fill in the high-order zeros to output B _jkrs = 6 'b{0,B _jk [4:0]}; where k=j+1, r=j+2, s=j+3, j=1,5 and j≤n; run ahead at the third stage , if the high-order value B ₁₂₃₄ <32, the number of leading zeros in the pair of data is B=7'b{00,B ₁₂₃₄ [4:0]}; if the high-order value B ₁₂₃₄ =32, and the low-order value B ₅₆₇₈ < 32, the number of leading zeros in the pair of data is B=7'b{01,B ₅₆₇₈ [4:0]}; if the high-order value B ₁₂₃₄ =32, and the low-order value B ₅₆₇₈ =32, then the pair of data has leading zeros The number is B=7'b{1,000,000}.

In the preceding calculation method for the number of leading zeros in the floating-point unit of the above-mentioned processor, each level of logical judgment includes: in the first level of logical judgment, if the highest bit of B _j B _j [3]=0, then output B _jk =5 'b{00, _Bj [2:0]}; if _Bj [3]=1, and _Bk [3]=0, then output _Bjk =5'b{01, _Bk [2:0] }; If B _j [3]=1, and B _k [3]=1, then output B _jk =5'b{10,000}; when n is odd, the last pair has only B _n , output B _jk =5 'b{0,B _n [3:0]}; where k=j+1, j=1, 3, 5, 7 and j≤n; in the second-level logical judgment, if B _jk [4] =0, then output B _jkrs =6'b{00,B _jk [3:0]}; if B _jk [4]=1, and B _rs [4]=0, then output B _jkrs =6'b{ 01,B _rs [3:0]}; if B _jk [4]=1, and B _rs [4]=1, then output B _jkrs =6'b{100,000}; when the last pair has only one data B _jk , output B _jkrs =6'b{0,B _jk [4:0]}; where k=j+1, r=j+2, s=j+3, j=1,5 and j≤n ;In the third-level logical judgment, if B ₁₂₃₄ [5]=0, then output B=7'b{00,B ₁₂₃₄ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [ 5]=0, then output B=7'b{01,B ₅₆₇₈ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5]=1, then output B=7'b{1,000,000 }. When only B ₁₂₃₄ exists and no B ₅₆₇₈ exists, the number of leading zeros B=B ₁₂₃₄ .

According to another aspect of the present invention, there is also provided an advanced operation system for the number of leading zeros in a floating-point unit of a processor, including: a first module, used for decoding and operation to obtain the number of leading zeros per 8-bit data: The data A[8n-1:0] with 8n bits is divided into groups of 8 bits in order from high bits to low bits, and the leading zeros in the n 8-bit data are decoded by n 8-4 decoders respectively. The number B _m [3:0]; wherein, B _m represents the number of leading zeros of the mth group of 8-bit data, m=1～n, n=1～8; the second module is used to pass the The number of leading zeros of the data A[8n-1:0] is obtained by the advance operation and logical judgment of each level. In each level, the input data will be divided into two pairs, and each pair will be operated in parallel; among them, n When odd, the last pair has only one input data.

In the preceding arithmetic system with the number of leading zeros in the floating-point unit of the above-mentioned processor, the decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8' When b00000001, the output data is 4'b0111; when the input data is 8'b0000001x, the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b00001xxx , the output data is 4'b0100; when the input data is 8'b0001xxxx, the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is 8'b01xxxxxx, the output The data is 4'b0001; when the input data is 8'b1xxxxxxx, the output data is 4'b0000; where x=0 or 1.

In the preceding operator system with the number of leading zeros in the floating-point unit of the processor, the operation formula of the data B _m [3:0] is:

B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]);

B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]);

B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]);

B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]);

Among them, A[p] is the p+1th bit of the data A, and _Bm [q] (q=0～3) is the q+1th bit of the data Bm; wherein, _p =0～7.

Compared with the prior art, the present invention has the following beneficial effects:

(1) Compared with the commonly used 8-3 decoder, the 8-4 decoder used in the present invention can directly provide the control bits and output bits of the selector, and exchange for high-efficiency operation speed with a small area cost.

( ₂ ) The pairwise operation of the data is a kind of auxiliary means for reducing the operation speed of the present invention, which can allow the data in each level to be operated in parallel by pairs. The number of operation stages required for one-by-one operation is n-1, and the operation time of each stage is basically the same, so the larger the data bits of the operation, the more obvious the advantage.

(3) The advantage of adopting the advanced operation of the present invention is that when the decoding result of the 8-4 decoder is obtained, the number of leading zeros of the input data has been determined, and the determined result output only needs to be selected in conjunction with the control bit, without the need for The addition operation is performed again, which is the core of the present invention to obtain high-efficiency operation speed.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be considered limiting of the invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

FIG. 1 is a functional block diagram of a method for leading zeros in a processor floating-point unit provided by an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

FIG. 1 is a functional block diagram of a method for leading zeros in a processor floating-point unit provided by an embodiment of the present invention. As shown in FIG. 1 , the advanced operation method for the number of leading zeros in the floating-point unit of the processor includes the following steps:

Step 100: Decoding operation to obtain the number of leading zeros of each 8-bit data: Divide the data bits into 8n-bit data A[8n-1:0] according to the order from high to low. The n 8-4 decoders decode the number of leading zeros in the n 8-bit data B _m [3:0]; wherein, B _m represents the number of leading zeros in the mth group of 8-bit data, m=1～ n, n=1～8;

Step 200: Obtain the number of leading zeros of the data A[8n-1:0] through the advance operation and logical judgment of each of the three levels, and in each level, the input data will be paired in twos, and each pair will be matched. The operations are performed in parallel between them; among them, when n is an odd number, the last pair has only one input data.

Step 200 includes the following steps:

Step 210: The input of the first stage is the result of the decoding operation B _m [3:0], the output is the number of leading zeros B _jk [4:0] of each 16-bit or 8-bit data, and the logical judgment is based on each pair of inputs The highest bit B _m [3] of the data, outputs the result from the look-ahead operation and/or the lower three bits B _m [2:0] of the input data; where, k=j+1, j=1,3,5,7 and j≤n;

Step 220: The input of the second stage is the result B _jk [4:0] of the output of the first stage, and the output is the number of leading zeros B _jkrs [5:0] of each 32-bit, 16-bit or 8-bit data, the logic judgment basis For the highest bit B _jk [4] of each pair of input data, output the result from the look-ahead operation and/or the lower four bits B _jk [3:0] of the input data; where k=j+1, r=j+2 , s=j+3, j=1,5 and j≤n;

Step 230: The input of the third stage is the result B _jkrs [5:0] of the output of the second stage, and the output is the leading zero number B of the 8n-bit data; the logic judgment basis is the highest bit B _jkrs [5] of each pair of input data , output the lower four bits B _jkrs [4:0] from the result of the previous operation and/or the input data; wherein, n=1˜8.

In the above embodiment, the decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8'b00000001, the output data is 4'b0111; When the input data is 8'b0000001x (x=0 or 1), the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b00001xxx, the output data is 4'b0100; when the input data is 8'b0001xxxx, the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is 8'b01xxxxxx, the output data is 4'b0001; when the input data is 8'b1xxxxxxx, the output data is 4'b0000. The operation formula of data B _m [3:0] is:

B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]);

B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]);

B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]);

B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]);

Among them, A[p] (p=0-7) is the _p +1th bit of the data A, and Bm[q] (q=0-3) is the q+1th bit of the data _Bm .

In the above-mentioned embodiment, in each level of logical judgment, the method for pairing data in pairs is as follows:

When n=1, B ₁ is the number of leading zeros in the operation, and the operation ends; when 1<n≤8, divide B _m into pairs from high to low, and carry out the first level in parallel between each pair operation, when n is an odd number, the last pair of data is less than two data, then keep B _n for no operation, the value of B _n is directly transmitted to the next level, and the high-order bits are filled with zeros when the number of digits is insufficient; or

When n=2, the operation result B ₁₂ of B ₁ and B ₂ is the number of leading zeros of the operation, and the operation ends; when 2<n≤8, enter the second-level logic judgment, and the output of the first-level logic judgment The result B _jk (where k=j+1; j=1, 3, 5, 7 and j≤n) is divided into two pairs from high to low, and the second-level logical judgment is carried out in parallel between each pair. If a pair of data is less than two, keep one data and pass it directly to the next level without operation. When the number of digits is insufficient, the high-order bits are filled with zeros, where k=j+1; j=1, 3, 5, 7 and j≤n; or

When 2<n≤4, B ₁₂₃₄ is the number of leading zeros of the operation, and the operation ends; when 4<n≤8, enter the third-level logic judgment, and operate on the two operation results of the second-level logic judgment.

In the above embodiment, each level of look-ahead operation includes:

In the first-level look-ahead operation, if the high-order value B _j <8, the number of leading zeros in the pair of data is B _jk =5'b{00,B _j [2:0]}; if the high-order value B _j =8 , and the low-order value B _k <8, then the number of leading zeros in the pair of data is B _jk =5'b{01,B _k [2:0]}; if the high-order value B _j =8, and the low-order value B _k = 8, then the number of leading zeros in the pair of data is B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and only need to fill in the high-order zeros to output B _jk =5'b{ 0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n;

In the second-level look-ahead operation, if the high-order value B _jk <16, the number of leading zeros in the pair of data is B _jkrs =6'b{00,B _jk [3:0]}; if the high-order value B _jk =16 , and the low-order value B _rs <16, the number of leading zeros in the pair of data is B _jkrs =6'b{01,B _rs [3:0]}; if the high-order value B _jk =16, and the low-order value B _rs = 16, then the number of leading zeros in the pair of data is B _jkrs = 6'b{100,000}; when the last pair has only one data B _jk , it is only necessary to add zeros in the high bits to output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s=j+3, j=1,5 and j≤n;

In the third-level look-ahead operation, if the high-order value B ₁₂₃₄ <32, the number of leading zeros in the pair of data is B=7'b{00,B ₁₂₃₄ [4:0]}; if the high-order value B ₁₂₃₄ =32, And the low-order value B ₅₆₇₈ <32, the number of leading zeros in the pair of data is B=7'b{01,B ₅₆₇₈ [4:0]}; if the high-order value B ₁₂₃₄ =32, and the low-order value B ₅₆₇₈ =32, Then the number of leading zeros in the pair of data is B=7'b{1,000,000}.

In the above embodiment, each level of logical judgment includes:

In the first-level logical judgment, if the highest bit of B _j B _j [3]=0, then output B _jk =5'b{00,B _j [2:0]}; if B _j [3]=1 , and B _k [3]=0, then output B _jk =5'b{01,B _k [2:0]}; if B _j [3]=1, and B _k [3]=1, then output B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and the output B _jk =5'b{0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n;

In the second-level logical judgment, if B _jk [4]=0, then output B _jkrs =6'b{00,B _jk [3:0]}; if B _jk [4]=1, and B _rs [ 4]=0, then output B _jkrs =6'b{01,B _rs [3:0]}; if B _jk [4]=1, and B _rs [4]=1, then output B _jkrs =6'b{100,000}; when the last pair has only one data B _jk , output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s =j+3, j=1,5 and j≤n;

In the third-level logical judgment, if B ₁₂₃₄ [5]=0, then output B=7'b{00,B ₁₂₃₄ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5 ]=0, then output B=7'b{01,B ₅₆₇₈ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5]=1, then output B=7'b{1,000,000} . When only B ₁₂₃₄ exists and no B ₅₆₇₈ exists, the number of leading zeros B=B ₁₂₃₄ .

Taking 64-bit data as an example below, the calculation method of leading zeros adopted in the present invention is to first decode the number of leading zeros in every 8 bits through an 8-4 decoder, and then use the highest bit of the decoded value as a judgment condition, The lower bit of the decoded value is used as the output value for selection, and the output value also has the data of the advance operation, and the final result is given after the two-level decision is made, which is the number of leading zeros.

Example:

As shown in Figure 1, when processing 64-bit data, eight decoders B1 to B8 need to be used to give results through three-level logic judgment. Divide the 64-bit data A[63:0] into 8-bit groups, and pass through eight 8-4 decoders to decode the number of leading zeros in the eight 8-bit data B _m [3:0](m = 1 to 8). The decoding principle is shown in the following table:

After completing the decoding, as shown in the following table, enter the first level of logical judgment: if the value of the data B ₁ decoded by the highest 8-bit data A[63:56] is less than 8, that is, B ₁ [3]=0, then B ₁₂ =5'b{00,B1[ ₂ :0]}. If B1[3]= ₁ and B2[ ₃ ]=0, then B12=5'b{01,B2[ ₂ : ₀ ]}. If B ₁ [3]=1 and B ₂ [3]=1, then B ₁₂ =5'b{10,000}.

While detecting the value of B ₁ , check whether the value of B ₃ is less than 8. If B ₃ [3]=0, then B ₃₄ =5'b{00,B ₃ [2:0]}; if B ₃ [3] =1 and B ₄ [3]=0, B ₃₄ is computed at the same time as B ₁₂ , B ₃₄ =5'b{01,B ₄ [2:0]}; if B ₃ [3]=1 and B ₄ [3]=1, then B ₃₄ =5'b{10,000} is obtained while calculating B ₁₂ . The logic judgment and output principles of B ₅₆ and B ₇₈ are the same as those of B ₁₂ and B ₃₄ .

In the second-level logic judgment, the value of the highest-order input B ₁₂ is detected first, and if B ₁₂ [4]=0, then B ₁₂₃₄ =6'b{00,B ₁₂ [3:0]}. If B12[ ₄ ]=1 and B34[4]=0, then _B1234 = _6'b {01, _B34 [3:0]}. If B12[ ₄ ]=1 and B34[4]=1, then _B1234 = _6'b {100,000}. The logic judgment and output principle of B ₅₆₇₈ is the same as that of B ₁₂₃₄ .

In the third-level logical judgment, the value of the highest-order input B ₁₂₃₄ is first detected. If B ₁₂₃₄ [5]=0, the number of leading zeros B=7'b{00,B ₁₂₃₄ [4:0]}. If B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5]=0, then the number of leading zeros B=7'b{01,B ₅₆₇₈ [4:0]}. If _B1234 [5]=1 and _B5678 [5]=1, then B=7'b{1,000,000} or 32. The operation ends.

The relationship between the above-mentioned logical judgment conditions and the output results can be clearly corresponding in the following table.

Combining the above steps, during each level of logic judgment, only the corresponding input value or advanced operation value is selected as the output through the control signal, and no other operations (such as addition operations) are needed, thus saving the operation time. In each level, the data is divided into two pairs of parallel operations, and the 64-bit data only needs to go through 3 levels of logic judgment to obtain the number of leading zeros, which is less than the time consumption of 7 levels of logic judgment required for sequential operations from high to low.

Compared with the commonly used 8-3 decoder, the 8-4 decoder used in this embodiment can directly provide the control bits and output bits of the selector, and obtains efficient operation speed at a small area cost; Pairwise operation is an auxiliary means to reduce the operation speed in this embodiment, which allows the data in each stage to be _operated in parallel in pairs. The number of operation stages is n-1, and the operation time of each stage is basically the same, so the larger the data bits of the operation, the more obvious the advantage; the advantage of using the advanced operation in this embodiment is that the decoding result of the 8-4 decoder is obtained after the decoding. When the number of leading zeros of the input data has been determined, only the determined result output needs to be selected in conjunction with the control bits, and no addition operation is required, which is the core of the present invention to obtain efficient operation speed.

Device embodiment

This embodiment also provides a look-ahead computing system for the number of leading zeros in a floating-point unit of a processor, including: a first module and a second module. in.

The first module is used for decoding operation to obtain the number of leading zeros of each 8-bit data: the data bits are 8n-bit data A[8n-1:0] divided into 8-bit groups in the order from high to low, Decode the number of leading zeros B _m [3:0] in the n 8-bit data through n 8-4 decoders respectively; wherein, B _m represents the number of leading zeros of the mth group of 8-bit data, m= 1～n, n=1～8;

The second module is used to obtain the number of leading zeros of the data A[8n-1:0] through the advance operation and logical judgment of each of the three stages, and the input data will be paired in pairs in each stage, Operations are performed in parallel between pairs; where n is odd, the last pair has only one input data.

In the above embodiment, the decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8'b00000001, the output data is 4'b0111; When the input data is 8'b0000001x, the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b00001xxx, the output data is 4'b0100; when the input data is 8'b00001xxx, the output data is 4'b0100; When the input data is 8'b0001xxxx, the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is 8'b01xxxxxx, the output data is 4'b0001; when the input data is 8 'b1xxxxxxx, the output data is 4'b0000; where x=0 or 1.

In the above embodiment, the operation formula of data B _m [3:0] is:

B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]);

B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]);

B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]);

B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]);

Among them, A[p] is the p+1th bit of the data A, and _Bm [q] (q=0～3) is the q+1th bit of the data Bm; wherein, _p =0～7.

Compared with the commonly used 8-3 decoder, the 8-4 decoder used in this embodiment can directly provide the control bits and output bits of the selector, and obtains efficient operation speed at a small area cost; Pairwise operation is an auxiliary means to reduce the operation speed in this embodiment, which allows the data in each stage to be _operated in parallel in pairs. The number of operation stages is n-1, and the operation time of each stage is basically the same, so the larger the data bits of the operation, the more obvious the advantage; the advantage of using the advanced operation in this embodiment is that the decoding result of the 8-4 decoder is obtained after the decoding. When the number of leading zeros of the input data has been determined, only the determined result output needs to be selected in conjunction with the control bits, and no addition operation is required, which is the core of the present invention to obtain efficient operation speed.

The above-mentioned embodiments are only preferred specific implementations of the present invention, and general changes and substitutions made by those skilled in the art within the scope of the technical solutions of the present invention should be included in the protection scope of the present invention.

Claims (2)

1. an advanced operation method for the number of leading zeros of a processor floating-point unit, characterized in that the method comprises the following steps: Step 100: Decoding operation to obtain the number of leading zeros of each 8-bit data: Divide the data A[8n-1:0] whose data bits are 8n-bits into 8-bit groups in order from high-bit to low-bit, respectively. The number of leading zeros in the n 8-bit data is decoded by n 8-4 decoders B _m [3:0]; wherein, B _m represents the number of leading zeros in the mth group of 8-bit data, m=1 ～n, n=1～8; Step 200: Obtain the number of leading zeros of the data A[8n-1:0] through the advance operation and logical judgment of each of the three levels, and in each level, the input data will be paired in twos, and each pair will be matched. The operation is carried out in parallel between the two; among them, when n is odd, the last pair has only one input data; Step 200 includes the following steps: Step 210: The input of the first stage is the result of the decoding operation B _m [3:0], the output is the number of leading zeros B _jk [4:0] of each 16-bit or 8-bit data, and the logical judgment is based on each pair of inputs The highest bit B _m [3] of the data, outputs the result from the look-ahead operation and/or the lower three bits B _m [2:0] of the input data; where, k=j+1, j=1,3,5,7 and j≤n; Step 220: The input of the second stage is the result B _jk [4:0] of the output of the first stage, and the output is the number of leading zeros B _jkrs [5:0] of each 32-bit, 16-bit or 8-bit data, the logic judgment basis For the highest bit B _jk [4] of each pair of input data, output the result from the look-ahead operation and/or the lower four bits B _jk [3:0] of the input data; where k=j+1, r=j+2 , s=j+3, j=1,5 and j≤n; Step 230: The input of the third stage is the result B _jkrs [5:0] of the output of the second stage, and the output is the leading zero number B of the 8n-bit data; the logic judgment basis is the highest bit B _jkrs [5] of each pair of input data , output the result from the look-ahead operation and/or the lower four bits of the input data B _jkrs [4:0]; wherein, n=1～8; The decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8'b00000001, the output data is 4'b0111; when the input data is 8' When b0000001x, the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b00001xxx, the output data is 4'b0100; when the input data is 8'b0001xxxx , the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is 8'b01xxxxxx, the output data is 4'b0001; when the input data is 8'b1xxxxxxx, the output The data is 4'b0000; where, x=0 or 1; The operation formula of data B _m [3:0] is: B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]); B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]); B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]); B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]); Among them, A[p] is the _p +1th bit of data A, and Bm[q] (q=0～3) is the q+1th bit of data Bm; among them, _p =0～7; When n=1, B ₁ is the number of leading zeros in the operation, and the operation ends; when 1<n≤8, divide B _m into pairs from high to low, and carry out the first level in parallel between each pair operation, when n is an odd number, the last pair of data is less than two data, then keep B _n for no operation, the value of B _n is directly transmitted to the next level, and the high-order bits are filled with zeros when the number of digits is insufficient; or When n=2, the operation result B ₁₂ of B ₁ and B ₂ is the number of leading zeros of the operation, and the operation ends; when 2<n≤8, enter the second-level logic judgment, and the output of the first-level logic judgment The result B _jk is divided into two pairs from high bits to low bits, and the second-level logic judgment is carried out in parallel between each pair. If the last pair is less than two data, one data is reserved and directly passed to the next level without operation. When the number is insufficient, high-order zeros are filled, where k=j+1; j=1, 3, 5, 7 and j≤n; or When 2<n≤4, B ₁₂₃₄ is the number of leading zeros of the operation, and the operation ends; when 4<n≤8, enter the third-level logic judgment, and perform the operation on the two operation results of the second-level logic judgment; Each level of lookahead operations includes: In the first-level look-ahead operation, if the high-order value B _j <8, the number of leading zeros in the pair of data is B _jk =5'b{00,B _j [2:0]}; if the high-order value B _j =8 , and the low-order value B _k <8, then the number of leading zeros in the pair of data is B _jk =5'b{01,B _k [2:0]}; if the high-order value B _j =8, and the low-order value B _k = 8, then the number of leading zeros in the pair of data is B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and only need to fill in the high-order zeros to output B _jk =5'b{ 0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n; In the second-level look-ahead operation, if the high-order value B _jk <16, the number of leading zeros in the pair of data is B _jkrs =6'b{00,B _jk [3:0]}; if the high-order value B _jk =16 , and the low-order value B _rs <16, the number of leading zeros in the pair of data is B _jkrs =6'b{01,B _rs [3:0]}; if the high-order value B _jk =16, and the low-order value B _rs = 16, then the number of leading zeros in the pair of data is B _jkrs = 6'b{100,000}; when the last pair has only one data B _jk , it is only necessary to add zeros in the high bits to output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s=j+3, j=1,5 and j≤n; In the third-level look-ahead operation, if the high-order value B ₁₂₃₄ <32, the number of leading zeros in the pair of data is B=7'b{00,B ₁₂₃₄ [4:0]}; if the high-order value B ₁₂₃₄ =32, And the low-order value B ₅₆₇₈ <32, the number of leading zeros in the pair of data is B=7'b{01,B ₅₆₇₈ [4:0]}; if the high-order value B ₁₂₃₄ =32, and the low-order value B ₅₆₇₈ =32, Then the number of leading zeros in the pair of data is B=7'b{1,000,000}; Each level of logical judgment includes: In the first-level logical judgment, if the highest bit of B _j B _j [3]=0, then output B _jk =5'b{00,B _j [2:0]}; if B _j [3]=1 , and B _k [3]=0, then output B _jk =5'b{01,B _k [2:0]}; if B _j [3]=1, and B _k [3]=1, then output B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and the output B _jk =5'b{0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n; In the second-level logical judgment, if B _jk [4]=0, then output B _jkrs =6'b{00,B _jk [3:0]}; if B _jk [4]=1, and B _rs [ 4]=0, then output B _jkrs =6'b{01,B _rs [3:0]}; if B _jk [4]=1, and B _rs [4]=1, then output B _jkrs =6'b{100,000}; when the last pair has only one data B _jk , output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s =j+3, j=1,5 and j≤n; In the third-level logic judgment, if B ₁₂₃₄ [5]=0, then output B=7'b{00, B ₁₂₃₄ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5] =0, then output B=7'b{01,B ₅₆₇₈ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5]=1, then output B=7'b{1,000,000}; When only B ₁₂₃₄ exists and no B ₅₆₇₈ exists, the number of leading zeros B=B ₁₂₃₄ . 2. A look-ahead computing system for the number of leading zeros in a floating-point unit of a processor, characterized in that it comprises: The first module is used for decoding operation to obtain the number of leading zeros per 8-bit data: the data A[8n-1:0] whose data bits are 8n bits is divided into 8-bit groups in the order from high to low. , respectively decode the number of leading zeros B _m [3:0] in the n 8-bit data through n 8-4 decoders; among them, B _m represents the number of leading zeros of the mth group of 8-bit data, m =1～n, n=1～8; The second module is used to obtain the number of leading zeros of the data A[8n-1:0] through the advance operation and logical judgment of each of the three stages, and the input data will be paired in pairs in each stage, The operation is carried out in parallel between each pair; among them, when n is an odd number, the last pair has only one input data; The decoding principle of the 8-4 decoder is that when the input data is 8'b00000000, the output data is 4'b1000; when the input data is 8'b00000001, the output data is 4'b0111; when the input data is 8' When b0000001x, the output data is 4'b0110; when the input data is 8'b000001xx, the output data is 4'b0101; when the input data is 8'b00001xxx, the output data is 4'b0100; when the input data is 8'b0001xxxx , the output data is 4'b0011; when the input data is 8'b001xxxxx, the output data is 4'b0010; when the input data is 8'b01xxxxxx, the output data is 4'b0001; when the input data is 8'b1xxxxxxx, the output The data is 4'b0000; where, x=0 or 1; The operation formula of data B _m [3:0] is: B _m [3]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]); B _m [2]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|～A[0])&(A[3]|A[2]|～A[1])&(A[3]|～A[2])&(～A[3]); B _m [1]=～(A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|((A[1]|～A[0] )&～A[1]))&(A[5]|～A[4])&(～A[5]); B _m [0]=～(A[7]|(A[6]|A[5]|(A[4]|A[3]|(A[2]|A[1]|～A[0 ])&～A[2])&～A[4])&～A[6]); Among them, A[p] is the _p +1th bit of data A, and Bm[q] (q=0～3) is the q+1th bit of data Bm; among them, _p =0～7; When n=1, B ₁ is the number of leading zeros in the operation, and the operation ends; when 1<n≤8, divide B _m into pairs from high to low, and carry out the first level in parallel between each pair operation, when n is an odd number, the last pair of data is less than two data, then keep B _n for no operation, the value of B _n is directly transmitted to the next level, and the high-order bits are filled with zeros when the number of digits is insufficient; or When n=2, the operation result B ₁₂ of B ₁ and B ₂ is the number of leading zeros of the operation, and the operation ends; when 2<n≤8, enter the second-level logic judgment, and the output of the first-level logic judgment The result B _jk is divided into two pairs from high bits to low bits, and the second-level logic judgment is carried out in parallel between each pair. If the last pair is less than two data, one data is reserved and directly passed to the next level without operation. When the number is insufficient, high-order zeros are filled, where k=j+1; j=1, 3, 5, 7 and j≤n; or When 2<n≤4, B ₁₂₃₄ is the number of leading zeros of the operation, and the operation ends; when 4<n≤8, enter the third-level logic judgment, and perform the operation on the two operation results of the second-level logic judgment; Each level of lookahead operations includes: In the first-level look-ahead operation, if the high-order value B _j <8, the number of leading zeros in the pair of data is B _jk =5'b{00,B _j [2:0]}; if the high-order value B _j =8 , and the low-order value B _k <8, then the number of leading zeros in the pair of data is B _jk =5'b{01,B _k [2:0]}; if the high-order value B _j =8, and the low-order value B _k = 8, then the number of leading zeros in the pair of data is B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and only need to fill in the high-order zeros to output B _jk =5'b{ 0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n; In the second-level look-ahead operation, if the high-order value B _jk <16, the number of leading zeros in the pair of data is B _jkrs =6'b{00,B _jk [3:0]}; if the high-order value B _jk =16 , and the low-order value B _rs <16, the number of leading zeros in the pair of data is B _jkrs =6'b{01,B _rs [3:0]}; if the high-order value B _jk =16, and the low-order value B _rs = 16, then the number of leading zeros in the pair of data is B _jkrs = 6'b{100,000}; when the last pair has only one data B _jk , it is only necessary to add zeros in the high bits to output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s=j+3, j=1,5 and j≤n; In the third-level look-ahead operation, if the high-order value B ₁₂₃₄ <32, the number of leading zeros in the pair of data is B=7'b{00,B ₁₂₃₄ [4:0]}; if the high-order value B ₁₂₃₄ =32, And the low-order value B ₅₆₇₈ <32, the number of leading zeros in the pair of data is B=7'b{01,B ₅₆₇₈ [4:0]}; if the high-order value B ₁₂₃₄ =32, and the low-order value B ₅₆₇₈ =32, Then the number of leading zeros in the pair of data is B=7'b{1,000,000}; Each level of logical judgment includes: In the first-level logical judgment, if the highest bit of B _j B _j [3]=0, then output B _jk =5'b{00,B _j [2:0]}; if B _j [3]=1 , and B _k [3]=0, then output B _jk =5'b{01,B _k [2:0]}; if B _j [3]=1, and B _k [3]=1, then output B _jk =5'b{10,000}; when n is an odd number, the last pair has only B _n , and the output B _jk =5'b{0,B _n [3:0]}; where k=j+1, j=1,3,5,7 and j≤n; In the second-level logical judgment, if B _jk [4]=0, then output B _jkrs =6'b{00,B _jk [3:0]}; if B _jk [4]=1, and B _rs [ 4]=0, then output B _jkrs =6'b{01,B _rs [3:0]}; if B _jk [4]=1, and B _rs [4]=1, then output B _jkrs =6'b{100,000}; when the last pair has only one data B _jk , output B _jkrs = 6'b{0, B _jk [4:0]}; where k=j+1, r=j+2, s =j+3, j=1,5 and j≤n; In the third-level logic judgment, if B ₁₂₃₄ [5]=0, then output B=7'b{00, B ₁₂₃₄ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5] =0, then output B=7'b{01,B ₅₆₇₈ [4:0]}; if B ₁₂₃₄ [5]=1 and B ₅₆₇₈ [5]=1, then output B=7'b{1,000,000}; When only B ₁₂₃₄ exists and no B ₅₆₇₈ exists, the number of leading zeros B=B ₁₂₃₄ .

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