CN108109973A - Chip packaging structure and manufacturing method thereof - Google Patents
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- 229910052751 metal Inorganic materials 0.000 claims description 52
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- 238000001816 cooling Methods 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
Description
技术领域technical field
本发明涉及一种芯片封装结构，特别是涉及一种具有良好散热功能的芯片封装结构及其制造方法。The invention relates to a chip packaging structure, in particular to a chip packaging structure with good heat dissipation function and a manufacturing method thereof.
背景技术Background technique
半导体封装是一种用于容纳、包覆一个或多个半导体芯片的结构，其作用在于防止芯片因受到外力或是湿气影响而造成损坏，也可以用以作为芯片散热的媒介。A semiconductor package is a structure used to accommodate and wrap one or more semiconductor chips. Its function is to prevent the chip from being damaged due to external force or moisture, and it can also be used as a medium for chip heat dissipation.
目前有一种四方形平面无引脚封装结构(Quad Flat NO-Lead package，简称为QFN package)，因为该封装结构没有设置外侧引脚(lead)，所以在包装、运送以及生产上都不会有引脚损伤(lead damage)的问题，大幅地提高了封装结构的稳定性。由于该封装结构散热效能、电性功能以及品质稳定性都很高，再加上轻、薄、短、小之特性，现在已成为导线架封装结构(Lead Frame Base Package)的主流。At present, there is a quad flat NO-Lead package (QFN package for short), because the package structure does not have an outer lead (lead), so there will be no problems in packaging, transportation and production. The problem of lead damage greatly improves the stability of the package structure. Due to the high heat dissipation efficiency, electrical function and quality stability of the package structure, coupled with the characteristics of lightness, thinness, shortness and small size, it has become the mainstream of the lead frame base package structure (Lead Frame Base Package).
一般四方形平面无引脚封装结构用以装设半导体芯片的散热基板是外露于封装结构的下表面，在使用上可以直接焊接至印刷电路板(PCB)上，并且借由该散热基板将芯片运作时所产生的热导至印刷电路板而散出。然而，印刷电路板的导热能力有限，难以作为封装结构良好的散热媒介。Generally, the heat dissipation substrate of the quadrangular planar leadless package structure used to install the semiconductor chip is exposed on the lower surface of the package structure, and can be directly welded to the printed circuit board (PCB) in use, and the chip is placed on the heat dissipation substrate by means of the heat dissipation substrate. The heat generated during operation is conducted to the printed circuit board and dissipated. However, the thermal conductivity of the printed circuit board is limited, and it is difficult to be a good heat dissipation medium for the package structure.
发明内容Contents of the invention
本发明的其中一目的在于提供一种散热基板是外露于封装结构之上表面的芯片封装结构。One object of the present invention is to provide a chip package structure in which the heat dissipation substrate is exposed on the top surface of the package structure.
本发明的其中另一目的在于提供一种散热基板是外露于封装结构之上表面的芯片封装结构的制造方法。Another object of the present invention is to provide a method for manufacturing a chip package structure in which the heat dissipation substrate is exposed on the top surface of the package structure.
本实用芯片封装结构，适用于装设在一电路板上，其特征在于，该芯片封装结构包含一散热基板、一设置于该散热基板的芯片、一设置在该散热基板及该电路板之间的导线架，以及一包覆该芯片的绝缘封装层。该散热基板包括一朝向该电路板的第一面及一相反于该第一面的第二面，该芯片是设置于该散热基板的第一面。该导线架设置于该散热基板及该电路板之间，该导线架包括多个电连接该芯片的引脚，所述引脚电连接该电路板以使该芯片借由所述引脚电连接该电路板。该绝缘封装层包覆该芯片，及该散热基板与该导线架之一部分而使该散热基板的第二面之部分与导线架之所述引脚之部分裸露出该绝缘封装层。The utility chip packaging structure is suitable for being mounted on a circuit board, and is characterized in that the chip packaging structure includes a heat dissipation substrate, a chip disposed on the heat dissipation substrate, and a chip disposed between the heat dissipation substrate and the circuit board. lead frame, and an insulating packaging layer covering the chip. The heat dissipation substrate includes a first surface facing the circuit board and a second surface opposite to the first surface, and the chip is arranged on the first surface of the heat dissipation substrate. The lead frame is arranged between the heat dissipation substrate and the circuit board, the lead frame includes a plurality of pins electrically connected to the chip, and the pins are electrically connected to the circuit board so that the chip is electrically connected through the pins the circuit board. The insulating encapsulation layer covers the chip, and a part of the heat dissipation substrate and the lead frame so that part of the second surface of the heat dissipation substrate and the part of the leads of the lead frame are exposed to the insulating encapsulation layer.
本发明所述的芯片封装结构，该散热基板的材质为金属。In the chip packaging structure of the present invention, the heat dissipation substrate is made of metal.
本发明所述的芯片封装结构，该散热基板包括一陶瓷板体及一结合于该陶瓷板体的第一金属层，该陶瓷板体具有一连接该芯片的第一表面及一相反于该第一表面的第二表面，该第一金属层结合于该陶瓷板体的第二表面以与该第二表面共同形成该散热基板之第二面。In the chip packaging structure of the present invention, the heat dissipation substrate includes a ceramic plate body and a first metal layer bonded to the ceramic plate body, the ceramic plate body has a first surface connected to the chip and a surface opposite to the first metal layer. The second surface of the first surface, the first metal layer is combined with the second surface of the ceramic board to form the second surface of the heat dissipation substrate together with the second surface.
本发明所述的芯片封装结构，该散热基板之陶瓷板体还具有多个形成于该第一表面且与该芯片电性连接的导电结构，该导线架之所述引脚分别电连接所述导电结构以使该芯片借由所述导电结构电连接所述引脚。In the chip package structure of the present invention, the ceramic body of the heat dissipation substrate further has a plurality of conductive structures formed on the first surface and electrically connected to the chip, and the pins of the lead frame are respectively electrically connected to the The conductive structure enables the chip to be electrically connected to the pins through the conductive structure.
本发明所述的芯片封装结构，该散热基板还包括多个结合至该陶瓷板体之第二表面的第二金属层，及多个嵌设于该陶瓷板体内且两端贯穿该陶瓷板体之第一表面与第二表面的导接线路，所述导接线路的一端连接于所述第二金属层且另一端连接于部分之所述导电结构。In the chip packaging structure of the present invention, the heat dissipation substrate further includes a plurality of second metal layers bonded to the second surface of the ceramic board, and a plurality of second metal layers embedded in the ceramic board with both ends passing through the ceramic board Conducting lines on the first surface and the second surface, one end of the conducting line is connected to the second metal layer and the other end is connected to a part of the conductive structure.
本发明所述的芯片封装结构，该散热基板的第一金属层的材质为铜，且该第一金属层是以共晶键合、电镀方式或是厚膜印刷技术结合于该陶瓷板体之该第二表面。In the chip packaging structure of the present invention, the material of the first metal layer of the heat dissipation substrate is copper, and the first metal layer is bonded to the ceramic board by eutectic bonding, electroplating or thick film printing technology. the second surface.
本发明所述的芯片封装结构，该散热基板之陶瓷板体的材质为氮化铝或是氧化铝。According to the chip package structure of the present invention, the material of the ceramic body of the heat dissipation substrate is aluminum nitride or aluminum oxide.
本发明所述的芯片封装结构，该散热基板还包括一设置于该第一金属层上以供一散热片贴附的导热金属层。According to the chip packaging structure of the present invention, the heat dissipation substrate further includes a heat conduction metal layer disposed on the first metal layer for attaching a heat dissipation sheet.
本发明所述的芯片封装结构的制造方法，适用于制作一装设在一电路板上的芯片封装结构，其特征在于，该制造方法包含以下步骤：(A)提供一散热基板及一导线架，该散热基板包括相反的一第一面及一第二面，并将一芯片设置在该散热基板的第一面；该导线架包括多个引脚；(B)令该散热基板之第一面朝向下而面对所述导线架之每一引脚的连接面，并使该芯片及导线架之所述引脚电性连接；及(C)形成一包覆该芯片，及该散热基板与该导线架之一部分的绝缘封装层而使该散热基板的第二面之部分与导线架之所述引脚之部分裸露出该绝缘封装层。The manufacturing method of the chip packaging structure of the present invention is suitable for making a chip packaging structure mounted on a circuit board, and is characterized in that the manufacturing method includes the following steps: (A) providing a heat dissipation substrate and a lead frame , the heat dissipation substrate includes an opposite first surface and a second surface, and a chip is arranged on the first surface of the heat dissipation substrate; the lead frame includes a plurality of pins; (B) the first surface of the heat dissipation substrate Facing downwards and facing the connecting surface of each pin of the lead frame, and electrically connecting the chip and the pins of the lead frame; and (C) forming a wrapping chip and the heat dissipation substrate Part of the insulating packaging layer and a part of the lead frame expose the insulating packaging layer to the part of the second surface of the heat dissipation substrate and the part of the lead of the lead frame.
本发明所述的芯片封装结构的制造方法，该步骤(A)的散热基板包括一陶瓷板体及一结合于该陶瓷板体的第一金属层，该陶瓷板体具有一连接该芯片的第一表面及一相反于该第一表面的第二表面，该第一金属层结合于该陶瓷板体的第二表面以与该第二表面共同形成该散热基板之第二面。In the manufacturing method of the chip packaging structure according to the present invention, the heat dissipation substrate in the step (A) includes a ceramic plate body and a first metal layer bonded to the ceramic plate body, and the ceramic plate body has a first metal layer connected to the chip A surface and a second surface opposite to the first surface, the first metal layer is bonded to the second surface of the ceramic board to jointly form the second surface of the heat dissipation substrate with the second surface.
本发明所述的芯片封装结构的制造方法，芯片封装结构的制造方法该还包含一在该步骤(C)之后的步骤(D)，于该散热基板的第一金属层上镀覆一可供一散热片贴附的导热金属层。The manufacturing method of the chip packaging structure described in the present invention, the manufacturing method of the chip packaging structure also includes a step (D) after the step (C), plating a metal layer on the first metal layer of the heat dissipation substrate. A thermally conductive metal layer attached to the heat sink.
本发明的有益效果在于：用以装设芯片的散热基板是外露于封装结构的上表面，芯片运作时所产生的热会导至上表面散出。相较于习知的封装结构将芯片运作时所产生的热导至印刷电路板的方式更能有效散除芯片产生的废热。The beneficial effect of the invention is that: the heat dissipation substrate used for mounting the chip is exposed on the upper surface of the packaging structure, and the heat generated during the operation of the chip will be led to the upper surface and dissipated. Compared with the conventional packaging structure, which conducts the heat generated during the operation of the chip to the printed circuit board, it can more effectively dissipate the waste heat generated by the chip.
附图说明Description of drawings
图1是本发明芯片封装结构之制造方法的一实施例之一步骤流程方块图；Fig. 1 is a flow block diagram of one step of an embodiment of the manufacturing method of the chip packaging structure of the present invention;
图2至7是该实施例之流程示意图；及2 to 7 are schematic flow diagrams of this embodiment; and
图8是一示意图，说明该实施例之一步骤S5完成时的态样。FIG. 8 is a schematic diagram illustrating the state when step S5 of this embodiment is completed.
具体实施方式Detailed ways
下面结合附图以及实施例对本发明进行详细说明。The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.
参阅图1，是本发明芯片封装结构之制造方法的一实施例，适用于制作一装设在一电路板7(见图7)上的芯片封装结构。以下配合图2至图8具体说明本实施例之实施步骤。Referring to FIG. 1 , it is an embodiment of the manufacturing method of the chip packaging structure of the present invention, which is suitable for making a chip packaging structure mounted on a circuit board 7 (see FIG. 7 ). The implementation steps of this embodiment will be described in detail below with reference to FIG. 2 to FIG. 8 .
参阅图2、3，步骤S1以及步骤S2：在执行步骤S3之组装前，要先执行步骤S1、S2以制备、提供一散热基板1以及一导线架3，并将一芯片2设置在该散热基板1，该步骤S1与步骤S2没有特定之执行先后顺序关系。该散热基板1包括相反的一第一面11以及一第二面12、一陶瓷板体13以及一结合于该陶瓷板体13的第一金属层14。该散热基板1的陶瓷板体13之材质可以是氮化铝或是氧化铝且该散热基板1具有一连接该芯片2的第一表面131，以及一相反于该第一表面131的第二表面132。该芯片2借由银胶黏贴在该陶瓷板体13的第一表面131。该第一金属层14的材质可以是铜，且是以共晶键合方式将一金属箔片结合于该陶瓷板体13之第二表面132，或是透过电镀方式形成于该陶瓷板体13之第二表面132，或是通过厚膜印刷技术使其结合于该陶瓷板体13之第二表面132，以与该陶瓷板体13之第二表面132共同形成该散热基板1的第二面12。该陶瓷板体13还具有多个形成于该第一表面131且借由打线接合之方式与该芯片2电性连接的导电结构133。Referring to Figures 2 and 3, step S1 and step S2: before performing the assembly of step S3, first perform steps S1 and S2 to prepare and provide a heat sink substrate 1 and a lead frame 3, and place a chip 2 on the heat sink For the substrate 1, there is no specific sequence relationship between step S1 and step S2. The heat dissipation substrate 1 includes a first surface 11 and a second surface 12 opposite to each other, a ceramic plate 13 and a first metal layer 14 combined with the ceramic plate 13 . The ceramic body 13 of the heat dissipation substrate 1 can be made of aluminum nitride or aluminum oxide, and the heat dissipation substrate 1 has a first surface 131 connected to the chip 2, and a second surface opposite to the first surface 131. 132. The chip 2 is pasted on the first surface 131 of the ceramic board 13 by silver glue. The material of the first metal layer 14 can be copper, and a metal foil is bonded to the second surface 132 of the ceramic board 13 by eutectic bonding, or formed on the ceramic board by electroplating. 13 of the second surface 132, or through the thick film printing technology to make it bonded to the second surface 132 of the ceramic plate 13, so as to form the second surface of the heat dissipation substrate 1 together with the second surface 132 of the ceramic plate 13. Surface 12. The ceramic board 13 also has a plurality of conductive structures 133 formed on the first surface 131 and electrically connected to the chip 2 by wire bonding.
在本实施例中，该散热基板1还包括多个结合至该陶瓷板体13之第二表面132的第二金属层15，以及多个嵌设于该陶瓷板体13内且两端分别贯穿该陶瓷板体13之第一表面131与第二表面132的导接线路16。所述导接线路16的一端连接于所述第二金属层15且另一端连接于部分之所述导电结构133，以使该芯片2借由连接所述导接线路16的导电结构133与该第二金属层15电性连接。该导线架3包括多个引脚31并且暂时地固定在一胶带8上，每一引脚31包括一供该胶带8黏贴之黏贴面311以及一相反于该黏贴面311的连接面312。In this embodiment, the heat dissipation substrate 1 further includes a plurality of second metal layers 15 bonded to the second surface 132 of the ceramic plate body 13, and a plurality of second metal layers 15 embedded in the ceramic plate body 13 with two ends respectively penetrating through The conductive lines 16 of the first surface 131 and the second surface 132 of the ceramic plate body 13 . One end of the conductive line 16 is connected to the second metal layer 15 and the other end is connected to a part of the conductive structure 133, so that the chip 2 is connected to the conductive structure 133 of the conductive line 16 and the The second metal layer 15 is electrically connected. The lead frame 3 includes a plurality of pins 31 and is temporarily fixed on an adhesive tape 8, each pin 31 includes an adhesive surface 311 for the adhesive tape 8 to be pasted and a connection surface opposite to the adhesive surface 311 312.
参阅图4，步骤S3：本步骤要进行该散热基板1与该导线架3之组装，具体是令该散热基板1之第一面11朝向下，且于组装前将该导线架3安置于该散热基板1的下方，再使该芯片2以及导线架3之所述引脚31连接以形成电性连接。在本实施例中该散热基板1与该导线架3的连接方式是在该陶瓷板体13的导电结构133上点银胶以及在所述引脚31之连接面312上打上金属线，再将导电结构133上之银胶与金属线接合，以使该散热基板1连接该导线架3且使所述引脚31与该芯片2电性连接。在组装完成后，该散热基板1之第一面11是朝向下而且面对所述导线架3之每一引脚31的连接面312。Referring to Fig. 4, Step S3: In this step, the assembly of the heat dissipation substrate 1 and the lead frame 3 is carried out. Specifically, the first surface 11 of the heat dissipation substrate 1 faces downward, and the lead frame 3 is placed on the lead frame 3 before assembly. Below the heat dissipation substrate 1 , the chip 2 and the pins 31 of the lead frame 3 are connected to form an electrical connection. In this embodiment, the heat dissipation substrate 1 is connected to the lead frame 3 by dotting silver glue on the conductive structure 133 of the ceramic board body 13 and putting metal wires on the connection surface 312 of the pin 31, and then The silver paste on the conductive structure 133 is bonded with metal wires, so that the heat dissipation substrate 1 is connected to the lead frame 3 and the pins 31 are electrically connected to the chip 2 . After the assembly is completed, the first surface 11 of the heat dissipation substrate 1 faces downward and faces the connecting surface 312 of each pin 31 of the lead frame 3 .
参阅图5，步骤S4：完成该散热基板1与该导线架3之组装后，本步骤会形成一包覆该芯片2、该散热基板1与该导线架3的绝缘封装层4。待步骤S1、S3中所涂布的银胶固化、干燥后，以流体状或粉末状的绝缘材料包覆该芯片2、该散热基板1与该导线架3，待绝缘材料固结后即形成覆盖并密封该芯片2的绝缘封装层4。该绝缘封装层4用以防御辐射、水气、氧气，以及外力破坏该芯片2。适用的绝缘材料例如环氧树脂、聚亚酰胺等，或者一些在固结成形为绝缘封装层4时不会影响该芯片2性质的硅化物、氧化物等。Referring to FIG. 5 , step S4: After the assembly of the heat dissipation substrate 1 and the lead frame 3 is completed, an insulating packaging layer 4 covering the chip 2 , the heat dissipation substrate 1 and the lead frame 3 will be formed in this step. After the silver glue coated in steps S1 and S3 is solidified and dried, the chip 2, the heat dissipation substrate 1 and the lead frame 3 are covered with a fluid or powder insulating material, and the solidified form is formed after the insulating material is solidified. An insulating encapsulation layer 4 covering and sealing the chip 2 . The insulating encapsulation layer 4 is used to protect the chip 2 from being damaged by radiation, moisture, oxygen, and external force. Applicable insulating materials are epoxy resin, polyimide, etc., or some silicides, oxides, etc. that will not affect the properties of the chip 2 when they are consolidated into the insulating encapsulation layer 4 .
参阅图6、8，步骤S5：本步骤为除胶、磨刷步骤，具体是要去除黏贴于每一引脚31之黏贴面311的胶带8，并且磨刷该绝缘封装层4之上表面41，以使每一引脚31之黏贴面311裸露出该绝缘封装层4之下表面42且使该散热基板1的第二面12之部分(该第一金属层14以及所述第二金属层15)裸露出该绝缘封装层4之上表面41(见图8)。由于该散热基板1是裸露出该绝缘封装层4之上表面41，该芯片2运作时所产生之废热可经由该散热基板1导出该绝缘封装层4之外，比起现有的芯片封装结构将废热导至电路板散出的方式更能有效散除该芯片2产生的废热。Referring to Figures 6 and 8, step S5: This step is the step of removing glue and brushing, specifically removing the adhesive tape 8 pasted on the adhesive surface 311 of each pin 31, and brushing the insulating packaging layer 4 surface 41, so that the adhesive surface 311 of each pin 31 exposes the lower surface 42 of the insulating packaging layer 4 and makes the part of the second surface 12 of the heat dissipation substrate 1 (the first metal layer 14 and the first metal layer 14 The second metal layer 15) exposes the upper surface 41 of the insulating packaging layer 4 (see FIG. 8 ). Since the heat dissipation substrate 1 exposes the upper surface 41 of the insulating packaging layer 4, the waste heat generated during the operation of the chip 2 can be exported to the outside of the insulating packaging layer 4 through the heat dissipation substrate 1, compared with the existing chip packaging structure The way of dissipating the waste heat to the circuit board can more effectively dissipate the waste heat generated by the chip 2 .
参阅图7，步骤S6：本步骤是于该散热基板1镀覆一导热金属层17。该导热金属层17是镀覆在该散热基板1的第一金属层14以及第二金属层15上。在本实施例中，还可以在该绝缘封装层4之上表面41装设一散热片9以增进该芯片封装结构的散热能力。而该导热金属层17可以是锡、锡银合金，或是化镍浸金(Electroless Nickel Immersion Gold，简称为ENIG)，其作用在于增加该第一金属层14之机械强度、导热能力，以及抗腐蚀能力。此外，欲将该芯片封装结构装设在该电路板7之前，也须在导线架3之所述引脚31的黏贴面311镀锡、锡银合金，或是化镍浸金，以保护所述引脚31。于该第一金属层表面以及所述引脚之黏贴面311镀覆金属即完成该芯片封装结构的制作。Referring to FIG. 7 , step S6 : this step is to coat a heat-conducting metal layer 17 on the heat dissipation substrate 1 . The thermally conductive metal layer 17 is plated on the first metal layer 14 and the second metal layer 15 of the heat dissipation substrate 1 . In this embodiment, a heat sink 9 can also be installed on the upper surface 41 of the insulating packaging layer 4 to improve the heat dissipation capability of the chip packaging structure. The thermally conductive metal layer 17 can be tin, tin-silver alloy, or Electroless Nickel Immersion Gold (ENIG for short), and its function is to increase the mechanical strength, thermal conductivity, and resistance of the first metal layer 14 Corrosion ability. In addition, before the chip packaging structure is installed on the circuit board 7, the adhesive surface 311 of the pin 31 of the lead frame 3 must be tin-plated, tin-silver alloy, or nickel-immersion gold to protect it. The pin 31. Plating metal on the surface of the first metal layer and the bonding surface 311 of the leads completes the fabrication of the chip package structure.
在本实施例中，该绝缘封装层4的上表面41与下表面42都具有电性输入/输出(I/O)的电性接点，使用上较具有弹性。但是在其他实施态样时也可以仅设置输入/输出在该绝缘封装层4之下表面42，于此情形下即不须在该陶瓷板体13之第二表面132设置所述第二金属层15也无须设置贯穿陶瓷板体13的所述导接线路16。此外，该散热基板1也可以是单一金属板，由于金属材料之热膨胀系数较陶瓷材料大，所以遇热时较易膨胀变形而导致结构崩坏。又因陶瓷材料之热膨胀系数与半导体芯片较为接近，在频繁冷热循环下较不会受到应力影响而分离，所以该散热基板1较佳为使用陶瓷材料。In this embodiment, both the upper surface 41 and the lower surface 42 of the insulating packaging layer 4 have electrical input/output (I/O) electrical contacts, which are relatively flexible in use. However, in other implementations, it is also possible to only set the input/output on the lower surface 42 of the insulating packaging layer 4. In this case, it is not necessary to set the second metal layer on the second surface 132 of the ceramic plate 13. 15 also does not need to be provided with the said conductive line 16 that runs through the ceramic plate body 13. In addition, the heat dissipation substrate 1 can also be a single metal plate. Since the thermal expansion coefficient of the metal material is larger than that of the ceramic material, it is easier to expand and deform when heated, resulting in structural collapse. And because the coefficient of thermal expansion of the ceramic material is closer to that of the semiconductor chip, it is less likely to be separated by stress under frequent cooling and heating cycles, so the heat dissipation substrate 1 is preferably made of a ceramic material.
综上所述，本发明芯片封装结构之制造方法所制得之芯片封装结构，用以装设芯片2的散热基板1是外露于绝缘封装层4的上表面41，芯片2运作时所产生的热会导至上表面41散出。比起已知的芯片封装结构是将芯片运作时所产生的热导至印刷电路板的方式更能有效散除芯片产生的废热。此外，本案提出的制造方法，能以简洁高效的方式实现芯片封装结构之制作，有助于良率之提升及成本之降低。故本发明芯片封装结构及其制造方法，确实能达成本发明之目的。To sum up, in the chip package structure produced by the manufacturing method of the chip package structure of the present invention, the heat dissipation substrate 1 for installing the chip 2 is exposed on the upper surface 41 of the insulating package layer 4, and the heat produced by the chip 2 during operation The heat will be conducted to the upper surface 41 and dissipated. Compared with the known chip package structure, which conducts the heat generated during the operation of the chip to the printed circuit board, it can effectively dissipate the waste heat generated by the chip. In addition, the manufacturing method proposed in this case can realize the manufacturing of the chip packaging structure in a simple and efficient manner, which is helpful to improve the yield rate and reduce the cost. Therefore, the chip packaging structure and the manufacturing method thereof of the present invention can indeed achieve the purpose of the present invention.
以上所述，仅为本发明的实施例而已，当不能以此限定本发明实施的范围，即大凡依本发明权利要求书及专利说明书内容所作的简单的等效变化与修饰，皆仍属本发明专利涵盖的范围内。The foregoing is only an embodiment of the present invention, and should not limit the scope of the present invention with this, that is, all simple equivalent changes and modifications made according to the claims of the present invention and the content of the patent specification are still within the scope of this invention. within the scope of invention patents.
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