CN108110008B - Semiconductor element and manufacturing method thereof and manufacturing method of memory - Google Patents

Abstract

The present invention discloses a semiconductor element and a manufacturing method thereof and a manufacturing method of a memory. The manufacturing method of the semiconductor element comprises: forming a first channel and a second channel in a substrate and a material layer thereon, wherein the width of the first channel is smaller than that of the second channel; forming a covering material layer and a flow isolation material filling the first and second channels; removing part of the flow isolation material in the second channel so that the thickness of the flow isolation material on the sidewall of the second channel is between 1000 and 2000 mm; and removing the flow isolation material from the second channel so that the flow isolation material on the sidewall of the second channel is between 1000 and 2000 mm.

to

between; forming a non-flowable isolation material on the flowable isolation material.

Description

Semiconductor element, method for manufacturing the same, and method for manufacturing memory

technical field

The present invention relates to a semiconductor element, a method for manufacturing the same, and a method for manufacturing a memory.

Background technique

In current semiconductor processes, isolation structures are usually formed in a substrate to define active regions and peripheral regions. For the non-volatile memory technology, a memory cell region is defined between the isolation structures occupying a large layout area, and an isolation structure occupying a smaller layout area also exists in the memory cell region. As the size of the device continues to shrink, when forming the above-mentioned isolation structure, the isolation material is filled into the trenches formed in the substrate to avoid voids in the formed isolation structure. At present, various technologies for isolation structures have been developed to improve device performance.

SUMMARY OF THE INVENTION

The present invention provides a method for manufacturing a semiconductor element, which can avoid damage to the sidewall and bottom of a trench when forming an isolation structure, and can avoid the problem of misalignment caused by the stress generated by the isolation structure.

The present invention provides a semiconductor element formed by the above-described manufacturing method.

The present invention provides a method for manufacturing a memory, which can manufacture a memory with better reliability.

至

之间；于所述流动性隔离材料上形成非流动性隔离材料。The manufacturing method of the semiconductor element of the present invention includes the following steps: forming a material layer on a substrate; forming a first channel and a second channel in the material layer and the substrate, and the width of the first channel is less than the width of the second channel; forming a fluid isolation material, covering the material layer and filling the first channel and the second channel; removing part of the second channel fluid isolation material such that the thickness of the fluid isolation material on the sidewall of the second channel is between

to

between; forming a non-flowable insulation material on the flowable insulation material.

In an embodiment of the method for manufacturing a semiconductor element of the present invention, the thickness of the fluid isolation material on the bottom of the second channel is, for example, greater than

In an embodiment of the method for manufacturing a semiconductor device of the present invention, after forming the first channel and the second channel and before forming the fluid isolation material, the substrate and the A buffer layer is formed on the material layer.

In an embodiment of the method for manufacturing a semiconductor element of the present invention, the method further includes curing the fluid isolation material.

In an embodiment of the method for manufacturing a semiconductor device of the present invention, the distance between the top surface of the fluid isolation material on the bottom of the second channel and the top surface of the substrate is, for example, greater than 1/3 of the distance between the top surface of the substrate and the bottom of the second channel.

至

之间。The semiconductor element of the present invention includes a material layer, a first isolation material layer and a second isolation material layer. The material layer is disposed on the substrate, wherein the material layer and the substrate have a first channel and a second channel, and the width of the first channel is smaller than the width of the second channel. The first isolation material layer is disposed in the first channel and on the sidewalls and the bottom of the second channel. A second isolation material layer is disposed on the first isolation material layer in the second channel. In addition, the thickness of the first isolation material layer on the sidewall of the second channel is between

to

between.

In an embodiment of the semiconductor device of the present invention, the thickness of the portion of the first isolation material layer located on the bottom of the second channel is, for example, greater than

In an embodiment of the semiconductor device of the present invention, the distance between the top surface of the first isolation material layer on the bottom of the second channel and the top surface of the substrate is, for example, greater than that of the substrate 1/3 of the distance between the top surface of the second channel and the bottom of the second channel.

至

之间；于所述第二沟道中的所述流动性隔离材料上形成非流动性隔离材料；移除所述第一沟道中的部分所述流动性隔离材料；于所述浮置栅极上形成栅间介电层；以及于所述栅间介电层上形成控制栅极。The manufacturing method of the memory of the present invention includes the following steps: sequentially forming a gate dielectric material layer and a gate material layer on a substrate; forming on the substrate, the gate dielectric material layer and the gate material layer A plurality of first channels and a plurality of second channels, a gate dielectric layer and a floating gate are defined on the substrate, and the width of the first channels is smaller than the width of the second channels Filling the first channel and the second channel with a fluid isolation material; removing part of the fluid isolation material in the second channel so that it is located on the sidewall of the second channel The thickness of the fluid barrier material on the

to

between; forming a non-fluid isolation material on the fluid isolation material in the second channel; removing a portion of the fluid isolation material in the first channel; on the floating gate forming an inter-gate dielectric layer; and forming a control gate on the inter-gate dielectric layer.

In an embodiment of the method for manufacturing a memory of the present invention, the distance between the top surface of the fluid isolation material on the bottom of the second channel and the top surface of the substrate is, for example, greater than the distance 1/3 of the distance between the top surface of the substrate and the bottom of the second channel.

Based on the above, in the present invention, after filling the larger trench with the fluid isolation material, part of the fluid isolation material in the trench is first removed before performing subsequent processes. In this way, the stress can be effectively released to solve the problem of misalignment caused by the isolation material, thereby improving the reliability of the device.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A to 1F are schematic cross-sectional views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

【Symbol Description】

100: base

102: Gate dielectric material layer

102a: gate dielectric layer

104: Gate material layer

104a: floating gate

106: first channel

108: Second channel

110: Buffer layer

112: Fluid isolation material

114: Patterned mask layer

116, 118: Isolation structure

120: Inter-gate dielectric layer

122: Control Gate

D1, D2: distance

T1, T2: Thickness

Detailed ways

1A to 1F are schematic cross-sectional views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

First, referring to FIG. 1A , a material layer is formed on the substrate 100 . The substrate 100 is, for example, a silicon substrate. In this embodiment, the material layer includes a gate dielectric material layer 102 and a gate material layer 104 formed on the substrate 100 in sequence. In other embodiments, if the semiconductor element to be formed is not a non-volatile memory, the above-mentioned material layers may be other types of film layers according to actual needs. In this embodiment, the gate dielectric material layer 102 is, for example, an oxide layer, and the gate material layer 104 is, for example, a polysilicon layer or a metal layer. In an embodiment of a non-volatile memory, in the memory region, the gate dielectric material layer 102 acts as a tunneling dielectric layer. Electrons can be stored in the floating gate through the tunneling dielectric layer. In the logic element region, the gate dielectric material layer 102 serves as a gate dielectric layer of a field effect transistor (FET). In some embodiments, a hard mask layer (not shown) is formed on the gate material layer 104 . The above-mentioned hard mask layer may include a composition of oxygen or nitrogen.

Then, referring to FIG. 1B , a plurality of first channels 106 and a plurality of second channels 108 are formed in the substrate 100 , the gate dielectric material layer 102 and the gate material layer 104 , wherein the width of the first channels 106 is less than The width of the second channel 108 . In FIG. 1B , for the clarity of the drawing, only two first channels 106 and two second channels 108 are shown, but the number of the first channels 106 and the second channels 108 is not limited thereto. In this embodiment, the second channel 108 surrounds the first channel 106 , and the first channel 106 and the second channel 108 define the substrate 100 to define a memory cell region with the first channel 106 and a memory cell region with the second channel The surrounding area of Road 108. The first channel 106 and the second channel 108 are formed by, for example, performing a patterning process on the gate material layer 104 , the gate dielectric material layer 102 and the substrate 100 . In addition, after the above patterning process is performed, the gate material layer 104 and the gate dielectric material layer 102 are respectively defined as a floating gate 104a and a gate dielectric layer 102a.

至

之间。然后，于基底100上形成流动性隔离材料112，以覆盖浮置栅极104a并填满第一沟道106与第二沟道108。流动性隔离材料112例如是氧化物材料，其例如是通过旋转涂布的方式形成于基底100上。流动性隔离材料112可包括硅酸盐或甲基硅倍半氧烷(methylsilsesquioxane，MSQ)。由于流动性隔离材料112与一般以沉积工艺所形成的材料相比具有较高的流动性，因此可以有效地填入第一沟道106与第二沟道108中，不会因流动性不佳而于填入宽度较小的第一沟道106之后产生孔隙。之后，可对流动性隔离材料112进行半固化处理。上述的半固化处理例如是在200℃至300℃的温度以及水蒸气或氧气下进行10分钟至30分钟。Next, referring to FIG. 1C , a buffer layer 110 is selectively formed on the substrate 100 . In this embodiment, the buffer layer 110 is conformally formed on the substrate 100 to cover the floating gate 104 a , the gate dielectric layer 102 a and the substrate 100 . The buffer layer 110 is, for example, an oxide layer, and the formation method thereof is, for example, an atomic layer deposition (ALD) process or a high temperature oxidation (HTO) process. The thickness of the buffer layer 110 is, for example, between

to

between. Then, a fluid isolation material 112 is formed on the substrate 100 to cover the floating gate 104 a and fill the first channel 106 and the second channel 108 . The fluid isolation material 112 is, for example, an oxide material, which is formed on the substrate 100 by, for example, spin coating. The flow isolation material 112 may include silicate or methylsilsesquioxane (MSQ). Since the fluid isolation material 112 has higher fluidity compared with the materials generally formed by the deposition process, it can effectively fill the first channel 106 and the second channel 108 without poor fluidity. The voids are generated after filling the first channel 106 with a smaller width. After that, the fluid barrier material 112 may be semi-cured. The above-mentioned semi-curing treatment is performed, for example, at a temperature of 200° C. to 300° C. and water vapor or oxygen for 10 minutes to 30 minutes.

In particular, in this embodiment, since the buffer layer 110 is formed before the fluid isolation material 112 is formed, the fluid isolation material 112 can be prevented from entering the floating gate 104a and the gate dielectric layer during the process 102a or the substrate 100, resulting in a problem that the reliability of the device is reduced.

In addition, when the fluid isolation material 112 is semi-cured, the fluid isolation material 112 located in the wider second channel 108 will generate greater stress, thereby causing the surrounding substrate 100 and the floating gate to be affected. 104a creates a misalignment problem. Therefore, in the following steps, a portion of the fluid isolation material 112 in the second channel 108 is removed to relieve stress.

至

之间，且于第二沟道108的侧壁上的流动性隔离材料112的厚度T1实质上是均一的；位于第二沟道108的底部上的流动性隔离材料112的顶表面与基底100的顶表面之间的距离D1大于基底100的顶表面与第二沟道108的底部之间的距离D2的1/3。此外，在本实施例中，位于第二沟道108的底部上的流动性隔离材料112的厚度T2例如大于

Then, referring to FIG. 1D , a patterned mask layer 114 is formed on the semi-cured fluid isolation material 112 . The patterned mask layer 114 exposes a portion of the flowable isolation material 112 over the second channel 108 , eg, exposes the flowable isolation material 112 over a central portion of the second channel 108 . The patterned mask layer 114 is, for example, a patterned photoresist layer. Next, using the patterned mask layer as an etching mask, an anisotropic etching process is performed to remove part of the exposed fluid isolation material 112 . In detail, after the partially exposed fluid isolation material 112 is removed, the fluid isolation material 112 remaining in the second channel 108 must meet the following conditions: flow on the sidewall of the second channel 108 The thickness T1 of the insulating material 112 is between

to

The thickness T1 of the fluid isolation material 112 on the sidewall of the second channel 108 is substantially uniform; the top surface of the fluid isolation material 112 on the bottom of the second channel 108 and the substrate 100 The distance D1 between the top surfaces of the substrate 100 is greater than 1/3 of the distance D2 between the top surface of the substrate 100 and the bottom of the second channel 108 . In addition, in this embodiment, the thickness T2 of the fluid isolation material 112 on the bottom of the second channel 108 is, for example, greater than

时，将无法有效地达成释放应力的目的。当厚度T1少于

时，第二沟道108的侧壁处的基底100、栅介电层102a与浮置栅极104a有可能在蚀刻工艺中受到损坏，且在基底100或浮置栅极104a中具有掺质的情况下可能会有掺质漏失的问题。此外，在距离D1未大于距离D2的1/3的情况下，第二沟道108中保留有过多的流动性隔离材料112，因此也无法有效地达成释放应力的目的。然而，厚度T2较佳需大于

以避免第二沟道108下方的基底100在蚀刻工艺中受到损坏。换句话说，当厚度T1、厚度T2与距离D1在上述范围内时，可以有效地达到释放应力的目的，且可避免基底100、栅介电层102a与浮置栅极104a在蚀刻工艺中受到损坏，以及可防止基底100或浮置栅极104a中的掺质漏失，进而提高后续所形成的元件的可靠度。When the thickness T1 exceeds

, it will not be able to effectively achieve the purpose of stress relief. When the thickness T1 is less than

, the substrate 100 , the gate dielectric layer 102 a and the floating gate 104 a at the sidewalls of the second channel 108 may be damaged during the etching process, and the substrate 100 or the floating gate 104 a has dopant 100 . In some cases, there may be a problem of dopant leakage. In addition, when the distance D1 is not greater than 1/3 of the distance D2, too much fluid isolation material 112 remains in the second channel 108, so the purpose of stress relief cannot be effectively achieved. However, the thickness T2 is preferably greater than

In order to avoid damage to the substrate 100 under the second channel 108 during the etching process. In other words, when the thickness T1 , the thickness T2 and the distance D1 are within the above ranges, the purpose of stress relief can be effectively achieved, and the substrate 100 , the gate dielectric layer 102 a and the floating gate 104 a can be prevented from being affected during the etching process. damage, and the leakage of dopants in the substrate 100 or the floating gate 104a can be prevented, thereby improving the reliability of the subsequently formed device.

Next, referring to FIG. 1E , after removing part of the fluid isolation material 112 in the second channel 108 , the patterned mask layer 114 is removed. Then, the fluid insulating material 112 is cured. The above-mentioned curing treatment is, for example, a multi-stage curing treatment: firstly at a temperature of 300°C to 500°C and under water vapor or oxygen for 10 minutes to 30 minutes, and then at a temperature of 500°C to 800°C and under water vapor or oxygen for 10 minutes. minutes to 30 minutes, followed by 30 minutes to 60 minutes at a temperature of 800°C to 1100°C under nitrogen.

Then, a non-flowable isolation material is formed on the cured flowable isolation material 112 in the second channel 108 , and the non-flowable isolation material fills the second channel 108 . The above-mentioned illiquid isolation material is, for example, a high-density plasma oxide material or an oxide material formed by an enhanced high aspect ratio process (eHARP). Then, a planarization process (such as a chemical mechanical polishing process) is performed to remove the non-fluid isolation material, the cured fluid isolation material 112 and the buffer layer 110 outside the second channel 108 until the floating gate 104a is exposed . In this way, the isolation structure 116 (ie the cured fluid isolation material 112 remaining in the second channel 108 ) and the isolation structure 118 on the isolation structure 116 (ie remaining in the second channel 108 ) are formed in the second channel 108 . illiquid isolation material in the second channel 108).

After that, referring to FIG. 1F , part of the isolation structure 116 and part of the buffer layer 110 in the first channel 106 are removed to expose at least part of the sidewalls of the floating gate 104 a around the first channel 106 . Then, an inter-gate dielectric layer 120 is formed on the top surface and sidewalls of the floating gate 104a. The formation method of the inter-gate dielectric layer 120 is, for example, a chemical vapor deposition process, so as to conformally form a multi-layer structure on the top surface and sidewalls of the floating gate 104a. The inter-gate dielectric layer 120 may include two oxide layers and a nitride layer therebetween. After that, the control gate 122 is formed on the inter-gate dielectric layer 120 . The material of the control gate 122 is, for example, polysilicon, and the formation method thereof is, for example, chemical vapor deposition. The removal of the isolation structure 116 and the buffer layer 110 in the first channel 106 can increase the contact area between the floating gate 104a and the control gate 122 . Therefore, the coupling ratio between the floating gate 104a and the control gate 122 can be improved, so that the device can have better performance.

In this embodiment, the method of manufacturing the semiconductor element of the present invention will be described by taking the formation of a nonvolatile memory as an example. However, the semiconductor element of the present invention is not limited to the nonvolatile memory. In the above-mentioned embodiments, the material layers are replaced according to actual needs, and the steps described in FIGS. 1A to 1E can be used to form other types of semiconductor elements. For example, when the above-mentioned material layer is a polysilicon layer, the isolation structure and the metal on the active region of the substrate defined by the isolation structure can be formed according to the steps described in FIG. 1A to FIG. 1E with appropriate processes. oxide semiconductor transistors.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor device includes:

forming a material layer on a substrate;

forming a first channel and a second channel in the material layer and the substrate, wherein the width of the first channel is smaller than that of the second channel;

forming a flowable isolation material to cover the material layer and fill the first channel and the second channel;

removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between

To

To (c) to (d); and

forming a non-flowable barrier material on the flowable barrier material.

2. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the flowable isolation material on a bottom of the second trench is larger than that of the flowable isolation material

3. The method of claim 1, further comprising forming a buffer layer on the substrate and the material layer after forming the first trench and the second trench and before forming the flowable isolation material.

4. The method as claimed in claim 1, further comprising curing the flowable isolation material.

5. The method of claim 1, wherein a distance between a top surface of the flowable isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.

6. A semiconductor component, comprising:

a material layer disposed on a substrate, wherein the material layer and the substrate have a first channel and a second channel, and a width of the first channel is smaller than a width of the second channel;

a first isolation material layer disposed in the first trench and on sidewalls and a bottom of the second trench; and

a second isolation material layer disposed on the first isolation material layer in the second trench, wherein the first isolation material layer on the sidewall of the second trench has a thickness between

To

In the meantime.

7. The semiconductor element of claim 6, wherein a thickness of a portion of the first isolation material layer on a bottom of the second trench is greater than a thickness of a portion of the first isolation material layer on a bottom of the second trench

8. The semiconductor component of claim 6 wherein a distance between a top surface of the first layer of isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.

9. A method of manufacturing a memory, comprising:

sequentially forming a gate dielectric material layer and a gate material layer on the substrate;

forming a plurality of first channels and a plurality of second channels in the substrate, the gate dielectric material layer and the gate material layer, and defining a gate dielectric layer and a floating gate on the substrate, wherein the width of the first channels is smaller than that of the second channels;

filling a fluid isolation material in the first trench and the second trench;

removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between

To

To (c) to (d);

forming a non-flowable isolation material on the flowable isolation material in the second channel;

removing a portion of the flowable isolation material in the first channel;

forming an inter-gate dielectric layer on the floating gate; and

and forming a control grid on the inter-grid dielectric layer.

10. The method of claim 9, wherein a distance between a top surface of the flowable isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.

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