CN108122977A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, and an electronic device, and relates to the technical field of semiconductors. The method includes: a semiconductor substrate having a first conductivity type; a body region having a first conductivity type formed in the semiconductor substrate, the body region including a first portion and a first portion above and adjacent to the first portion A second portion, wherein the second portion is close to the first surface of the semiconductor substrate, the first portion extends a first width along a first direction, and the second portion extends a second width along the first direction , the first width is smaller than the second width; a first gate structure is disposed on the first surface of the semiconductor substrate and partially extends to the body region; a second gate structure, It is arranged on the first surface of the semiconductor substrate, partially extends to the body region, and is spaced apart from the first gate structure along the first direction.

Description

A kind of semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

With the rapid development of the semiconductor industry, PIC (Power Integrated Circuit, power integrated circuit) is continuously used in many fields, such as motor control, flat panel display drive control, computer peripheral drive control, etc., the PIC circuit used Among power devices, DMOS (Double Diffused MOSFET, Double Diffused Metal Oxide Semiconductor Field Effect Transistor) has the characteristics of high operating voltage, simple process, and easy compatibility with low-voltage CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) circuits. received widespread attention.

There are two main types of DMOS: vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). LDMOS is widely adopted in the industry because it is easier to be compatible with CMOS process.

Lateral Diffusion Metal Oxide Semiconductor (LDMOS) plays an important role in the design and manufacture of integrated circuits. For example, high-voltage lateral diffusion metal oxide semiconductor transistors (HV LDMOS) are widely used in thin-film transistor liquid crystal displays. in the driver chip. In general, LDMOS transistors need to have a high breakdown voltage between drain and source (BVDS) and a low turn-on resistance (Ron) in order to improve device performance.

Wherein, as shown in FIG. 1, the traditional body region fully isolated LDMOS device uses the body region to completely isolate adjacent LDMOS devices, and the critical dimension of the body region (the gate structure 101 and the gate structure 102 of the corresponding adjacent LDMOS device The critical dimension of the gap between them) is large, and the ion implantation in the body region will not have a photoresist shielding (shielding) effect. Therefore, the pitch size between the LDMOS devices is relatively large, and increasing the size of the device is not conducive to the reduction of the integration of the device. , and the turn-on resistance (Ron) is large, which reduces the performance of the device.

Therefore, it is necessary to propose a semiconductor device and a manufacturing method thereof to solve the above technical problems.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

To address the deficiencies of the prior art, Embodiment 1 of the present invention provides a semiconductor device, including:

a semiconductor substrate having a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite the first surface;

a body region with a first conductivity type formed in the semiconductor substrate, the body region includes a first portion and a second portion above and adjacent to the first portion, wherein the second portion is adjacent to the a first surface of a semiconductor substrate, the first portion extends along a first direction with a first width, the second portion extends along the first direction with a second width, and the first width is smaller than the second width;

a first gate structure disposed on the first surface of the semiconductor substrate and partially extending to the body region;

The second gate structure is disposed on the first surface of the semiconductor substrate, partially extends to the body region, and is spaced apart from the first gate structure along the first direction.

Further, it also includes:

a source formed in the body region at the gap between the first gate structure and the second gate structure and having a second conductivity type.

Further, it also includes:

a body lead-out region, the body lead-out region is formed in the body region, and its top surface is flush with the top surface of the body region, and is spaced apart from the source along a second direction perpendicular to the first direction arranged and have the same conductivity type as the body region.

Further, it also includes:

a buried layer formed in the semiconductor substrate, the top surface of the buried layer is lower than the first surface of the semiconductor substrate, and the bottom surface of the buried layer is close to the second surface of the semiconductor substrate a surface having a second conductivity type;

a deep well region, formed on the top surface of the buried layer and adjacent to the buried layer, part of the top surface of the deep well region is adjacent to the bottom surface of the body region, and has a first conductivity type;

a first drift region formed in the semiconductor substrate below the first gate structure, located on the top surface of the deep well region, and having a second conductivity type;

The second drift region is formed in the semiconductor substrate below the second gate structure, is located on the top surface of the deep well region, and has a second conductivity type, and the body region is located on the first gate structure. Between a drift region and the second drift region, the first drift region and the second drift region are completely isolated;

a first drain formed in the first drift region outside the first gate structure and having a second conductivity type;

The second drain, formed in the second drift region outside the second gate structure, has a second conductivity type.

Further, it also includes:

a first spacer formed on the sidewall of the first gate structure;

The second spacer is formed on the sidewall of the second gate structure.

Further, the first conductivity type is N-type, and the second conductivity type is P-type, or, the first conductivity type is P-type, and the second conductivity type is N-type.

Further, the size of the gap between the first gate structure and the second gate structure is equal to the first width.

Embodiment 2 of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

A semiconductor substrate having a first conductivity type is provided, the semiconductor substrate includes a first surface and a second surface opposite to the first surface, on the first surface of the semiconductor substrate is formed a a first gate structure and a second gate structure arranged at intervals in the direction;

forming a patterned mask layer having an opening to cover the first surface of the semiconductor substrate, wherein the opening exposes a gap between the first gate structure and the second gate structure the semiconductor substrate;

performing a first ion implantation to form a first portion of a body region in the semiconductor substrate exposed in the opening, wherein the first portion of the body region extends along the first direction by a first width and has a first conductivity type ;

trimming the mask layer to enlarge the width of the opening along the first direction, exposing part of the first gate structure and the second gate structure;

performing a second ion implantation to form a second portion of the body region in the semiconductor substrate exposed in the opening, wherein the second ion implantation is an oblique ion implantation whose implantation depth is smaller than that of the first ion implantation implantation depth, the first portion and the second portion constitute the body region, the second portion of the body region extends along the first direction with a second width, has a first conductivity type, and the first width less than the second width.

Further, after forming the first gate structure and the second gate structure, the following steps are further included:

A source is formed in the semiconductor substrate at a gap between the first gate structure and the second gate structure, the source having a second conductivity type.

Further, after the second ion implantation process, the following steps are also included:

A body lead-out region is formed in the body region, the body lead-out region and the source are arranged at intervals along a second direction perpendicular to the first direction, and has the same conductivity type as the body region.

Further, before forming the patterned mask layer, the following steps are also included:

A first spacer is formed on the sidewall of the first gate structure, and a second spacer is formed on the sidewall of the second gate structure.

Further, before forming the first gate structure and the second gate structure, the following steps are also included:

forming a buried layer in the semiconductor substrate, the top surface of the buried layer is lower than the first surface of the semiconductor substrate, and the bottom surface of the buried layer is close to the second surface of the semiconductor substrate , and has a second conductivity type;

forming a deep well region on the top surface of the buried layer, the deep well region having a first conductivity type;

A drift region is formed on the top surface of the deep well region, the drift region has a second conductivity type.

Embodiment 3 of the present invention provides an electronic device, where the electronic device includes the aforementioned semiconductor device.

In summary, the body region of the semiconductor device of the present invention includes a first part and a second part, wherein the width of the first part located below is smaller than the width of the second part located above, which reduces the critical dimension of the body region, thereby reducing the The pitch size between adjacent devices is reduced, and the turn-on resistance of the device is reduced, which ultimately improves the overall performance and integration of the device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1 shows a schematic structural diagram of an existing LDMOS device;

FIG. 2 shows a schematic structural view of a semiconductor device according to an embodiment of the present invention;

3A to 3B show schematic structural views of devices obtained in related steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 4 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 5 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, detailed steps and structures will be provided in the following description, so as to explain the technical solution proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

Embodiment one

In order to solve the foregoing technical problems, the present invention provides a semiconductor device, which mainly includes:

a semiconductor substrate having a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite the first surface;

a body region with a first conductivity type formed in the semiconductor substrate, the body region includes a first portion and a second portion above and adjacent to the first portion, wherein the second portion is adjacent to the a first surface of a semiconductor substrate, the first portion extends along a first direction with a first width, the second portion extends along the first direction with a second width, and the first width is smaller than the second width;

a first gate structure disposed on the first surface of the semiconductor substrate and partially extending to the body region;

The second gate structure is disposed on the first surface of the semiconductor substrate, partially extends to the body region, and is spaced apart from the first gate structure along the first direction.

The body region of the semiconductor device of the present invention includes a first part and a second part, wherein the width of the first part located below is smaller than the width of the second part located above, which reduces the critical dimension of the body region, thereby reducing the gap between adjacent devices. The pitch size of the device is reduced, and the turn-on resistance of the device is reduced, which ultimately improves the overall performance and integration of the device.

Specifically, the semiconductor device of the present invention will be described in detail below with reference to FIG. 2 , wherein FIG. 2 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

The semiconductor device of the present invention may be an LDMOS device. In this embodiment, an LDNMOS device is mainly used as an example, as shown in FIG. 2 .

First, the semiconductor device of the present invention includes a semiconductor substrate 200 having a first conductivity type, and the semiconductor substrate may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), stack-on-insulator Silicon (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, in this embodiment, single crystal silicon is selected as the constituent material of the semiconductor substrate.

Wherein, an appropriate semiconductor substrate is selected and used according to a specific device type, for example, for LDNMOS, the semiconductor substrate 200 is a P-type substrate; for LDPMOS, the semiconductor substrate 200 may be an N-type substrate.

Further, the semiconductor substrate 200 includes a first surface 2011 and a second surface 2012 opposite to the first surface 2011 .

Exemplarily, the semiconductor device of the present invention further includes a buried layer 202, which is formed in the semiconductor substrate 200 and has a second conductivity type. For an LDNMOS device, the buried layer 202 is an N-type buried layer layer, and for LDPMOS devices, the buried layer 202 is a P-type buried layer, further, the top of the buried layer 202 is located in the semiconductor substrate 200, that is, the top of the buried layer 202 is lower than the semiconductor substrate The first surface 2011 of the bottom 200.

It is worth mentioning that in the present invention, when the semiconductor device is an LDNMOS device, the first conductivity type is P-type, and the second conductivity type is N-type, and when the semiconductor device is an LDPMOS device, the first The conductivity type is N type, and the second conductivity type is P type.

In one example, the semiconductor device of the present invention further includes a deep well region 203 formed on the top surface of the buried layer 202, the deep well region 203 has a first conductivity type, and the deep well region The top surface of the region 203 is lower than the first surface 2011 of the semiconductor substrate 200 , for example, for an LDNMOS device, the deep well region 203 is a P-type deep well region.

In one example, the semiconductor device further includes a first drift region 2041 and a second drift region 2042, the first drift region 2041 and the second drift region 2042 are formed in the semiconductor substrate and located in the deep well region 203 On the top surface of , the first drift region 2041 and the second drift region 2042 are completely isolated from each other, and both have the second conductivity type. For example, for an LDNMOS device, the first drift region 2041 and the second drift region Regions 2042 are all N-type drift regions.

Further, the semiconductor device of the present invention further includes a body region 205 having a first conductivity type, which is formed in the semiconductor substrate 200, the body region 205 includes a first portion 2051 and is located above and connected to the first portion 2051 The adjacent second portion 2052, wherein the top surface of the second portion 2052 is flush with the first surface 2011 of the semiconductor substrate 200, the first portion 2051 extends along the first direction by a first width W1, the The second portion 2052 extends along the first direction with a second width W2, the first width W1 is smaller than the second width W2, and the body region 205 completely isolates the first drift region 2041 from the second drift region. region 2042 , the bottom surface of the body region 205 is connected to part of the bottom surface of the deep well region 203 .

Exemplarily, for an LDNMOS device, the body region is a P-type body region.

In one example, on the outside of the first drift region 2041, a first well region 2061 is provided on the side opposite to the body region 205, and on the outside of the second drift region 2042, connected to the body region 205 The opposite side is also provided with a second well region 2062, the first well region and the second well region can play a certain role of isolation for isolating adjacent devices, the first well region 2061 and the second well region The bottom surface of the second well region 2062 is adjacent to part of the top surface of the buried layer 202 , and the top surfaces of the first well region 2061 and the second well region 2062 are close to the first surface of the semiconductor substrate 200 2011.

Exemplarily, both the first well region 2061 and the second well region 2062 have a first conductivity type, for example, for an LDNMOS device, the first conductivity type is P type, that is, the first well region 2061 and the second well region 2062 are both P-type well regions.

In one example, the semiconductor device further includes a first gate structure 2071 disposed on the first surface 2011 of the semiconductor substrate 200 and partially extending to the body region 205 .

In one example, the semiconductor device of the present invention further includes a second gate structure 2072, which is disposed on the first surface of the semiconductor substrate 200, and partially extends to the body region 205, and is compatible with the The first gate structures 2071 are arranged at intervals along the first direction.

Further, it also includes a first spacer 2081 formed on the sidewall of the first gate structure 2071 and a second spacer 2082 formed on the sidewall of the second gate structure 2072 .

Both the first gate structure 2071 and the second gate structure 2072 include a gate dielectric layer on the first surface of the semiconductor substrate and a gate layer on the gate dielectric layer.

The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). The gate layer is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer.

The first spacer 2081 and the second spacer 2082 may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the first spacer 2081 and the second spacer 2082 are composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first nitrogen oxide layer on a semiconductor substrate The silicon oxide layer and the second silicon oxide layer are formed, and then the spacers are formed by etching.

Further, the semiconductor device of the present invention includes a source 210, the source 210 is formed in the body region 205, located at the gap between the first gate structure 2071 and the second gate structure 2072, and It may also partially extend into the semiconductor substrate below the first gate structure 2071 and the second gate structure 2072, the source 210 has the second conductivity type, and the top surface of the source 210 is in contact with the first surface 2011 flush.

Exemplarily, as shown in FIG. 2 , the source 210 is an N-type source, and is heavily doped with N-type impurities.

In one example, as shown in the partial schematic diagram pointed by the straight arrow in FIG. are arranged at intervals along a second direction perpendicular to the first direction, and have the same conductivity type as the body region 205, for example, if the body region 205 is a P-type body region, then the body lead-out region 210 can also be a P-type , and its impurity doping concentration is greater than that of the body region, for example, the body lead-out region is heavily doped with P-type impurities. The top surface of the body lead-out region 211 is flush with the first surface, that is, the top surface thereof is flush with the top surface of the body region 205 .

Wherein, both the first direction and the second direction refer to directions parallel to the first surface 2011 of the semiconductor substrate.

Compared with the structure in the prior art where the source electrode and the body lead-out region are arranged along the first direction and are located in the gap between adjacent gate structures, in the present invention, the source electrode 210 and the body lead-out region 211 are arranged along the first direction perpendicular to the first direction. Therefore, the gap size S1 between the adjacent first gate structure 2081 and the second gate structure 2082 can also be shortened, and the gap size can only meet the size of the source electrode 210. .

Further, optionally, the gap size S1 between the first gate structure 2081 and the second gate structure 2082 is approximately equal to the first width W1.

Further, the semiconductor device of the present invention further includes a first drain 2091, which is formed in the first drift region 2041 outside the first gate structure 2081 and has a second conductivity type, for example, the first drain 2091 is an N-type drain, especially an N-type heavily doped drain.

Further, the semiconductor device of the present invention further includes a second drain 2092, which is formed in the second drift region 2042 outside the second gate structure 2082 and has a second conductivity type, for example, the first drain 2092 is an N-type drain, especially an N-type heavily doped drain.

Wherein, as shown in FIG. 2 , the body region 205 completely isolates two adjacent LDNMOS devices, and the device including the first gate structure 2081 and the first drift region 2041 on the left side of the body region 205 is an LDNMOS device. , the device including the second gate structure 2082 and the second drift region 2042 on the right side of the body region 205 is another LDNMOS device.

In one example, as shown in FIG. 2 , two adjacent LDNMOS devices share one source 210 .

So far, the description of the key components of the semiconductor device of the present invention is completed, and a complete device may also include other components, etc., which will not be repeated here.

In summary, since the body region of the semiconductor device of the present invention includes a first part and a second part, wherein the width of the first part located below is smaller than the width of the second part located above, the critical dimension of the body region is reduced, thereby reducing The pitch size between adjacent devices is reduced, the turn-on resistance of the device is reduced, and the overall performance and integration of the device are finally improved.

Embodiment two

This implementation also provides a method for manufacturing a semiconductor device in the aforementioned implementation one, as shown in FIG. 4 , which mainly includes the following steps:

Step S1, providing a semiconductor substrate having a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite to the first surface, and forming on the first surface of the semiconductor substrate a first gate structure and a second gate structure arranged at intervals along the first direction;

Step S2, forming a patterned mask layer with an opening to cover the first surface of the semiconductor substrate, wherein the opening exposes the gap between the first gate structure and the second gate structure said semiconductor substrate at the gap;

Step S3, performing a first ion implantation to form a first part of a body region in the semiconductor substrate exposed in the opening, wherein the first part of the body region extends along the first direction with a first width and has a first - conductivity type;

Step S4, trimming the mask layer to enlarge the width of the opening along the first direction, exposing part of the first gate structure and the second gate structure;

Step S5, performing a second ion implantation to form a second part of the body region in the semiconductor substrate exposed in the opening, wherein the second ion implantation is an oblique ion implantation, and its implantation depth is smaller than that of the first The implantation depth of the ion implantation, the second portion of the body region extends along the first direction with a second width, which has a first conductivity type, and the first width is smaller than the second width.

To sum up, the body region of the semiconductor device formed according to the manufacturing method of this method includes a first part and a second part, wherein the width of the first part located below is smaller than the width of the second part located above, which reduces the criticality of the body region. size, thereby reducing the pitch size between adjacent devices, and reducing the on-resistance of the device, and ultimately improving the overall performance and integration of the device.

Next, the manufacturing method of the semiconductor device in the embodiment will be described in detail with reference to FIG. 3A and FIG. 3B, wherein FIG. 3A to FIG. Schematic diagram of the device structure.

First, as shown in FIG. 3A, a semiconductor substrate 200 having a first conductivity type is provided, and the semiconductor substrate 200 includes a first surface 2011 and a second surface 2012 opposite to the first surface 2011. In the semiconductor A first gate structure 2071 and a second gate structure 2072 are formed on the first surface 2011 of the substrate 200 at intervals along the first direction.

Specifically, the semiconductor substrate 200 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, in this embodiment, single crystal silicon is selected as the constituent material of the semiconductor substrate.

Wherein, an appropriate semiconductor substrate is selected and used according to a specific device type, for example, for LDNMOS, the semiconductor substrate 200 is a P-type substrate; for LDPMOS, the semiconductor substrate 200 may be an N-type substrate.

In one example, before forming the first gate structure 2071 and the second gate structure 2072, the following steps are further included:

Step A1: forming a buried layer 202 in the semiconductor substrate 200, the top surface of the buried layer 202 is lower than the first surface 2011 of the semiconductor substrate 200, and the bottom surface of the buried layer 202 is close to the The second surface 2012 of the semiconductor substrate 200 has a second conductivity type, that is, has a conductivity type opposite to that of the semiconductor substrate 200 .

The method for forming the buried layer 202 can be a method well known to those skilled in the art, including but not limited to ion implantation. For example, for an N-type buried layer, ion implantation of N-type dopant ions, such as phosphorus or arsenic, for The P-type buried layer can be ion-implanted with P-type dopant ions, such as boron.

Step A2: forming a deep well region 203 on the top surface of the buried layer 202, the deep well region 203 has a first conductivity type, that is, has a conductivity type opposite to that of the buried layer.

For LDNMOS devices, the deep well region 203 is a P-type well region, while the buried layer 202 is an N-type well region, and the ion implantation method can be used to perform P-type dopant ion implantation into the area where the deep well region 203 is scheduled to be formed. The device needs to make the deep well region 203 have a certain depth by adjusting the implantation energy and the like.

Step A3: forming a first well region 2061 and a second well region 2062 on both sides of the deep well region 203, wherein the first well region 2061 and the second well region 2062 are both connected to the deep well region 203, The first well region 2061 and the second well region 2062 have the same conductivity type as the deep well region 202 and are used to isolate adjacent devices.

Wherein, the bottoms of the first well region 2061 and the second well region 2062 are located on part of the top surface of the buried layer 202, and the top surfaces of the first well region 2061 and the second well region 2062 and the first surface 2011 of the semiconductor substrate 200 .

Specifically, a patterned mask layer with openings can be formed, and the openings expose regions of the semiconductor substrate where the first well region and the second well region are planned to be formed, and then ion implantation, such as ion implantation of P-type doping Ions, phosphorus or arsenic, etc., to form a P-type first well region and a second well region. When the patterned mask layer is removed, the mask layer is preferably made of a photoresist material.

Step A4: forming a drift region on the top surface of the deep well region 203 between the first well region 2061 and the second well region 2062, the top surface of the drift region is in contact with the semiconductor substrate The first surface 2011 is flush, and the drift region has the second conductivity type.

Specifically, an ion implantation step is performed on the semiconductor substrate 200 to form a drift region in the semiconductor substrate. Preferably, an ion implantation process or a diffusion process is selected in this step. Preferably, the drift region is formed by mild ion implantation or doping, wherein the implanted ion type is selected according to needs, and can be N-type or P-type. For example, the ions used to form the N-type drift region are phosphorus and arsenic. One or a combination of , antimony and bismuth, or boron is selected for the P-type drift region.

Subsequently, a first gate structure 2071 and a second gate structure 2072 arranged at intervals along the first direction are formed on the first surface 2011 of the semiconductor substrate 200, wherein the first gate structure 2071 and the second gate structure A pole structure 2072 is located on the drift region.

In one example, the method for forming the first gate structure 2071 and the second gate structure 2072 includes: sequentially depositing a gate dielectric layer and a gate layer to cover the first surface of the semiconductor substrate 200 2011 , pattern the gate layer and the gate dielectric layer to form the first gate structure 2071 and the second gate structure 2072 .

The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanates (BSTs), and lead zirconate titanates (PZTs).

The gate layer is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. In this embodiment, the gate layer is made of polysilicon material.

The preferred formation methods of gate dielectric layer and gate layer include chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma Chemical vapor deposition (PECVD), generally similar methods such as sputtering and physical vapor deposition (PVD) can also be used.

Wherein, the gap size between the adjacent first gate structure 2081 and the second gate structure 2082 is S1.

Afterwards, a first spacer 2081 may also be selectively formed on the sidewall of the first gate structure 2071 , and a second spacer 2082 may be formed on the sidewall of the second gate structure 2072 .

Wherein, the first spacer 2081 and the second spacer 2082 may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the first spacer 2081 and the second spacer 2082 are composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first nitrogen oxide layer on a semiconductor substrate The silicon oxide layer and the second silicon oxide layer are formed, and then the spacers are formed by etching.

Subsequently, as shown in FIG. 3A , a source 210 is formed in the semiconductor substrate 200 at the gap between the first gate structure 2071 and the second gate structure 2072, and the source 210 has a first gate structure. Two conductivity types, the first drain 2091 is formed in the drift region outside the first gate structure 2071, and the second drain 2092 is formed in the drift region outside the second gate structure 2072, wherein, The first drain 2091 and the source 210 are respectively located on both sides of the first gate structure 2071, and the second drain 2092 and the source 210 are respectively located on both sides of the second gate structure 2092. side.

Specifically, on the first surface of the semiconductor substrate, a patterned photoresist layer exposing regions where the source electrode is to be formed, the regions where the first drain electrode is to be formed and the second drain electrode is to be formed may be formed, and then ion implantation is performed to respectively form The source 210, the first drain 2091 and the second drain 2092 have the same conductivity type.

Wherein, the doping concentration of the source 210, the first drain 2091 and the second drain 2092 is generally heavily doped, for example, for the doping of the source 210, the first drain 2091 and the second drain 2092 of the LDNOMS device The concentration is generally heavily doped with N-type dopant ions, such as heavily doped with phosphorus or arsenic.

The ion type and doping concentration in this step can be selected from the range commonly used in this field. The doping energy selected in the present invention is 1000ev-30kev, preferably 1000-10kev, so as to ensure that the doping concentration can reach 5E17-1E25 atoms/cm ³ .

Wherein, the source electrode 210 is located in the body region to be formed later.

Subsequently, as shown in FIG. 3A , a patterned mask layer 212 having an opening is formed to cover the first surface 2011 of the semiconductor substrate 200, wherein the opening exposes the first gate structure 2071 and the semiconductor substrate 200 at the gap between the second gate structure 2072 .

Specifically, the mask layer 212 may include any one of several mask materials, including but not limited to: hard mask materials and photoresist mask materials. Preferably, the masking layer comprises a photoresist masking material. The photoresist mask material may include a photoresist material selected from the group consisting of positive photoresist materials, negative photoresist materials, and hybrid photoresist materials. Typically, the mask layer includes a positive tone photoresist material or a negative tone photoresist material having a thickness from about 2000 to about 50000 Angstroms.

In one example, a photoresist mask material is coated on the first surface of the semiconductor substrate by a spin coating process, and the mask layer 212 is patterned in steps of exposure and development using a photolithography process to form a The patterned masking layer 212 of the openings.

Wherein, the opening exposes the first spacer 2081 and the second spacer 2082 located between the first gate structure 2071 and the second gate structure 2072 .

Subsequently, as shown in FIG. 3A , a first ion implantation is performed to form a first portion 2051 of a body region in the semiconductor substrate 200 exposed in the opening, wherein the first portion 2051 of the body region is along the first portion 2051 of the body region. Extending in one direction with a first width W1 and having a first conductivity type.

Specifically, the first part of the body region has a conductivity type opposite to that of the aforementioned drift region, and according to the type of device, suitable dopant ions are selected and implanted into the semiconductor substrate, wherein, for LDNOMS devices, the dopant ions may include boron Such as P-type dopant ions to form a P-type well region, and for LDPOMS devices, the dopant ions may include N-type dopant ions such as phosphorus or arsenic to form an N-type well region.

In this step, the depth of the first ion implantation can be controlled by controlling parameters such as ion implantation energy, so that the bottom of the first part 2051 of the formed body region is located on the top surface of the deep well region 203, and is in contact with the The deep well region 203 is connected.

Wherein, the first ion implantation is selected to use vertical ion implantation, that is, the implantation is performed along a direction perpendicular to the surface of the semiconductor substrate. Therefore, the first width W1 of the first portion 2051 of the body region formed in the semiconductor substrate can be approximately is equal to the gap width S1 between the first gate structure and the second gate structure. Since the ion implantation also includes the step of performing thermal annealing to activate the doping ions in the semiconductor substrate, the first gate structure of the body region The first width W1 of the part 2051 may also be slightly larger than the gap width S1.

Subsequently, as shown in FIG. 3B , the mask layer 212 is trimmed to enlarge the width of the opening along the first direction, exposing part of the first gate structure 2071 and the second gate structure 2072 .

Specifically, when the mask layer 212 includes a photoresist mask material, a part of the mask layer 212 may be removed by exposure and development using a photolithography process, so as to enlarge the width of the opening along the first direction.

Wherein, the width of the trimmed opening along the first direction is set according to the width of the second part of the body region to be formed in a subsequent step.

Subsequently, as shown in FIG. 3B , a second ion implantation is performed to form a second portion 2052 of the body region in the semiconductor substrate 200 exposed in the opening, wherein the second ion implantation is an oblique ion implantation, Its implantation depth is less than the implantation depth of the first ion implantation, the second portion 2052 of the body region extends along the first direction with a second width W2, which has the first conductivity type, and the first width W1 is less than the Describe the second width W2.

Specifically, the second part 2052 of the body region and the first part 2051 of the body region jointly constitute the body region 205, and the body region 205 divides the drift region into a first drift region 2041 and a second drift region located on both sides of the body region. Two Drift Zone 2042.

The second portion 2052 of the body region has the same conductivity type, doping concentration, etc. as the first portion 2051 of the body region.

Since the first gate structure and the second gate structure have a blocking effect on ion implantation, oblique ion implantation is used in this step to form the second portion of the body region, wherein the implantation angle of the oblique ion implantation can be determined according to a predetermined The width of the second part of the formed body region is reasonably set, for example, the implantation angle is adjusted between 0° and 45°. The implantation angle refers to the angle between the implantation direction of the second ion implantation and the normal line perpendicular to the first surface of the semiconductor substrate.

Wherein, the implantation depth of the second ion implantation is smaller than the implantation depth of the aforementioned first ion implantation, so that the second part of the formed body region is located above the first part of the body region.

Exemplarily, when the second ion implantation is performed, the implantation energy will not penetrate the gate structure, and the implantation angle can be 0 to 45 degrees, so as to realize the self-alignment process.

The second portion 2052 of the formed body region partially extends below the first gate structure 2071 and the second gate structure 2072 by oblique ion implantation.

Afterwards, as shown in FIG. 3B , it further includes forming a body lead-out region 211 in the body region 205, and the body lead-out region 211 and the source electrode 210 are arranged at intervals along a second direction perpendicular to the first direction. , and have the same conductivity type as the body region, as shown in the partial schematic diagram pointed by the straight arrow in FIG. 3B .

Specifically, the top surface of the body lead-out region 211 is flush with the first surface 2011 of the semiconductor substrate.

The body lead-out region 211 can be formed by a method commonly used by those skilled in the art such as ion implantation, and the body lead-out region 211 is generally heavily doped, and its doping concentration is greater than that of the body region.

For example, for an LDNMOS device, the P-type body lead-out region 211 is formed by ion implantation of P-type dopant ions such as boron.

Compared with the structure in the prior art where the source electrode and the body lead-out region are arranged along the first direction and are located in the gap between adjacent gate structures, in the present invention, the source electrode 210 and the body lead-out region 211 are arranged along the first direction perpendicular to the first direction. The second direction is arranged at intervals, so the gap size between the adjacent first gate structure 2081 and the second gate structure 2082 can be shortened, that is, the gap size only needs to meet the size of the source electrode 210 .

Finally, the mask layer 212 can also be removed, for example, the photoresist mask material can be removed by an ashing process.

So far, the description of the key steps of the manufacturing method of the semiconductor device of the present invention is completed, and other steps may be required for the complete device manufacturing, which will not be repeated here.

In summary, according to the manufacturing method of the present invention, an LDNMOS device with a fully isolated structure is formed. In the case of reducing the size of the gap between adjacent gate structures, the first one with a deeper implantation depth is first used. Ion implantation, and then expand the opening size by trimming the mask layer (such as photoresist mask material), and use the first gate structure and the second gate structure exposed in the opening as a mask to perform the inclined second gate structure. Ion implantation, and the depth of the second ion implantation is relatively shallow to achieve self-alignment of the implantation, thus reducing the pitch size of the LDNMOS device with a fully isolated structure, reducing the turn-on resistance of the device, and finally improving the overall performance of the device and integration.

Embodiment three

The present invention also provides an electronic device, including the semiconductor device described in Embodiment 1, and the semiconductor device is prepared according to the method described in Embodiment 2.

The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

Among them, FIG. 5 shows an example of a mobile phone handset. A mobile phone handset 500 is provided with a display portion 502 included in a casing 501, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like.

Wherein the mobile phone handset includes the semiconductor device described in Embodiment 1, and the semiconductor device mainly includes:

a semiconductor substrate having a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite the first surface;

a body region with a first conductivity type formed in the semiconductor substrate, the body region includes a first portion and a second portion above and adjacent to the first portion, wherein the second portion is adjacent to the a first surface of a semiconductor substrate, the first portion extends along a first direction with a first width, the second portion extends along the first direction with a second width, and the first width is smaller than the second width;

a first gate structure disposed on the first surface of the semiconductor substrate and partially extending to the body region;

The second gate structure is disposed on the first surface of the semiconductor substrate, partially extends to the body region, and is spaced apart from the first gate structure along the first direction.

The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (13)

1. a kind of semiconductor devices, which is characterized in that including：

Semiconductor substrate with the first conduction type, the Semiconductor substrate include first surface and with the first surface phase To second surface；

Body area with the first conduction type, is formed in the Semiconductor substrate, and the body area includes first portion and position Above the first portion and the second portion that is adjacent, wherein, the second portion is close to the Semiconductor substrate First surface, the first portion extend in a first direction the first width, and the second portion is along first direction extension the Two width, first width are less than second width；

First grid structure is arranged on the first surface of the Semiconductor substrate, and part is extended in the body area；

Second grid structure is arranged on the first surface of the Semiconductor substrate, and part is extended in the body area, And it is alternatively arranged with the first grid structure along the first direction.

2. semiconductor devices as described in claim 1, which is characterized in that further include：

Source electrode, the source electrode are formed in the body area, between the first grid structure and second grid structure between At gap, and with the second conduction type.

3. semiconductor devices as claimed in claim 2, which is characterized in that further include：

Body draw-out area, the body draw-out area are formed in the body area, and its top surface is flushed with the top surface in the body area, and described Source electrode is alternatively arranged along the second direction vertical with the first direction, and with the conduction type identical with the body area.

4. semiconductor devices as described in claim 1, which is characterized in that further include：

Buried regions is formed in the Semiconductor substrate, and the top surface of the buried regions is less than first table of the Semiconductor substrate Face, the bottom surface of the buried regions close to the Semiconductor substrate the second surface, and with the second conduction type；

Deep-well region, be formed on the top surface of the buried regions and with the buried regions abut, the portion top surface of the deep-well region with it is described The bottom surface adjoining in body area, and with the first conduction type；

First drift region is formed in the Semiconductor substrate below the first grid structure, positioned at the deep-well region On top surface, and with the second conduction type；

Second drift region is formed in the Semiconductor substrate below the second grid structure, positioned at the deep-well region On top surface, and with the second conduction type, and the body area is between first drift region and second drift region, complete Isolate first drift region and second drift region entirely；

First drain electrode, is formed in first drift region on the outside of the first grid structure, has the second conduction type；

Second drain electrode, is formed in second drift region on the outside of the second grid structure, has the second conduction type.

5. semiconductor devices as described in claim 1, which is characterized in that further include：

First clearance wall is formed on the side wall of the first grid structure；

Second clearance wall is formed on the side wall of the second grid structure.

6. semiconductor devices as described in claim 1, which is characterized in that first conduction type is N-type, and described second leads Electric type is p-type, alternatively, first conduction type is p-type, second conduction type is N-type.

7. semiconductor devices as described in claim 1, which is characterized in that the first grid structure and the second grid knot Gap size between structure is equal to first width.

8. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes：

There is provided with the first conduction type Semiconductor substrate, the Semiconductor substrate include first surface and with first table The opposite second surface in face forms along the first direction spaced first on the first surface of the Semiconductor substrate Gate structure and second grid structure；

The patterned mask layer with opening is formed, to cover the first surface of the Semiconductor substrate, wherein, the opening Expose the Semiconductor substrate of the gap location between the first grid structure and the second grid structure；

The first ion implanting is carried out, to form the first portion in body area in the Semiconductor substrate exposed in said opening, wherein, The first portion in the body area extends the first width along the first direction, has the first conduction type；

The mask layer is trimmed, to expand width of the opening along the first direction, first grid knot described in exposed portion Structure and the second grid structure；

The second ion implanting is carried out, to form the second portion in body area in the Semiconductor substrate exposed in said opening, wherein, Second ion implanting is injected for angle-tilt ion, and injection depth is less than the injection depth of first ion implanting, described First portion and the second portion form the body area, and the second portion in the body area is wide along first direction extension second Degree, has the first conduction type, and first width is less than second width.

9. manufacturing method as claimed in claim 8, which is characterized in that forming the first grid structure and the second gate It is further comprising the steps of after the structure of pole：

Source electrode is formed in the Semiconductor substrate of gap location between the first grid structure and second grid structure, institute Source electrode is stated with the second conduction type.

10. manufacturing method as claimed in claim 9, which is characterized in that after second ion implantation technology, further include Following steps：

Body draw-out area, the body draw-out area and source electrode edge vertical with the first direction second are formed in the body area Direction is alternatively arranged, and with the conduction type identical with the body area.

11. manufacturing method as claimed in claim 8, which is characterized in that before the patterned mask layer is formed, also wrap Include following steps：

The first clearance wall is formed on the side wall of the first grid structure, and is formed on the side wall of the second grid structure Second clearance wall.

12. manufacturing method as claimed in claim 8, which is characterized in that forming the first grid structure and described second It is further comprising the steps of before gate structure：

Buried regions is formed in the Semiconductor substrate, the top surface of the buried regions is less than first table of the Semiconductor substrate Face, the bottom surface of the buried regions close to the Semiconductor substrate the second surface, and with the second conduction type；

Deep-well region is formed on the top surface of the buried regions, the deep-well region has the first conduction type；

Drift region is formed on the top surface of the deep-well region, the drift region has the second conduction type.

13. a kind of electronic device, which is characterized in that the electronic device includes half as any one of claim 1 to 7 Conductor device.