CN108155187B - Switching power supply circuit, semiconductor power device and preparation method thereof - Google Patents

Abstract

The invention provides a switching power supply circuit, a semiconductor power device and a preparation method thereof, which include: a first MOS field effect transistor as a constant current source; a low-voltage power generation unit that generates an internal low-voltage power supply based on the constant current source; and a third unit that regulates the output current. two MOS field effect transistors; a third MOS field effect transistor that samples the output current; and a pulse width modulation unit that adjusts the second MOS field effect transistor based on the current sampling signal. The control module of the present invention has high integration, relatively simple process, and low manufacturing cost; the constant current source has high accuracy, the output current collection accuracy is high, and the overall accuracy is greatly improved; the semiconductor power device and the control module are integrated in a sealed manner. In a packaged tube, the process complexity and high cost caused by achieving the same function in a single chip are avoided.

Description

Switching power supply circuit, semiconductor power device and preparation method thereof

Technical field

The invention relates to the field of semiconductor manufacturing, and in particular to a switching power supply circuit, a semiconductor power device and a preparation method thereof.

Background technique

Figure 1 is a schematic structural diagram of an existing AC-DC switching power supply chip 1, in which an integrated circuit 11 is provided as a control circuit in one chip, and a power device 12 is provided in another chip, both of which are integrated in a package tube. in the shell.

As shown in Figure 1, the integrated circuit 11 includes a high-voltage constant current source 111, a control module 112 and a sampling resistor 113; the high-voltage constant current source 111 is connected to the high-voltage power supply VDD to provide a constant current for the control module 112; The control module 112 is connected to the sampling resistor 113 and the floating point VSS, and outputs a switch control signal to control the power MOS field effect transistor 121 in the discrete power device 12 . The power device 12 includes a power MOS field effect transistor 121. The drain end of the power MOS field effect transistor 121 is connected to the high-voltage power supply VDD, the gate end is connected to the output end of the control module 112, and the source end is connected to the sampling resistor 113.

Figure 2 shows a structure of a high-voltage constant current source 111 in the prior art. Although the gate terminal and the source terminal of the high-voltage constant current source 111 are connected to each other, the drain terminal and the source terminal of the high-voltage constant current source 111 can withstand high voltage. As shown in FIG. 3 , another structure of a high-voltage constant current source 111 in the prior art is shown. The gate terminal and the source terminal of the high-voltage loss device 1111 are bridged by a fixed value impedance 1112 . Although the drain end of 1111 is connected to a high voltage V+, the gate end is connected to the source end, or is bridged through a fixed value impedance 1112 and then connected to a low voltage V-. The high voltage V+ and the low voltage V- serve as two ends of the reference current source, and the characteristics of the high voltage constant current source 111 ensure the constant output current. The voltage Vgs between the gate terminal and the source terminal of the high-voltage constant current source 111 described in the prior art is 0. According to the circuit structure, the following relationship can be obtained:

Among them, K ₁₁₁₁ is a parameter related to the width-to-length ratio of the high-power loss 1111, which satisfies: I is the output current of the high-voltage constant current source 111, I _D1111 is the drain current of the high-voltage loss despite 1111, Vth is the threshold voltage of the high-voltage loss despite 1111, μ ₁₁₁₁ is the current carried in the channel of the high-voltage loss despite 1111 The average mobility of electrons, C _ox is the oxide layer capacitance of the gate terminal of the high-power loss device 1111, W ₁₁₁₁ is the channel width of the high-power loss device 1111, and L ₁₁₁₁ is the channel length of the high-power loss device 1111.

The existing technology has the following shortcomings and deficiencies:

First of all: just because of the existence of the high-voltage dissipation device 1111 in the integrated circuit 11, it is necessary to adopt a high-voltage semiconductor process in the entire preparation process, and to increase the mask level of the dissipation device threshold voltage adjustment injection; the components of the high-voltage process The integration level is low, the component area is large, the process is relatively complex, and the number of photomasks is large, resulting in high-voltage consumption just to manufacture the 1111, which increases the overall manufacturing cost of the chip and indirectly increases the production of AC-DC switching power supply chips. cost, thereby reducing the economic benefits of AC-DC switching power supply manufacturers.

Secondly: since the sampling resistor 113 and the impedance 1112 are both manufactured in the integrated circuit 11, and the impedance integrated on the chip is greatly affected by process fluctuations, the resistance value is difficult to be accurate, which leads to the failure of the high-voltage constant current source. The output current and sampling current are not accurate; in addition, although the threshold voltage Vth of the high-voltage constant current source 1111 will also fluctuate due to process fluctuations, the output current I of the high-voltage constant current source 111 is proportional to Vth ² . The above factors lead to poor overall batch consistency of AC-DC switching power supplies, reduce product accuracy, and increase the difficulty of product classification.

Therefore, how to simplify the process, improve the accuracy of the constant current source, and improve the sampling accuracy, thereby reducing the production cost of the AC-DC switching power supply, and improving the precision and accuracy of the AC-DC switching power supply have become one of the issues that technicians in the field need to solve urgently. one.

Contents of the invention

In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a switching power supply circuit, a semiconductor power device and a preparation method thereof to solve the problems of high production cost and low precision of AC-DC switching power supplies in the prior art. question.

In order to achieve the above objects and other related objects, the present invention provides a semiconductor power device, which at least includes:

A first MOS field effect transistor, a second MOS field effect transistor and a third MOS field effect transistor formed on the same semiconductor substrate;

The drain end of the first MOS field effect transistor is connected to the drain ends of the second MOS field effect transistor and the third MOS field effect transistor, and is drawn out as the drain end of the semiconductor power device; the first MOS The gate end of the field effect transistor is taken out as the first gate end of the semiconductor power device; the source end of the first MOS field effect transistor is connected to one end of the adjustable impedance, and the other end of the adjustable impedance is used as the semiconductor power device. The first source terminal of the device is led out;

The gate end of the second MOS field effect transistor is connected to the gate end of the third MOS field effect transistor, and is taken out as the second gate end of the semiconductor power device; the source end of the second MOS field effect transistor The source end of the third MOS field effect transistor is drawn out as the second source end of the semiconductor power device, and the source end of the third MOS field effect transistor is drawn out as the third source end of the semiconductor power device.

Preferably, the first MOS field effect transistor is a depletion mode MOS field effect transistor, and the second MOS field effect transistor and the third MOS field effect transistor are enhancement mode MOS field effect transistors.

Preferably, the adjustable impedance includes a plurality of parallel or series adjustment branches, each adjustment branch includes an impedance and an aluminum fuse or polysilicon fuse short-circuited with the impedance, and the aluminum fuse or polysilicon fuse is blown. The wire will be released with the corresponding impedance.

Preferably, the second MOS field effect transistor and the third MOS field effect transistor have the same cell structure, and the number of cells of the second MOS field effect transistor and the third MOS field effect transistor is The ratio is N:1, where N is a number greater than zero.

In order to achieve the above objects and other related objects, the present invention provides a switching power supply circuit, which at least includes:

The above-mentioned semiconductor power device, low-voltage power generation unit and pulse width modulation unit;

The drain terminal of the first MOS field effect transistor is connected to the power supply voltage, and the gate terminal is connected to the first source terminal of the semiconductor power device for providing a constant current source;

The low-voltage power generation unit is connected to the first source end of the semiconductor power device, and generates an internal low-voltage power supply based on the constant current source to power the pulse width modulation unit;

The drain end of the second MOS field effect transistor is connected to the power supply voltage, the source end is connected to ground, and the gate end is connected to the output end of the pulse width modulation unit. The switching signal output by the pulse width modulation unit is based on the switching signal flowing through the The size of the output current of the second MOS field effect transistor;

The drain end of the third MOS field effect transistor is connected to the drain end of the second MOS field effect transistor, the source end is connected to the pulse width modulation unit, and the gate end is connected to the output end of the pulse width modulation unit. Output current for sampling and output current sampling signal;

The pulse width modulation unit receives the internal low-voltage power supply and the current sampling signal, adjusts the pulse width of the switching signal based on the current sampling signal, and thereby adjusts the output current.

Preferably, the low-voltage power generation unit and the pulse width modulation unit are provided on the same semiconductor substrate as a control module.

More preferably, the semiconductor power device and the control module are integrated in a package package.

More preferably, the semiconductor power device is fixed on the base island of the first packaging frame through die-mounting adhesive or eutectic welding, and the control module is fixed on the base island of the second packaging frame through die-mounting adhesive or eutectic welding. , the semiconductor power device and the control module are electrically connected through package bonding wires.

Preferably, the adjustable impedance connected to the first MOS field effect transistor satisfies the following relationship:

Among them, K ₂₁₁₁ is a parameter related to the width-to-length ratio of the first MOS field effect transistor, which satisfies: Z is the impedance value of the adjustable impedance, V _th is the threshold voltage of the first MOS field effect transistor, I is the output current of the constant current source, and μ is the load in the channel of the first MOS field effect transistor. The average mobility of carriers, C _ox is the oxide layer capacitance at the gate end of the first MOS field effect transistor, W is the channel width of the first MOS field effect transistor, and L is the Channel length.

In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing the above-mentioned semiconductor power device. The method for manufacturing the semiconductor power device at least includes:

Step S11: Provide a substrate, and perform terminal implantation on the substrate to form a terminal region;

Step S12: Form a field oxide layer on the surface of the substrate surrounded by the terminal area to determine the position of the adjustable impedance;

Step S13: Perform body region implantation in the substrate surrounded by the terminal region to form a body region;

Step S14: Perform a depletion region threshold voltage adjustment implant in the substrate surrounded by the terminal region to form a depletion region between the two body regions;

Step S15: Form a gate terminal structure on the depletion region and on the substrate between two adjacent body regions; form a polysilicon layer on the surface of the field oxide layer to form the adjustable impedance;

Step S16: Form a source region in the body region below both sides of the gate terminal structure, and form a body contact region in the body region;

Step S17: Form source contacts and gate contacts on the upper layer of the structure obtained in step S16, and form drain contacts on the back surface of the substrate to form the semiconductor power device.

In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing the above-mentioned semiconductor power device. The method for manufacturing the semiconductor power device at least includes:

Step S21: Provide a substrate, and perform terminal implantation on the substrate to form a terminal region;

Step S22: Form a field oxide layer on the surface of the substrate surrounded by the terminal area to determine the position of the adjustable impedance;

Step S23: Etch to form a plurality of trenches in the substrate surrounded by the terminal area, and form a first gate terminal structure in each of the trenches;

Step S24: Perform body region implantation in the substrate surrounded by the terminal region to form a body region;

Step S25: Perform a depletion region threshold voltage adjustment implant in the substrate surrounded by the terminal region to form a depletion region between the two body regions;

Step S26: Form a second gate terminal structure on the depletion region; form a polysilicon layer on the surface of the field oxide layer to form the adjustable impedance;

Step S27: Form source regions in the body regions on both sides of the gate terminal structure, and form body contact regions in the body region;

Step S28: Form source contacts and gate contacts on the upper layer of the structure obtained in step S27, and form drain contacts on the back surface of the substrate to form the semiconductor power device.

As mentioned above, the switching power supply circuit, semiconductor power device and preparation method thereof of the present invention have the following beneficial effects:

1. Separate the high-voltage devices from the control circuit, and the devices in the control circuit can be prepared only through low-voltage semiconductor processes, without increasing the loss of the mask layer injected by the threshold voltage adjustment; the components of the low-voltage process are highly integrated, The component area is small, the process is relatively simple, and the manufacturing cost is low.

2. Use MOS field effect transistors for sampling and make them in power devices to avoid the problem of inaccurate resistance using sampling resistors, thereby improving the accuracy of the switching power supply circuit.

3. The constant current source has adjustable impedance, high output current accuracy, and ensures the consistency of the current and other related parameters of the power devices produced in batches.

4. The semiconductor power device and control module are integrated into a packaged tube using a sealing method to form an AC-DC switching power supply, which organically combines chips based on different processes to avoid the occurrence of a single chip realizing the same functional band. The resulting process complexity and high cost.

Description of the drawings

Figure 1 shows a schematic structural diagram of an AC-DC switching power supply chip in the prior art.

FIG. 2 shows a schematic structural diagram of a high-voltage constant current source in the prior art.

FIG. 3 shows another structural schematic diagram of a high-voltage constant current source in the prior art.

Figure 4 shows a schematic structural diagram of the switching power supply circuit of the present invention.

Figure 5 shows a schematic structural diagram of the semiconductor power device of the present invention.

FIG. 6 shows a schematic layout diagram of the semiconductor power device of the present invention.

FIG. 7 shows a schematic cross-sectional view of the semiconductor power device of the present invention.

FIG. 8 shows another schematic cross-sectional view of the semiconductor power device of the present invention.

Component label description

1 AC-DC switching power supply chip

11 integrated circuits

111 High voltage constant current source

1111 High consumption despite

1112 impedance

112 control module

113 sampling resistor

12 Power devices

121 Power MOS field effect transistor

2 Switching power supply circuit

21 Semiconductor power devices

211 constant current source

2111 The first MOS field effect transistor

2112 Adjustable impedance

212 Second MOS field effect tube

213 The third MOS field effect tube

214 substrate

214a epitaxial layer

214b metal layer

215 terminal area

216 field oxygen layer

217 depletion zone

218 gate oxide layer

218a first gate oxide layer

218b second gate oxide layer

219 polysilicon layer

219a First polysilicon layer

219b Second polysilicon layer

Steps S11～S17

Steps S21～S28

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 4 to Figure 8. It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. The drawings only show the components related to the present invention and do not follow the actual implementation of the component numbers, shapes and components. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

Embodiment 1

As shown in Figure 4, the present invention provides a switching power supply circuit 2. The switching power supply circuit 2 includes:

Semiconductor power device 21 and control module 22; the semiconductor power device 21 includes a constant current source 211, a second MOS field effect transistor 212 and a third MOS field effect transistor 213; the control module 22 includes a low-voltage power generation unit 221 and a pulse Width modulation unit 222.

As shown in FIG. 4 , the input terminal of the constant current source 211 is connected to the power supply voltage VDD, and the output terminal is connected to the low-voltage power generation unit 221 for providing a constant current source.

Specifically, as shown in Figure 5, in this embodiment, the constant current source 211 includes a first MOS field effect transistor 2111 and an adjustable impedance 2112. The drain end of the first MOS field effect transistor 2111 is connected to the The power supply voltage VDD and the source end are connected to one end of the adjustable impedance 2112, and the other end of the adjustable impedance 214 is connected to the gate end of the first MOS field effect transistor 2111. The first MOS field effect transistor 2111 is a depletion mode MOS field effect transistor. The adjustable impedance 2112 includes a plurality of parallel or series adjustment branches. Each adjustment branch includes an impedance and an aluminum fuse or polysilicon fuse short-circuited with the impedance. After the aluminum fuse or polysilicon fuse is blown, Will be released with the corresponding impedance, in this embodiment a polysilicon fuse is used.

More specifically, in this embodiment, the circuit structure can be obtained by the following relationship:

After derivation, it is concluded that:

Get: or/>

Since Z>0, and the _Vth of the depletion mode MOS field effect transistor is <0, the negative solution is discarded

Finally obtained: impedance value K ₂₁₁₁ is a parameter related to the width-to-length ratio of the first MOS field effect transistor, satisfying: />

Wherein, _Vgs is the gate-source voltage of the first MOS field effect transistor 2111, I is the output current ID of the constant current source 211, _D2111 is the drain current of the constant current source 211, and _Vth is the third The threshold voltage of a MOS field effect transistor 2111, Z is the impedance value of the adjustable impedance 2112, μ is the average mobility of carriers in the channel of the first MOS field effect transistor 2111, C _ox is the first The oxide layer capacitance at the gate end of the MOS field effect transistor 2111, W is the channel width of the first MOS field effect transistor 2111, and L is the channel length of the first MOS field effect transistor 2111. It can be seen that the output current I of the constant current source 211 is determined by V _th and Z at the same time. Therefore, when V _th fluctuates, the actual V _th of the manufactured chip is measured. When the constant current source current When the design target value is I, the impedance value Z is adjusted through the impedance adjustment circuit, so that Then I can be accurately equal to the design target value.

As shown in FIG. 4 , the low-voltage power generation unit 221 is connected to the gate terminal of the first MOS field effect transistor 2111 and generates internal low-voltage power Vin based on the constant current source 211 to power the pulse width modulation unit 222 .

Specifically, in this embodiment, the reference ground of the low-voltage power generation unit 221 is grounded VSS. Any circuit structure that can convert high voltage into low voltage is suitable for the low voltage power generation unit 221 of the present invention, and is not limited here.

As shown in Figure 4, the drain terminal of the second MOS field effect transistor 212 is connected to the power supply voltage VDD, the source terminal is connected to ground, and the gate terminal is connected to the output terminal of the pulse width modulation unit 222. Based on the pulse width modulation unit The switching signal output by 222 adjusts the size of the output current flowing through the second MOS field effect transistor 212 .

Specifically, the second MOS field effect transistor 212 is an enhancement mode MOS field effect transistor.

As shown in Figure 4, the drain end of the third MOS field effect transistor 213 is connected to the power supply voltage VDD, the source end is connected to the pulse width modulation unit 222, and the gate end is connected to the output end of the pulse width modulation unit 222. The output current is sampled and a current sampling signal is output.

Specifically, the third MOS field effect transistor 213 is an enhancement type MOS field effect transistor. The second MOS field effect transistor 212 and the third MOS field effect transistor 213 have the same cell structure, and the number of cells of the second MOS field effect transistor 212 and the third MOS field effect transistor 213 is The ratio is N:1, where N is a number greater than zero, and the size of N is determined by the sampling processing circuit in the control module 22 (set in the pulse width modulation unit 222), and is not limited here. .

As shown in FIG. 4 , the pulse width modulation unit 222 receives the internal low-voltage power supply Vin and the current sampling signal, adjusts the pulse width of the switching signal based on the current sampling signal, and thereby realizes the control of the output current. Adjustment (current limiting or constant current effect).

Specifically, any circuit structure that can realize pulse width modulation is suitable for the pulse width modulation unit 222 of the present invention, and is not limited here.

It should be noted that in this embodiment, the constant current source 211, the second MOS field effect transistor 212 and the third MOS field effect transistor 213 are formed on the same semiconductor substrate, and the low voltage power generation unit 221 and the The pulse width modulation unit 222 is formed on another semiconductor substrate to simplify the manufacturing process.

Specifically, the drain end of the first MOS field effect transistor 2111 is connected to the drain ends of the second MOS field effect transistor 212 and the third MOS field effect transistor 213 as the drain end of the semiconductor power device 21 D lead out. The gate terminal of the first MOS field effect transistor 2111 is taken out as the first gate terminal G1 of the semiconductor power device 21 . The source end of the first MOS field effect transistor 2111 is connected to one end of the adjustable impedance 2112, and the other end of the adjustable impedance 2112 is taken out as the first source end S1 of the semiconductor power device 21. The gate terminal of the second MOS field effect transistor 212 is connected to the gate terminal of the third MOS field effect transistor 213 and is taken out as the second gate terminal G2 of the semiconductor power device 21 . The source end of the second MOS field effect transistor 212 is used as the second source end S2 of the semiconductor power device 21 , and the source end of the third MOS field effect transistor 213 is used as the third source of the semiconductor power device 21 Terminal S3 leads out. Since the second MOS field effect transistor 212 itself needs to adopt a high-voltage process, it only needs to add one depletion depletion threshold voltage adjustment injection to be compatible with the first MOS field effect transistor 2111 (high-voltage depletion MOS field effect transistor). ), greatly saving costs.

As shown in FIG. 6 is a chip layout diagram of the semiconductor power device 21, S1 is the source end pad of the first MOS field effect transistor 2111, and S2 is the source end pad of the second MOS field effect transistor 212. , S3 is the source end pad of the third MOS field effect transistor 213, G1 is the gate end pad of the first MOS field effect transistor 2111, G2 is the second MOS field effect transistor 212 and the third MOS field effect transistor 2111. The gate terminal pad of the three MOS field effect transistors 213.

Specifically, the preparation process of the low-voltage power generation unit 221 and the pulse width modulation unit 222 does not require a high-voltage process, has high integration, small component area, relatively simple process, and can greatly reduce manufacturing costs.

It should be noted that in this embodiment, the semiconductor power device 21 and the control module 22 are integrated in a package package in a sealed manner.

Specifically, the semiconductor power device 21 is fixed on the base island of the first packaging frame through die-mounting adhesive or eutectic welding, and the control module 22 is fixed on the base island of the second packaging frame through die-mounting adhesive or eutectic welding. The semiconductor power device 21 and the control module 22 are electrically connected through package bonding wires. The external ports of the semiconductor power device 21 and the control module 22 are led out of the package shell through pins.

Embodiment 2

As shown in Figure 7, the present invention provides a method for manufacturing the semiconductor power device 2. The first MOS field effect transistor 2111, the second MOS field effect transistor 212 and the third MOS field effect transistor 213 They all use planar technology, and the impedance in the adjustable impedance 2112 uses polycrystalline resistors. Specific steps are as follows:

Step S21: Provide a substrate 214, and perform terminal implantation on the substrate 214 to form the terminal region 215.

Specifically, in this embodiment, the conductivity type of the substrate 214 is N-type doping, an epitaxial layer 214a is formed on the substrate 214, the conductivity type of the epitaxial layer 214a is N-type doping, and The doping concentration is less than the doping concentration of the substrate 214 . The surface of the epitaxial layer 214a is oxidized, and then terminal photolithography is performed. The terminal region 215 is formed through ion implantation. As shown in FIGS. 6 and 7 , the terminal region 215 is a ring-shaped structure.

Step S12: Form a field oxide layer 216 on the surface of the epitaxial layer 214a surrounded by the terminal region 215 to determine the position of the adjustable impedance 2112.

Specifically, as shown in FIG. 7 , in this embodiment, the field oxygen layer 216 includes multiple field oxygen structures, and each field oxygen structure is provided independently of each other. In practical applications, the entire field oxygen layer can be formed, and each impedance is formed on the same field oxygen layer.

Step S13: Perform body region implantation in the epitaxial layer 214a surrounded by the terminal region 215 to form a body region P-body.

Specifically, as shown in Figure 7, active area photolithography and body area photolithography are performed, and the body region P-body is formed through ion implantation. In this embodiment, the body region P-body adopts P-type doping. miscellaneous.

Step S14: Perform a depletion region threshold voltage adjustment implant in the epitaxial layer 214a surrounded by the terminal region 215 to form a depletion region 217 between the two body regions P-body.

Specifically, as shown in Figure 7, a depletion region threshold voltage adjustment injection is performed between the two body regions P-body to form a depletion region 217, thereby determining the position of the first MOS field effect transistor 2111. .

Step S15: Form a gate terminal structure on the depletion region 217 and on the epitaxial layer 214a between two adjacent body regions P-body; form a polysilicon layer 219 on the surface of the field oxide layer 216 to form The adjustable impedance 2112.

Specifically, a gate oxide layer 218 is formed on the surface of the depletion region 217 and the terminal region 215 between two adjacent body regions P-body, and on the gate oxide layer 218 and the field oxide A polysilicon layer 219 is formed on the surface of the layer 216 through deposition, photolithography and etching. The gate oxide layer 218 and the polysilicon layer 219 are sequentially stacked to form a gate terminal structure.

Step S16: Form a source region N+ in the body region P-body below both sides of the gate terminal structure, and form a body contact region P+ in the body region P-body.

Specifically, a source region N+ is formed in the body region P-body under both sides of the gate terminal structure through photolithography and N-type ion implantation, and the source region N+ is diffused to part of the gate oxide layer 218; by Contact hole photolithography and contact hole etching form contact holes; ion implantation is used to form a body contact region P+ in the body region P-body. In this embodiment, the doping concentration of the body contact region P+ is greater than the The doping concentration of the body region P-body.

Step S17: Form source contacts and gate contacts on the upper layer of the structure obtained in step S16, and form drain contacts on the back surface of the substrate 214 to form the semiconductor power device.

Specifically, metal deposition, metal photolithography, and metal etching are used to form source contacts and gate contacts, and a passivation layer is deposited between each contact terminal, and insulation barrier is achieved through passivation layer photolithography and passivation layer etching. ; And form a metal layer 214b on the back side of 214 to achieve drain contact.

Embodiment 3

As shown in Figure 8, the present invention provides a method for manufacturing the semiconductor power device 2. The first MOS field effect transistor 2111 adopts a planar process, the second MOS field effect transistor 212 and the third MOS field effect transistor 2112 adopt a planar process. The effect transistor 213 adopts a trench process, which can greatly reduce the area occupied by the second MOS field effect transistor 212 and the third MOS field effect transistor 213 and reduce the chip cost; the impedance in the adjustable impedance 2112 adopts a polycrystalline resistor. . Specific steps are as follows:

Step S21: Provide a substrate 214, and perform terminal implantation on the substrate 214 to form the terminal region 215.

Specifically, in this embodiment, the conductivity type of the substrate 214 is N-type doping, an epitaxial layer 214a is formed on the substrate 241, the conductivity type of the epitaxial layer 214a is N-type doping, and The doping concentration is less than the doping concentration of the substrate 214 . An oxidation treatment is performed on the surface of the epitaxial layer 214a, and then terminal photolithography is performed. The terminal region 215 is formed through ion implantation. As shown in FIG. 6 and FIG. 8, the terminal region 215 is a ring-shaped structure.

Step S22: Form a field oxide layer 216 on the surface of the epitaxial layer 214a surrounded by the terminal region 215 to determine the position of the adjustable impedance 2112.

Specifically, as shown in FIG. 8 , in this embodiment, the field oxygen layer 216 includes multiple field oxygen structures, and each field oxygen structure is provided independently of each other. In practical applications, the entire field oxygen layer can be formed, and each impedance is formed on the same field oxygen layer.

Step S23: Etch to form a plurality of trenches in the epitaxial layer 214a surrounded by the terminal region 215, and form a first gate terminal structure in each of the trenches.

Specifically, as shown in FIG. 8 , active area photolithography and trench photolithography are performed, the trench is etched, and the first gate oxide layer 218a and the first polysilicon are sequentially grown in the trench. Layer 219a, etching the first polysilicon layer 219a, and sequentially stacking the first gate oxide layer 218a and the first polysilicon layer 219a to form a first gate terminal structure.

Step S24: Perform body region implantation in the epitaxial layer 214a surrounded by the terminal region 215 to form a body region P-body.

Specifically, as shown in Figure 8, active region photolithography and body region photolithography are performed, and the body region P-body is formed through ion implantation. In this embodiment, the body region P-body adopts P-type doping. miscellaneous.

Step S25: Perform depletion region threshold voltage adjustment implantation in the epitaxial layer 214a surrounded by the terminal region 215 to form a depletion region 217 between the two body regions P-body.

Specifically, as shown in Figure 8, a depletion region threshold voltage adjustment injection is performed between the two body regions P-body to form a depletion region 217, thereby determining the position of the first MOS field effect transistor 2111. .

Step S26: Form a second gate terminal structure on the depletion region 217; form a second polysilicon layer 219b on the surface of the field oxide layer 216 to form the adjustable impedance 2112.

Specifically, a second gate oxide layer 218b is formed on the surface of the depletion region 217, and a third gate oxide layer 218b is formed on the surface of the second gate oxide layer 218b and the field oxide layer 216 through deposition, photolithography and etching. Two polysilicon layers 219b, the second gate oxide layer 218b and the second polysilicon layer 219b stacked in sequence form a second gate terminal structure.

Step S27: Form a source region N+ in the body region P-body below both sides of each gate terminal structure, and form a body contact region P+ in the body region P-body.

Specifically, the source region N+ is formed in the body region P-body below both sides of the gate terminal structure through photolithography and N-type ion implantation. The source region N+ is diffused to part of the gate oxide layer; through the contact hole Contact holes are formed by photolithography and contact hole etching; ion implantation is used to form a body contact region P+ in the body region P-body. In this embodiment, the doping concentration of the body contact region P+ is greater than that of the body region Doping concentration of P-body.

Step S28: Form source contacts and gate contacts on the upper layer of the structure obtained in step S27, and form drain contacts on the back surface of the substrate 214 to form the semiconductor power device.

Specifically, metal deposition, metal photolithography, and metal etching are used to form source contacts and gate contacts, and a passivation layer is deposited between each contact terminal, and insulation barrier is achieved through passivation layer photolithography and passivation layer etching. ; And form a metal layer 214b on the back side of 214 to achieve drain contact.

The switching power supply circuit, semiconductor power device and preparation method of the present invention separate the high-voltage device from the control circuit, and can prepare the device in the control circuit only through low-voltage semiconductor technology without increasing the consumption of light injected despite the threshold voltage adjustment. Cover level; low-voltage process components have high integration, small component area, relatively simple process, and low manufacturing cost. MOS field effect transistors are used for sampling and are manufactured in power devices to avoid the problem of inaccurate resistance values using sampling resistors, thereby improving the accuracy of the switching power supply circuit. The constant current source has adjustable impedance, high output current accuracy, and ensures the consistency of the current and other related parameters of the power devices produced in batches. The semiconductor power device and control module are integrated into a packaged tube using a sealing method to form an AC-DC switching power supply, so as to achieve the same functions and product appearance as the existing technology at the customer end.

To sum up, the present invention provides a switching power supply circuit, a semiconductor power device and a preparation method thereof, including: a first MOS field effect transistor as a constant current source; a low-voltage power generation unit that generates an internal low-voltage power supply based on the constant current source; a second MOS field effect transistor that regulates the output current; a third MOS field effect transistor that samples the output current; and a pulse width modulation unit that adjusts the second MOS field effect transistor based on the current sampling signal. The control module of the present invention adopts low-voltage process components, with high integration, small component area, relatively simple process, and low manufacturing cost; it uses MOS field effect tubes to collect output current and improves the accuracy of the switching power supply circuit; the constant current source has The impedance is adjustable, the output current is highly accurate, and the consistency of the current and other related parameters of the power devices produced in batches is ensured; the semiconductor power device and the control module are integrated into a package shell using a sealing method to form a AC-DC switching power supply organically combines chips based on different processes to avoid the process complexity and high cost caused by achieving the same function on a single chip. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (11)

1. A semiconductor power device, the semiconductor power device comprising at least:

the first MOS field effect transistor, the second MOS field effect transistor and the third MOS field effect transistor are formed on the same semiconductor substrate;

the drain end of the first MOS field effect transistor is connected with the drain ends of the second MOS field effect transistor and the third MOS field effect transistor and is led out as the drain end of the semiconductor power device; the gate end of the first MOS field effect transistor is led out as a first gate end of the semiconductor power device; the source end of the first MOS field effect transistor is connected with one end of an adjustable impedance, and the other end of the adjustable impedance is led out as a first source end of the semiconductor power device; wherein the first MOS field effect transistor and the adjustable impedance form a constant current source;

the gate end of the second MOS field effect transistor is connected with the gate end of the third MOS field effect transistor and is led out as a second gate end of the semiconductor power device; the source end of the second MOS field effect transistor is led out as a second source end of the semiconductor power device, and the source end of the third MOS field effect transistor is led out as a third source end of the semiconductor power device.

2. The semiconductor power device of claim 1, wherein: the first MOS field effect transistor is a depletion type MOS field effect transistor, and the second MOS field effect transistor and the third MOS field effect transistor are enhancement type MOS field effect transistors.

3. The semiconductor power device of claim 1, wherein: the adjustable impedance comprises a plurality of parallel or serial adjusting branches, each adjusting branch comprises an impedance and an aluminum fuse or a polysilicon fuse which is short-circuited with the impedance, and the corresponding impedance is released after the aluminum fuse or the polysilicon fuse is blown.

4. The semiconductor power device of claim 1, wherein: the second MOS field effect transistor and the third MOS field effect transistor have the same cell structure, and the ratio of the number of cells of the second MOS field effect transistor to the number of cells of the third MOS field effect transistor is N:1, wherein N is a number larger than zero.

5. A switching power supply circuit, characterized in that it comprises at least:

the semiconductor power device, the low voltage power generation unit, and the pulse width modulation unit according to any one of claims 1 to 4;

the drain end of the first MOS field effect transistor is connected with a power supply voltage, and the gate end of the first MOS field effect transistor is connected with the first source end of the semiconductor power device and is used for providing a constant current source;

the low-voltage power generation unit is connected with the first source end of the semiconductor power device, and generates an internal low-voltage power source based on the constant current source to supply power for the pulse width modulation unit;

the drain end of the second MOS field effect transistor is connected with the power supply voltage, the source end of the second MOS field effect transistor is grounded, the gate end of the second MOS field effect transistor is connected with the output end of the pulse width modulation unit, and the magnitude of the output current flowing through the second MOS field effect transistor is regulated based on the switching signal output by the pulse width modulation unit;

the drain end of the third MOS field effect transistor is connected with the drain end of the second MOS field effect transistor, the source end of the third MOS field effect transistor is connected with the pulse width modulation unit, the gate end of the third MOS field effect transistor is connected with the output end of the pulse width modulation unit, the output current is sampled, and a current sampling signal is output;

the pulse width modulation unit receives the internal low-voltage power supply and the current sampling signal, adjusts the pulse width of the switching signal based on the current sampling signal, and further adjusts the output current.

6. The switching power supply circuit according to claim 5, wherein: the low-voltage power generation unit and the pulse width modulation unit are arranged on the same semiconductor substrate as a control module.

7. The switching power supply circuit according to claim 6, wherein: the semiconductor power device and the control module are integrated in a packaging tube shell in a sealing mode.

8. The switching power supply circuit according to claim 7, wherein: the semiconductor power device is fixed on the first packaging frame base island in a chip mounting glue or eutectic welding mode, the control module is fixed on the second packaging frame base island in a chip mounting glue or eutectic welding mode, and the semiconductor power device is electrically connected with the control module through packaging welding wires.

9. The switching power supply circuit according to claim 5, wherein: the adjustable impedance of the first MOS field effect transistor connection meets the following relation:

wherein K is ₂₁₁₁ The parameters related to the width-to-length ratio of the first MOS field effect transistor are as follows:z is the impedance value of the adjustable impedance, V _th For the threshold voltage of the first MOS field effect transistor, I is the output current of the constant current source, mu is the average mobility of carriers in the channel of the first MOS field effect transistor, and C _ox And the oxide layer capacitor at the gate end of the first MOS field effect transistor is W, the channel width of the first MOS field effect transistor is W, and the channel length of the first MOS field effect transistor is L.

10. A method of manufacturing a semiconductor power device according to any one of claims 1 to 4, wherein the method of manufacturing a semiconductor power device comprises at least:

step S11: providing a substrate, and performing terminal implantation on the substrate to form a terminal region;

step S12: forming a field oxide layer on the surface of the substrate surrounded by the terminal area so as to determine the position of the adjustable impedance;

step S13: performing body region implantation in the substrate surrounded by the terminal region to form a body region;

step S14: performing depletion region threshold voltage adjustment injection in the substrate surrounded by the terminal region to form a depletion region between the two body regions;

step S15: forming a gate end structure on the depletion region and on the substrate between two adjacent body regions; forming a polysilicon layer on the surface of the field oxide layer to form the adjustable impedance;

step S16: forming a source region in a body region below two sides of the gate end structure, and forming a body contact region in the body region;

step S17: and forming a source contact and a gate contact on the upper layer of the structure obtained in the step S16, and forming a drain contact on the back surface of the substrate to form the semiconductor power device.

11. A method of manufacturing a semiconductor power device according to any one of claims 1 to 4, wherein the method of manufacturing a semiconductor power device comprises at least:

step S21: providing a substrate, and performing terminal implantation on the substrate to form a terminal region;

step S22: forming a field oxide layer on the surface of the substrate surrounded by the terminal area so as to determine the position of the adjustable impedance;

step S23: etching a substrate surrounded by the terminal area to form a plurality of grooves, and forming a first gate end structure in each groove;

step S24: performing body region implantation in the substrate surrounded by the terminal region to form a body region;

step S25: performing depletion region threshold voltage adjustment injection in the substrate surrounded by the terminal region to form a depletion region between the two body regions;

step S26: forming a second gate end structure on the depletion region; forming a polysilicon layer on the surface of the field oxide layer to form the adjustable impedance;

step S27: forming source regions in the body regions at two sides of each gate end structure, and forming body contact regions in the body regions;

step S28: and forming a source contact and a gate contact on the upper layer of the structure obtained in the step S27, and forming a drain contact on the back surface of the substrate to form the semiconductor power device.