CN108170021B - Electronic watch driving circuit and electronic watch - Google Patents
Electronic watch driving circuit and electronic watch Download PDFInfo
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- CN108170021B CN108170021B CN201810144694.4A CN201810144694A CN108170021B CN 108170021 B CN108170021 B CN 108170021B CN 201810144694 A CN201810144694 A CN 201810144694A CN 108170021 B CN108170021 B CN 108170021B
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Abstract
The invention belongs to the field of electronic watches, and discloses an electronic watch driving circuit and an electronic watch, wherein a negative pressure module is used for generating a negative constant voltage power supply according to the constant voltage power supply; the segment code selection module generates a segment code selection signal according to the negative constant voltage power supply and the first functional signal; the segment code assignment module generates a segment code display signal according to the negative constant voltage power supply and the second functional signal; the display module displays according to the segment code selection signal and the segment code display signal; the difference between the segment code selection signal and the segment code display signal is larger than the power supply value of the display module, so that the display driving capability is improved, namely the display effect and the reliability are improved, and the market competitiveness of the product is enhanced.
Description
Technical Field
The invention belongs to the field of electronic watches, and particularly relates to an electronic watch driving circuit and an electronic watch.
Background
In the current market, the battery voltage of an electronic watch generally drops after the electronic watch is used for a period of time, and a time field displayed on a liquid crystal screen also correspondingly lightens; when the backlight function of the electronic watch is turned on, key sounds or alarm clock sounds are turned on, the backlight and sound functions all require larger driving current, however, the driving capacity of the battery is limited, and the voltage of the battery is reduced to a certain extent due to the deficiency of the load capacity, so that the displayed time field is also diluted or turned on and turned off along with the sound functions, the use look and feel of the electronic watch is seriously affected, and poor user experience is brought to a customer. The non-ideal display effect is difficult to meet the requirements of customers on the watch screen, and simultaneously, the popularization and market popularization of the electronic watch are difficult.
The prior art has the problem of poor display effect and reliability due to limited display driving capability.
Disclosure of Invention
The invention provides an electronic watch driving circuit and an electronic watch, and aims to solve the problems of poor display effect and poor reliability of the existing electronic watch driving circuit.
The present invention is achieved by an electronic timepiece drive circuit including:
a constant voltage module for generating a constant voltage power supply according to the input direct current;
the negative pressure module is connected with the constant pressure module and used for generating a negative constant pressure power supply according to the constant pressure power supply;
the crystal oscillator module is connected with the constant voltage module and is used for generating an original pulse signal according to the constant voltage power supply;
the time reference module is connected with the crystal oscillator module and used for generating a reference pulse signal according to the original pulse signal;
the key module is connected with the time reference module and is used for generating a key trigger signal according to the reference pulse signal and a key instruction input by a user;
the functional module is connected with the key module and the time reference module and is used for generating a first functional signal and a second functional signal according to the reference pulse signal and the key trigger signal;
The segment code selection module is connected with the functional module and the negative pressure module and is used for generating a segment code selection signal according to the negative constant voltage power supply and the first functional signal;
the segment code assignment module is connected with the functional module and the negative pressure module and is used for generating a segment code display signal according to the negative constant voltage power supply and the second functional signal;
and the display module is connected with the segment code selection module and the segment code assignment module and used for displaying according to the segment code selection signal and the segment code display signal.
An electronic timepiece including the electronic timepiece driving circuit described above.
According to the embodiment of the invention, the negative constant voltage power supply is generated by the negative voltage module according to the constant voltage power supply; the segment code selection module generates a segment code selection signal according to the negative constant voltage power supply and the first functional signal; the segment code assignment module generates a segment code display signal according to the negative constant voltage power supply and the second functional signal; the display module displays according to the segment code selection signal and the segment code display signal; the difference between the segment code selection signal and the segment code display signal is larger than the power supply value of the display module, so that the display driving capability is improved, namely the display effect and the reliability are improved, and the market competitiveness of the product is enhanced.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a circuit configuration diagram of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 2 is a circuit structure diagram of a negative voltage module of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an exemplary circuit of a negative-pressure module of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an exemplary circuit of a set inverter circuit in a negative voltage module of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 5 is a circuit diagram of a section code selecting module of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 6 is a circuit diagram illustrating an example of a timing sequence generating circuit in a negative voltage module of an electronic watch driving circuit according to an embodiment of the present invention;
fig. 7 is a circuit diagram illustrating an example of a code assignment module of an electronic driving circuit according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 shows a block structure of an electronic timepiece driving circuit according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown in detail as follows:
the electronic timepiece driving circuit can be applied to various display driving circuits, and is particularly suitable for electronic watches.
The electronic timepiece driving circuit includes:
and a constant voltage module 01 for generating a constant voltage power supply from the input direct current.
And a negative pressure module 02 connected with the constant pressure module 01 and used for generating a negative constant pressure power supply according to the constant pressure power supply.
And the crystal oscillator module 03 is connected with the constant voltage module 01 and is used for generating an original pulse signal according to the constant voltage power supply.
And the time reference module 04 is connected with the crystal oscillator module 03 and is used for generating a reference pulse signal according to the original pulse signal.
And the key module 05 is connected with the time reference module 04 and is used for generating a key trigger signal according to the reference pulse signal and a key instruction input by a user.
And the function module 06 is connected with the key module 05 and the time reference module 04 and is used for generating a first function signal and a second function signal according to the reference pulse signal and the key trigger signal.
And a segment code selection module 07 connected with the functional module 06 and the negative pressure module 02 and used for generating a segment code selection signal according to the negative constant voltage power supply and the first functional signal.
And the segment code assignment module 08 is connected with the functional module 06 and the negative pressure module 02 and is used for generating a segment code display signal according to the negative constant voltage power supply and the second functional signal.
And the display module 09 is connected with the segment code selection module 07 and the segment code assignment module 08 and is used for displaying according to the segment code selection signal and the segment code display signal.
Generating a negative constant voltage power supply according to the constant voltage power supply through a negative voltage module 02; the segment code selection module 07 generates a segment code selection signal according to the negative constant voltage power supply and the first functional signal; the segment code assignment module 08 generates a segment code display signal according to the negative constant voltage power supply and the second functional signal; the display module 09 displays according to the segment code selection signal and the segment code display signal; the display driving voltage is the difference between the segment code selection signal and the segment code display signal, and the difference can be larger than the power supply value of the original display module 09, so that the display driving capability is obviously improved, namely the display effect and the reliability are improved, and the market competitiveness of the product is enhanced.
As shown in fig. 2, the negative pressure module 02 includes: a control signal generation module 021 for generating a negative pressure control signal; the boost module 022 is connected with the control signal generation module 021 and is used for generating a negative constant voltage power supply according to the constant voltage power supply and the negative pressure control signal.
Fig. 3 shows an example circuit structure of the electronic watch driving circuit negative voltage module 02 according to the embodiment of the present invention, and for convenience of explanation, only the portions related to the embodiment of the present invention are shown, and the details are as follows:
the control signal generating module 021 includes a first set inverter U1, a second set inverter U2, a first level converting module U3, a second level converting module U4, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a sixth NAND gate NAND6, a first inverter X1, a second inverter X2, a third inverter X3, a fourth inverter X4, a fifth inverter X5, a sixth inverter X6, a seventh inverter X7, an eighth inverter X8, a ninth inverter X9, a tenth inverter X10, an eleventh inverter X11, a twelfth inverter X12, a thirteenth inverter X13, a fourteenth inverter X14, and a fifteenth inverter X15.
The input end of the first inverter X1 is the first input end of the control signal generating module 021, the output end of the first inverter X1 is connected with the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 is connected with the output end of the second NAND gate NAND2, the second input end of the fifth NAND gate NAND5, the third input end of the sixth NAND gate NAND6 and the second end of the third NAND gate NAND2, the output end of the first NAND gate NAND1 is connected with the first input end of the second NAND gate NAND2, the second input end of the second NAND gate NAND2 is the second input end of the control signal generating module 021, the positive phase setting end A of the first setting inverter U1, the positive phase setting end A of the second setting inverter U2 and the input end of the fifth inverter X5 jointly form the third input end of the control signal generating module 021, the phase setting end B of the first setting inverter U1 is connected with the second input end of the second NAND gate NAND2, the second input end of the third inverter C3 and the third input end of the third NAND gate NAND2 is connected with the output end of the third NAND1, the second input end of the third inverter U3 and the third input end of the third NAND4 is connected with the third input end of the third NAND gate NAND2, the output end of the third inverter U1 is connected with the third input end of the third NAND4 NAND2, the output end of the third inverter C1 is connected with the third input end of the third NAND3 NAND2 is connected with the output end of the third input end of the third NAND3 NAND2, the output end of the third NAND2 is connected with the output end of the third input end of the third NAND2 is connected with the output end of the third NAND2, the output end Y of the second set inverter U1 is connected with the first input end of the fourth and NOT gate NAND4, the second input end of the third NAND gate NAND3 is the fifth input end of the control signal generating module 021, the output end of the sixth inverter X6 is connected with the third input end of the fifth NAND gate NAND5 and the first input end of the sixth NAND gate NAND6, the first input end of the fifth NAND gate NAND5 is the sixth input end of the control signal generating module 021, the output end of the fifth NAND gate NAND5 is connected with the input end of the seventh inverter X7, the output end of the seventh inverter X7 is connected with the second input end of the first level converting module U3, the output end of the eighth inverter X8 is connected with the first input end of the first level converting module U3, the output end of the level converting module U3 is connected with the first input end of the eleventh inverter X11, the output end of the eleventh inverter X11 is connected with the input end of the thirteenth inverter X13 and the sixth input end of the twelfth inverter X12, the output end of the thirteenth inverter X14 is connected with the output end of the ninth inverter X14, the output end of the ninth inverter X14 is connected with the output end of the ninth inverter X9, the output end of the thirteenth inverter X12 is connected with the output end of the thirteenth inverter X13, the output end of the thirteenth inverter X12 is connected with the output end of the thirteenth inverter X12, the output end of the thirteenth inverter X12 is connected with the output end of the ninth inverter X12, the output end of the eighth inverter X12 is connected with the eighth input end of the eighth inverter X12, the output end of the second level conversion module U4 is connected to the input end of the fifteenth inverter X15, and the output end of the fifteenth inverter X15 is the fourth output end of the control signal generating module 021.
The boosting module 022 includes a ninth fet M9, a tenth fet M10, an eleventh fet M11, a twelfth fet M12, a thirteenth fet M13, a fourteenth fet M14, a fifteenth fet M15, a sixteenth fet M16, a seventeenth fet M17, an eighteenth fet M18, a nineteenth fet M19, a twentieth fet M20, a twenty-first fet M21, a twenty-second fet M22, and a first capacitor C1.
The grid electrode of the ninth field effect tube M9, the grid electrode of the tenth field effect tube M10 and the grid electrode of the twenty-second field effect tube M22 jointly form a first control end of the boosting module 022, the grid electrode of the fourteenth field effect tube M14, the grid electrode of the sixteenth field effect tube M16, the grid electrode of the seventeenth field effect tube M17 and the grid electrode of the twenty-first field effect tube M21 jointly form a second control end of the boosting module 022, the grid electrode of the thirteenth field effect tube M13, the grid electrode of the fifteenth field effect tube M15, the grid electrode of the eighteenth field effect tube M18 and the grid electrode of the nineteenth field effect tube M19 jointly form a third control end of the boosting module 022, the grid electrodes of the eleventh field effect tube M11 and the twenty-second field effect tube M20 jointly form a fourth control end of the boosting module 022, the drain electrode of the ninth field effect tube M9 and the source electrode of the twenty-second field effect tube M21 are connected with the first power supply VDD, the source electrode of the ninth field effect tube M9 is connected with the grid electrode of the twelfth field effect tube M12 and the source of the tenth field effect tube M10, the drain electrode of the tenth FET M10 is connected with the first end of the first capacitor C1, the drain electrode of the eleventh FET M11, the source electrode of the twelfth FET M2 and the drain electrode of the thirteenth FET M13, the source electrode of the eleventh FET M11 and the source electrode of the twenty-first FET are the second power supply output end VSS2 of the boost module 022, the drain electrode of the twelfth FET M12, the source electrode of the fourteenth FET M14, the drain electrode of the fifteenth FET M15 and the drain electrode of the nineteenth FET M19 together form the first power supply output end VSS1 of the boost module 022, the source electrode of the thirteenth FET M13, the source electrode of the seventeenth FET M17, the source electrode of the sixteenth FET M16, the drain electrode of the eighteenth FET M18 and the source electrode of the twentieth FET M20 are commonly connected to the first power supply ground, the drain electrode of the fourteenth field effect transistor M14 is connected to the source electrode of the fifteenth field effect transistor M15 and the drain electrode of the sixteenth field effect transistor M16, the drain electrode of the seventeenth field effect transistor M17 is connected to the source electrode of the eighteenth field effect transistor M18 and the drain electrode of the twenty first field effect transistor M21, and the source electrode of the nineteenth field effect transistor M19 is connected to the second end of the first capacitor C1, the drain electrode of the twenty second field effect transistor M22 and the drain electrode of the twenty first field effect transistor M20.
The first set inverter U1 and the second set inverter U2 each include a set inverter circuit, which includes a thirty-third fet M33, a thirty-fourth fet M34, a thirty-fifth fet M35, a thirty-sixteen fet M36, and a thirty-seventh fet M37, as shown in fig. 4.
The source of the thirty-third field effect transistor M33 and the source of the thirty-fourth field effect transistor M34 together form a first power supply end of the set inverter, the gate of the thirty-fourth field effect transistor M33 is a positive phase set end A of the set inverter, the gate of the thirty-fourth field effect transistor M34 and the thirty-seventh field effect transistor M37 are opposite phase set ends B of the set inverter, the gate of the thirty-fifth field effect transistor M35 and the gate of the thirty-sixth field effect transistor M36 are data input ends C of the set inverter, the drain of the thirty-fifth field effect transistor M35, the drain of the thirty-fourth field effect transistor M34 and the source of the thirty-sixth field effect transistor M36 together form an output end of the set inverter, the drain of the thirty-third field effect transistor M33 is connected with the source of the thirty-fifth field effect transistor M35, the drain of the thirty-sixth field effect transistor M36 is connected with the source of the thirty-seventh field effect transistor M37, and the drain of the thirty-seventh field effect transistor M37 is connected with the second power supply GND.
The first level conversion module U3 and the second level conversion module U4 each include a level conversion circuit, as shown in fig. 3, where the level conversion circuit includes a first fet M1, a second fet M2, a third fet M3, and a fourth fet M4.
The grid electrode of the second field effect tube M2 is a first input end of the level conversion module, the grid electrode of the first field effect tube M1 is a second input end of the level conversion module, a source electrode of the first field effect tube M1 and a source electrode of the second field effect tube M2 jointly form a first power end of the level conversion module, a drain electrode of the first field effect tube M1 is connected with a drain electrode of the third field effect tube M3 and a grid electrode of the fourth field effect tube M4, a drain electrode of the second field effect tube M2 is connected with a drain electrode of the fourth field effect tube M4 and a grid electrode of the third field effect tube M3, and a source electrode of the third field effect tube M3 and a source electrode of the fourth field effect tube M4 jointly form a second power end of the level conversion module.
The following further describes the operation of the device shown in fig. 2, 3 and 4 in conjunction with the following principle:
in a specific implementation process, the frequency signal input from the second input end of the control signal generating module 021 to the sixth input end of the control signal generating module 021 is combined and level-converted by the RS flip-flop and the logic gate to obtain the control signal output from the first output end of the control signal generating module 021 to the fourth output end of the control signal generating module 021, and the first input end of the control signal generating module 021 provides an initial state for the part of the control circuit.
In the boosting module 022, the first step: n20_g is high and x48_y is low. M12 and M22 are open, CAP2 is connected to VDD, CAP1 is connected to VSS1, Δv=vdd-VSS 1; and a second step of: x34_y is high, M19 and M13 are on, where CAP2 is connected to VSS1 and CAP1 is connected to DGND, in order to generate a fixed level dgnd=vss 1- Δv=2vss 1-VDD; and a third step of: n20_g is high horizon, x48_y is low, M12 and M22 are on, CAP2 is connected to VDD, CAP1 is connected to VSS1, so that the voltage between CAP2 and CAP1 is kept at Δv; fourth, x35_y is high level, M11 and M20 are opened, CAP2 is connected to DGND, CAP1 is connected to VSS2, voltage between CAP2 and CAP1 is kept at Δv, VSS2 = DGND- Δv = 3VSS1-2vdd, VSS2 negative voltage level is generated, and stable negative voltage level can be obtained by repeating the above steps.
As shown in fig. 5, the segment code selection module 07 includes: a time sequence encoding module 071 connected with the functional module 06 and used for generating a time sequence encoding signal according to the first functional signal; a first timing generation module 072 connected to the timing encoding module 071 and the negative pressure module 02, for generating a first timing signal according to the negative constant voltage power supply and the timing encoding signal; a second timing generation module 073 connected to the timing encoding module 071 and the negative pressure module 02 for generating a second timing signal according to the negative constant voltage power supply and the timing encoding signal; a third timing generation module 074 connected to the timing encoding module 071 and the negative pressure module 02 for generating a third timing signal according to the negative constant voltage power supply and the timing encoding signal.
The first timing generation module 072, the second timing generation module 073, and the third timing generation module 074 each include a timing generation circuit, and as shown in fig. 6, the timing generation circuit includes a thirty-eighth fet M38, a thirty-ninth fet M39, a forty fet M40, a forty-eleven fet M41, a forty-two fet M42, a forty-third fet M43, a forty-four fet M44, and a forty-five fet M45.
The source of the thirty-eighth field effect transistor M38 is the first power supply terminal VDD of the timing generation module, the source of the forty-second field effect transistor M42 is the second power supply terminal VSS1 of the timing generation module, the source of the forty-first field effect transistor M41 is the third power supply terminal VSS2 of the timing generation module, the source of the forty-fifth field effect transistor M45 is the ground terminal of the timing generation module, the gates of the thirty-eighth field effect transistor M38 and the forty-fifth field effect transistor M45 are the first data input terminal A of the timing generation module, the gates of the forty-first field effect transistor M41 and the forty-second field effect transistor M42 are the second data input terminal B of the timing generation module, the gates of the thirty-ninth field effect transistor M39 and the fortieth field effect transistor M40 are the third data input terminal C of the timing generation module, the grid electrode of the forty-third field effect tube M43 and the grid electrode of the forty-fourth field effect tube M44 are the fourth data input end D of the time sequence generation module, the drain electrode of the thirty-eighth field effect tube M38 is connected with the source electrode of the thirty-ninth field effect tube M39, the drain electrode of the thirty-ninth field effect tube M39, the source electrode of the forty-third field effect tube M40, the drain electrode of the forty-third field effect tube M43 and the source electrode of the forty-fourth field effect tube M44 jointly form the output end of the time sequence generation module, the drain electrode of the forty-first field effect tube M40 is connected with the source electrode of the forty-first field effect tube M41, the drain electrode of the forty-third field effect tube M42 is connected with the source electrode of the forty-third field effect tube M43, and the drain electrode of the forty-fourth field effect tube is connected with the source electrode of the forty-fifth field effect tube M45.
The following further describes the operation of the device shown in fig. 5 and 6:
the timing encoding module 071 generates four sets of timing encoding signals according to the first functional signal, the first set of timing encoding signals is connected to the first data input terminal a of the first timing generation module 072 and the second data input terminal B of the first timing generation module 072, the second set of timing encoding signals is connected to the first data input terminal a of the second timing generation module 073 and the second data input terminal B of the second timing generation module 073, the third set of timing encoding signals is connected to the first data input terminal a of the third timing generation module 074 of the first timing generation module 072 and the second data input terminal B of the third timing generation module 074, and the third set of timing encoding signals is connected to the third data input terminals C to the fourth data input terminal D of the first to third timing generation modules 074.
Taking the first timing generation module 072 as an example, when the first data input terminal a of the first timing generation module 072 and the third data input terminal C of the first timing generation module 072 are VSS2, the thirty-eighth field effect transistor M38 and the thirty-ninth field effect transistor M39 are turned on, and the output of the first timing generation module 072 is VDD; when the first data input terminal a of the first timing generation module 072 and the fourth data input terminal D of the first timing generation module 072 are VDD, the forty-four field effect transistor M44 and the forty-five field effect transistor M45 are turned on, and the output of the first timing generation module 072 is DGND; when the second data input terminal B of the first timing generation module 072 and the third data input terminal C of the first timing generation module 072 are VDD, the forty field effect transistor M40 and the forty-first field effect transistor M41 are turned on, and the output of the first timing generation module 072 is VSS2; when the second data input terminal B of the first timing generation module 072 and the fourth data input terminal D of the first timing generation module 072 are VSS1, the fourth twelve field effect transistor M42 and the fourth thirteenth field effect transistor M43 are turned on, and the output of the first timing generation module 072 is VSS1; thus, one cycle of the output of the first timing generation block 072 is formed, and the second timing generation block 073 and the third timing generation block 074 are also on the same principle, and finally three-phase control signals are formed.
Fig. 7 shows an example circuit structure of the electronic watch driving circuit section code assignment module 08 according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, and the details are as follows:
the segment code assignment module 08 includes a first decoding module U5, a second decoding module U6, a third level conversion module U7, a first AND gate AND1, a first NOR gate NOR1, a second NOR gate NOR2, a sixteenth inverter X16, a seventeenth inverter X17, an eighteenth inverter X18, a twenty-seventh fet M27, a twenty-eighth fet M28, a twenty-ninth fet M29, a thirty-eighth fet M30, a thirty-eleventh fet M31, AND a thirty-second fet M32.
The first input end A1 of the first decoding module U5 is the first input end of the segment code assignment module 08, the second input end A3 of the first decoding module U5 is the second input end of the segment code assignment module 08, the third input end A3B of the first decoding module U5 is the third input end of the segment code assignment module 08, the fourth input end H0 of the first decoding module U5 is the fourth input end of the segment code assignment module 08, the first input end A0 of the second decoding module U6 is the fifth input end of the segment code assignment module 08, the second input end A1 of the second decoding module U6 is the sixth input end of the segment code assignment module 08, the third input end A2 of the second decoding module U6 is the seventh input end of the segment code assignment module 08, the fourth input end A2B of the second decoding module U6 is the eighth input end of the segment code assignment module 08, the fifth input end A4 of the second decoding module U6 is the ninth input end of the segment code assignment module 08, the sixth input A4B of the second decoder U6 is the tenth input of the segment code assignment module 08, the seventh input K1 of the second decoder U6 is the eleventh input of the segment code assignment module 08, the eighth input K2 of the second decoder U6 is the twelfth input of the segment code assignment module 08, the output of the first decoder U5 is connected to the output of the second decoder U6, the first input of the first AND gate AND1 AND the first input of the first NOR gate NOR1, the second input of the first AND gate AND1 AND the second input of the first NOR gate NOR1 together form the thirteenth input of the segment code assignment module 08, the output of the first AND gate AND1 is connected to the first input of the second NOR gate XOR2, the output of the first NOR gate NOR1 is connected to the second input of the second or NOR gate XOR2, the output end of the second nor gate XOR2 is connected with the first input end of the third level conversion module U7 and the input end of the sixteenth inverter X16, the output end of the sixteenth inverter X16 is connected with the second input end of the third level conversion module U7, the output end of the third level conversion module U7 is connected with the input end of the seventeenth inverter X17, the output end of the seventeenth inverter X17 is connected with the gate of the thirty-seventh field effect transistor M30 and the gate of the thirty-first field effect transistor M31, the input end of the eighteenth inverter X18, the gate of the twenty-seventh field effect transistor M27 and the gate of the twenty-eighth field effect transistor M28 form the fourteenth input end of the segment code assignment module 08, the source of the thirty-second field effect transistor M32 is the first power end of the segment code assignment module 08, the drain of the thirty-seventh field effect transistor M32 is connected with the source of the seventeenth inverter X17, the drain of the thirty-seventh field effect transistor M27 is connected with the source of the thirty-seventh field effect transistor M30, the drain of the thirty-seventh field effect transistor M27 is the drain of the thirty-seventh segment code assignment module M31 is connected with the drain of the thirty-eighth segment code assignment module M28, and the drain of the twenty-seventh field effect transistor M31 is connected with the drain of the thirty-seventh segment code assignment module M28 is the source of the thirty-seventh segment code assignment module M32 is connected with the source of the thirty-seventh segment field effect transistor M31.
As shown in fig. 7, the third level conversion module U7 includes a twenty-third fet M23, a twenty-fourth fet M24, a twenty-fifth fet M25, and a twenty-sixth fet M26.
The grid electrode of the twenty-fourth field effect tube M24 is a first input end of the third level conversion module, the grid electrode of the twenty-sixth field effect tube M26 is a second input end of the third level conversion module, the source electrode of the twenty-sixth field effect tube M26 and the source electrode of the twenty-fourth field effect tube M24 are first power supply ends of the level conversion module, the drain electrode of the twenty-sixth field effect tube M26 is connected with the drain electrode of the twenty-third field effect tube M23 and the grid electrode of the twenty-fifth field effect tube M25, the source electrode of the twenty-third field effect tube M23 and the source electrode of the twenty-fifth field effect tube M25 are second power supply ends of the level conversion module, and the drain electrode of the twenty-fourth field effect tube M24, the drain electrode of the twenty-fifth field effect tube M25 and the grid electrode of the twenty-third field effect tube M23 jointly form an output end of the third level conversion module.
The following further describes the operation principle shown in fig. 7:
in a specific implementation process, signals of the third input end A3B of the first decoding module U5, the fourth input end A2B of the second decoding module U6, and the sixth input end A4B of the second decoding module U6 are inverted outputs of signals of the second input end A3 of the first decoding module U5, the third input end A2 of the second decoding module U6, and the fifth input end A4 of the second decoding module U6, respectively. All the inputs of the first decoding module and all the inputs of the second decoding module are output data of the functional module 06. The signals of the third input end A3B of the first decoding module U5, the fourth input end A2B of the second decoding module U6 and the sixth input end A4B of the second decoding module U6 are three control signals with phase differences, and the signals output the segment code data decoded by the first decoding module and the second decoding module to the output ends of the first decoding module and the second decoding module in a time sharing manner, which correspond to the output of the segment code selecting module 07. In the figure, the SET signal is a signal, when a preset key is pressed, all display sections are coded into one, and the screen is displayed completely, so that the test is convenient.
X222_y is the control signal after level conversion. When X222_Y is VDD and X169_Y is VSS2, the thirty-first field effect transistor M31 and the twenty-ninth field effect transistor M29 are opened, and the output of the segment code assignment module 08 is VSS2; when X222_ Y, X169 _169_Y is VSS2, the second seventeenth field effect transistor M27 and the thirty-first field effect transistor M30 are turned on, and the output of the segment code assignment module 08 is VSS1; when X222_ Y, X169 _169_Y is VDD, the thirty-first field effect transistor M31 and the twenty-second field effect transistor M28 are opened, and the output of the segment code assignment module 08 is DGND; when X222_Y is VSS2 and X169_Y is VDD, the third twelfth field effect transistor M32 and the thirty-first field effect transistor M30 are turned on, and the output of the segment code assignment module 08 is VDD; the output of the segment code assignment module 08 will vary with the control signal.
When the liquid crystal screen is correspondingly Duan Madian bright, the voltage difference between the output of the segment code selection module 07 and the output of the segment code assignment module 08 is 3VDD-3VSS1, and is generally 4.5V; when the corresponding segment code of the liquid crystal screen is not lighted, the voltage difference between the output of the segment code selecting module 07 and the output of the segment code assigning module 08 is VSS1, which is generally 1.5V. When the battery is used for a long time, the battery voltage is reduced, the voltage difference between the segment code and the public terminal (namely the difference between the segment code selection signal and the segment code display signal) is always maintained to be 3V larger than the display threshold voltage of the watch liquid crystal screen, the brightness of the watch liquid crystal screen is unchanged, and the constant voltage function is realized.
An electronic timepiece including the electronic timepiece driving circuit as described above.
According to the embodiment of the invention, the negative constant voltage power supply is generated by the negative voltage module according to the constant voltage power supply; the segment code selection module generates a segment code selection signal according to the negative constant voltage power supply and the first functional signal; the segment code assignment module generates a segment code display signal according to the negative constant voltage power supply and the second functional signal; the display module displays according to the segment code selection signal and the segment code display signal; the difference between the segment code selection signal and the segment code display signal is larger than the power supply value of the display module, so that the display driving capability is improved, namely the display effect and the reliability are improved, and the market competitiveness of the product is enhanced.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (7)
1. An electronic timepiece drive circuit, characterized by comprising:
a constant voltage module for generating a constant voltage power supply according to the input direct current;
the negative pressure module is connected with the constant pressure module and used for generating a negative constant pressure power supply according to the constant pressure power supply;
The crystal oscillator module is connected with the constant voltage module and is used for generating an original pulse signal according to the constant voltage power supply;
the time reference module is connected with the crystal oscillator module and used for generating a reference pulse signal according to the original pulse signal;
the key module is connected with the time reference module and is used for generating a key trigger signal according to the reference pulse signal and a key instruction input by a user;
the functional module is connected with the key module and the time reference module and is used for generating a first functional signal and a second functional signal according to the reference pulse signal and the key trigger signal;
the segment code selection module is connected with the functional module and the negative pressure module and is used for generating a segment code selection signal according to the negative constant voltage power supply and the first functional signal;
the segment code assignment module is connected with the functional module and the negative pressure module and is used for generating a segment code display signal according to the negative constant voltage power supply and the second functional signal;
the display module is connected with the segment code selection module and the segment code assignment module and used for displaying according to the segment code selection signal and the segment code display signal;
wherein, the display driving voltage is the difference value of the segment code selection signal and the segment code display signal;
The segment code selection module comprises:
the time sequence coding module is connected with the functional module and used for generating a time sequence coding signal according to the first functional signal;
the first time sequence generation module is connected with the time sequence coding module and the negative pressure module and is used for generating a first time sequence signal according to the negative constant voltage power supply and the time sequence coding signal;
the second time sequence generation module is connected with the time sequence coding module and the negative voltage module and is used for generating a second time sequence signal according to the negative constant voltage power supply and the time sequence coding signal;
the third time sequence generation module is connected with the time sequence coding module and the negative voltage module and is used for generating a third time sequence signal according to the negative constant voltage power supply and the time sequence coding signal;
the first time sequence generating module, the second time sequence generating module and the third time sequence generating module all comprise time sequence generating circuits, wherein the time sequence generating circuits comprise a thirty-eighth field effect transistor, a thirty-ninth field effect transistor, a forty-first field effect transistor, a forty-second field effect transistor, a forty-third field effect transistor, a forty-fourth field effect transistor and a forty-fifth field effect transistor;
The source of the thirty-eighth field effect transistor is the first power end of the time sequence generating module, the source of the forty-second field effect transistor is the second power end of the time sequence generating module, the source of the forty-first field effect transistor is the third power end of the time sequence generating module, the source of the forty-fifth field effect transistor is the grounding end of the time sequence generating module, the grid electrode of the thirty-eighth field effect transistor and the grid electrode of the forty-fifth field effect transistor are the first data input end of the time sequence generating module, the grid electrode of the forty-first field effect transistor and the grid electrode of the forty-second field effect transistor are the second data input end of the time sequence generating module, the grid electrode of the thirty-ninth field effect transistor and the grid electrode of the forty-fifth field effect transistor are the third data input end of the time sequence generating module, the gate of the forty-third field effect transistor and the gate of the forty-fourth field effect transistor are the fourth data input end of the time sequence generating module, the drain of the thirty-eighth field effect transistor is connected with the source of the thirty-ninth field effect transistor, the drain of the thirty-ninth field effect transistor, the source of the forty-third field effect transistor, the drain of the forty-third field effect transistor and the source of the forty-fourth field effect transistor jointly form the output end of the time sequence generating module, the drain of the forty-first field effect transistor is connected with the source of the forty-second field effect transistor, the drain of the forty-second field effect transistor is connected with the source of the forty-third field effect transistor, and the drain of the forty-fourth field effect transistor is connected with the source of the forty-fifth field effect transistor.
The segment code assignment module comprises a first decoding module, a second decoding module, a third level conversion module, a first AND gate, a first NOR gate, a second NOR gate, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, a twenty-ninth field effect transistor, a thirty-first field effect transistor and a thirty-second field effect transistor;
the first input end of the first decoding module is the first input end of the segment code assignment module, the second input end of the first decoding module is the second input end of the segment code assignment module, the third input end of the first decoding module is the third input end of the segment code assignment module, the fourth input end of the first decoding module is the fourth input end of the segment code assignment module, the first input end of the second decoding module is the fifth input end of the segment code assignment module, the second input end of the second decoding module is the sixth input end of the segment code assignment module, the third input end of the second decoding module is the seventh input end of the segment code assignment module, the fourth input end of the second decoding module is the eighth input end of the segment code assignment module, the fifth input end of the second decoding module is the ninth input end of the segment code assignment module, the sixth input end of the second decoding module is the tenth input end of the segment code assignment module, the seventh input end of the second decoding module is the eleventh input end of the segment code assignment module, the eighth input end of the second decoding module is the twelfth input end of the segment code assignment module, the output end of the first decoding module is connected with the output end of the second decoding module, the first input end of the first and gate and the first input end of the first nor gate, the second input end of the first and gate and the second input end of the first nor gate jointly form the thirteenth input end of the segment code assignment module, the output end of the first and gate is connected with the first input end of the second nor gate, the output end of the first nor gate is connected with the second input end of the second nor gate, the output end of the second NOR gate is connected with the first input end of the third level conversion module and the input end of the sixteenth inverter, the output end of the sixteenth inverter is connected with the second input end of the third level conversion module, the output end of the third level conversion module is connected with the input end of the seventeenth inverter, the output end of the seventeenth inverter is connected with the grid electrode of the thirty-seventh field effect transistor and the grid electrode of the third eleventh field effect transistor, the input end of the eighteenth inverter, the grid electrode of the second seventeenth field effect transistor and the grid electrode of the second eighteenth field effect transistor jointly form a fourteenth input end of the segment code assignment module, the source electrode of the thirty-second field effect transistor is a first power supply end of the segment code assignment module, the drain electrode of the thirty-second field effect transistor is connected with the source electrode of the twenty-seventh field effect transistor and the source electrode of the thirty-seventh field effect transistor, the drain electrode of the thirty-seventh field effect transistor is connected with the drain electrode of the thirty-eighth field effect transistor and the drain electrode of the thirty-eighth field effect transistor is connected with the drain electrode of the thirty-eighth field effect transistor.
2. The electronic timepiece drive circuit as claimed in claim 1, wherein said negative pressure module includes:
a control signal generation module for generating a negative pressure control signal;
and the boosting module is connected with the control signal generating module and used for generating a negative constant voltage power supply according to the constant voltage power supply and the negative pressure control signal.
3. The electronic timepiece driving circuit as claimed in claim 2, wherein said control signal generating means includes a first set inverter, a second set inverter, a first level converting means, a second level converting means, a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a fifth nand gate, a sixth nand gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, and a fifteenth inverter;
the input end of the first inverter is the first input end of the control signal generating module, the output end of the first inverter is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with the output end of the second NAND gate, the second input end of the fifth NAND gate, the third input end of the sixth NAND gate and the second end of the third NAND gate, the output end of the first NAND gate is connected with the first input end of the second NAND gate, the second input end of the second NAND gate is the second input end of the control signal generating module, the positive phase setting end of the first setting inverter, the positive phase setting end of the second setting inverter, the input end of the second inverter and the input end of the fifth inverter jointly form the third input end of the control signal generating module, the inverting setting end of the first setting inverter is connected with the output end of the second inverter, the output end of the second inverter is connected with the third input end of the third NAND gate, the second input end of the second NAND gate is connected with the third input end of the fourth setting inverter, the second input end of the third setting inverter is connected with the third input end of the fifth setting inverter, the third setting inverter is connected with the output end of the third setting inverter is connected with the third input end of the fifth setting inverter, the output end of the second set inverter is connected with the first input end of the fourth NAND gate, the second input end of the third NAND gate is a fifth input end of the control signal generating module, the output end of the sixth inverter is connected with the third input end of the fifth NAND gate and the first input end of the sixth NAND gate, the first input end of the fifth NAND gate is a sixth input end of the control signal generating module, the output end of the fifth NAND gate is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the input end of the eighth inverter and the second input end of the first level converting module, the output end of the eighth inverter is connected with the first input end of the first level converting module, the output end of the level converting module is connected with the input end of the eleventh inverter, the output end of the eleventh inverter is connected with the input end of the thirteenth inverter and the input end of the twelfth inverter, the output end of the thirteenth inverter is connected with the input end of the fourteenth inverter, the output end of the fourteenth inverter is the second output end of the control signal generating module, the output end of the twelfth inverter is the third output end of the control signal generating module, the second input end of the sixth NAND gate is the seventh input end of the control signal generating module, the output end of the sixth NAND gate is connected with the input end of the ninth inverter, the output end of the ninth inverter is connected with the first input end of the second level converting module and the input end of the tenth inverter, the output end of the tenth inverter is connected with the second input end of the second level converting module, the output end of the second level conversion module is connected with the input end of the fifteenth inverter, and the output end of the fifteenth inverter is a fourth output end of the control signal generation module.
4. The electronic timepiece drive circuit as claimed in claim 3 wherein said first and second set inverters each include a set inverter circuit including a thirty-third field effect transistor, a thirty-fourth field effect transistor, a thirty-fifth field effect transistor, a thirty-sixteen field effect transistor, and a thirty-seventeenth field effect transistor;
the source electrode of the thirty-third field effect tube and the source electrode of the thirty-fourth field effect tube jointly form a first power end of the set inverter, the gate electrode of the thirty-third field effect tube is a positive phase set end of the set inverter, the gate electrode of the thirty-fourth field effect tube and the thirty-seventh field effect tube are opposite phase set ends of the set inverter, the gate electrode of the thirty-fifth field effect tube and the gate electrode of the thirty-sixth field effect tube are data input ends of the set inverter, the drain electrode of the thirty-fifth field effect tube, the drain electrode of the thirty-fourth field effect tube and the source electrode of the thirty-sixth field effect tube jointly form an output end of the set inverter, the drain electrode of the thirty-third field effect tube is connected with the source electrode of the thirty-fifth field effect tube, the drain electrode of the thirty-sixth field effect tube is connected with the source electrode of the thirty-seventh field effect tube, and the drain electrode of the thirty-seventh field effect tube is connected with a second power ground.
5. The electronic timepiece drive circuit as claimed in claim 3, wherein said first level shift module and said second level shift module each include a level shift circuit including a first field effect transistor, a second field effect transistor, a third field effect transistor, and a fourth field effect transistor;
the grid of the second field effect tube is a first input end of the level conversion module, the grid of the first field effect tube is a second input end of the level conversion module, a source electrode of the first field effect tube and a source electrode of the second field effect tube jointly form a first power end of the level conversion module, a drain electrode of the first field effect tube is connected with a drain electrode of the third field effect tube and a grid electrode of the fourth field effect tube, a drain electrode of the second field effect tube is connected with a drain electrode of the fourth field effect tube and a grid electrode of the third field effect tube, and a source electrode of the third field effect tube and a source electrode of the fourth field effect tube jointly form a second power end of the level conversion module.
6. The electronic watch driving circuit of any one of claims 2 to 5, wherein the boost module includes a ninth fet, a tenth fet, an eleventh fet, a twelfth fet, a thirteenth fet, a fourteenth fet, a fifteenth fet, a sixteenth fet, a seventeenth fet, an eighteenth fet, a nineteenth fet, a twentieth fet, a twenty-first fet, a twenty-second fet, and a first capacitor;
The gate of the ninth field-effect transistor, the gate of the tenth field-effect transistor and the gate of the twelfth field-effect transistor together form a first control end of the boost module, the gate of the fourteenth field-effect transistor, the gate of the seventeenth field-effect transistor and the gate of the eleventh field-effect transistor together form a second control end of the boost module, the gate of the thirteenth field-effect transistor, the gate of the fifteenth field-effect transistor, the gate of the eighteenth field-effect transistor and the gate of the nineteenth field-effect transistor together form a third control end of the boost module, the gates of the eleventh field-effect transistor and the twenty-first field-effect transistor together form a fourth control end of the boost module, the drain of the ninth field-effect transistor and the source of the twenty-second field-effect transistor are connected with a first power supply, the source of the ninth field-effect transistor is connected with the gate of the thirteenth field-effect transistor and the source of the tenth field-effect transistor, the gates of the thirteenth field-effect transistor, the gates of the eighteenth field-effect transistor, the eighteenth field-effect transistor and the drain of the nineteenth field-effect transistor together form a third control end of the boost module, the drain of the eleventh field-effect transistor and the thirteenth field-effect transistor, the source of the thirteenth field-effect transistor and the twenty-source of the twenty-eighth field-effect transistor together form a fourth control end of the boost module, the source of the eleventh field-effect transistor and the source of the thirteenth field-effect transistor, the source of the thirteenth field-effect transistor and the thirteenth source of the thirteenth field-effect transistor and the source of the thirteenth source, the drain electrode of the eighteenth field effect tube and the source electrode of the twentieth field effect tube are commonly connected to a first power supply ground, the drain electrode of the fourteenth field effect tube is connected with the source electrode of the fifteenth field effect tube and the drain electrode of the sixteenth field effect tube, the drain electrode of the seventeenth field effect tube is connected with the source electrode of the eighteenth field effect tube and the drain electrode of the twenty first field effect tube, and the source electrode of the nineteenth field effect tube is connected with the second end of the first capacitor, the drain electrode of the twenty second field effect tube and the drain electrode of the twentieth field effect tube.
7. An electronic timepiece comprising an electronic timepiece drive circuit according to any one of claims 1 to 6.
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