CN108170634B - A kind of isomerous multi-source data reconstruction transient state reliable treatments method - Google Patents

Abstract

The invention discloses a reliable transient processing method for heterogeneous multi-source data reconstruction, including: FPGA dynamic area state judgment; Send an inquiry frame to the static area, which includes the coordinates of the dynamic area in the physical area of the FPGA chip and the function ID of the reconfigured code running on the dynamic area; the FPGA static area parses the inquiry frame sent by the dynamic area and returns Response frame, which includes the data cached in the BRAM at the moment of reconstruction. The method disclosed by the invention can solve the problem of interruption of data interaction between the dynamic area and the static area during the reconstruction of the dynamic area caused by the failure of the FPGA dynamic area or function switching, and improve the reliability of heterogeneous multi-source data processing .

Description

A Transient and Reliable Processing Method for Heterogeneous Multi-source Data Reconstruction

technical field

The invention belongs to the fields of electronic engineering and computer science, and in particular relates to a transient reliable processing method for heterogeneous multi-source data reconstruction.

Background technique

With the proposal of the national strategy "Made in China 2025", intelligent manufacturing has become a hot term in contemporary China. However, the realization of intelligent manufacturing is inseparable from data. These data are more specifically expressed as data on the manufacturing site. Therefore, the reliable collection, processing, exchange and transmission of manufacturing site data is the underlying technical support for the realization of intelligent manufacturing. The data at the manufacturing site is heterogeneous in terms of data protocol and multi-source in terms of data volume. How to efficiently process heterogeneous multi-source data while ensuring the reliability of data processing is very important. Due to the inherent hardware parallelism and dynamic reconfiguration characteristics of FPGA, a static area and multiple dynamic areas are built inside the FPGA. The static area completes the data collection, such as collecting the voltage, current, and speed of the machine tool, collecting real-time image data of the production line, and Environmental parameters, etc.; each dynamic area runs different processing algorithms, such as the voltage filter processing algorithm in dynamic area 1, the image grayscale processing algorithm in dynamic area 2, and the preprocessing algorithm for environmental parameters in dynamic area 3, etc., so that different Efficient processing of structured multi-source data.

However, there is a certain amount of radiation and ionization in the manufacturing site, and micro-processing chips including FPGAs are likely to have hardware damage and code "runaway" failures, but FPGAs can improve the reliability of data processing through dynamic reconfiguration. The performance is that when the code running on a certain dynamic area "runs away", the static area of the FPGA reads the dynamic code stored in the off-chip flash through the state machine, and reloads it into the faulty dynamic area to realize dynamic The fault self-recovery of the area; or the FPGA static area reads another dynamic code and loads it into the dynamic area to realize the function switching of the dynamic area. However, during the reconstruction process of the dynamic area, the data interaction between the static area and the dynamic area is interrupted. Even though the FPGA dynamic reconstruction time is generally at the millisecond level, for data processing occasions with strict real-time requirements, The interruption of data processing caused by reconstruction also directly affects the reliability of data processing. Therefore, the present invention proposes a reliable transient processing method for heterogeneous multi-source data reconstruction, which can solve the problem of interruption of data interaction between the static area and the dynamic area when the FPGA is dynamically reconfigured, and can realize heterogeneous multi-source Reliable processing of data.

Contents of the invention

The technical problem to be solved by the present invention is to provide a reliable transient processing method for heterogeneous multi-source data reconstruction, which can solve the problem of interruption of data interaction between the static area and the dynamic area during FPGA dynamic reconstruction, and can Realize reliable processing of heterogeneous multi-source data.

The present invention solves the technical problem by adopting the following technical solutions: a transient and reliable processing method for heterogeneous multi-source data reconstruction, comprising the following steps:

Step 1: Judging the status of the FPGA dynamic area, the specific implementation is as follows:

① Establish a dual-port BRAM with a width of 1 and a depth of 1. Driven by the main clock of the FPGA, the static area sets the value of the BRAM to a high level through port A. After 10 main clock cycles, the static area passes Port A reads and judges the level state of the value of the BRAM: when it is high, it indicates that the dynamic area is in the process of reconstruction; when it is low, it indicates that the dynamic area is in the process of non-reconstruction;

②The dynamic area reads and judges the level state of the value of the BRAM through port B in real time under the drive of the FPGA main clock. When it is high, the level state of the value of the BRAM is reset to low in the next clock cycle. flat;

③When there are k dynamic areas, k dual-port BRAMs with a width of 1 and a depth of 1 need to be established in the static area, and the status of each dynamic area is judged as ① and ②;

Step 2: Establish a data cache BRAM in the static area of the FPGA to cache the reconstructed transient data. The specific implementation is as follows:

① A BRAM is established in the static area of the FPGA. When the static area detects that the dynamic area is in the process of being reconstructed, the static area caches the data to be processed in this BRAM;

②The FPGA static area caches data in different offset addresses of the BRAM according to the coordinates of each dynamic area in the physical area of the FPGA chip and the function ID of the reconfigured code running on the dynamic area;

Step 3: After the reconstruction is completed, the FPGA dynamic area sends an inquiry frame to the static area. The specific implementation of the frame format is as follows:

①Byte 0-1 is the frame header, that is, hexadecimal 5A, 54;

②Byte 2-11 is the data area, where byte 2-3 indicates the abscissa of the upper left vertex of the dynamic area in the physical area inside the FPGA chip; byte 4-5 indicates that the dynamic area is in the upper left of the physical area inside the FPGA chip The ordinate of the vertex; bytes 6-7 indicate the abscissa of the dynamic area in the lower right vertex of the internal physical area of the FPGA chip; bytes 8-9 indicate the ordinate of the dynamic area in the lower right vertex of the internal physical area of the FPGA chip ;Bytes 10-11 represent the function ID of the refactored code running on this dynamic area;

③Byte 12 is the end identifier of the data area, that is, hexadecimal 00;

④Byte 13 is the checksum, that is, the logical sum of each byte in the data area takes the low byte;

⑤Byte 14-15 is the length of the data area, and byte 14 is the high byte;

⑥Byte 16-17 is the end of the frame, that is, hexadecimal 5A, FE;

When the frame end appears in the data area in the query frame, that is, hexadecimal 5A, FE, the escape character hexadecimal 00 needs to be inserted before the 5A, FE; the length of the data area does not include the inserted escape character;

Step 4: The FPGA static area parses the query frame sent by the dynamic area. When parsing the query frame, the inserted escape characters need to be removed to obtain the coordinates of the dynamic area in the physical area inside the FPGA chip and the reconstruction running on the dynamic area. The function ID of the code, and then the static area reads the corresponding data in the data cache BRAM;

Step 5: The FPGA static area returns a response frame to the dynamic area, and the frame format is specifically implemented as follows:

①Byte 0-1 is the frame header, that is, hexadecimal 5A, 54;

②Byte 2-(n+1) is the data area, that is, the data cached in the BRAM during reconstruction, where n is the data byte length;

③Byte n+2 is the end identifier of the data area, that is, hexadecimal 00;

④Byte n+3 is the checksum, that is, the logical sum of each byte in the data area takes the low byte;

⑤Byte n+4, n+5 are the length of the data area, wherein byte n+4 is the high byte;;

⑥Bytes n+6, n+7 are the end of the frame, that is, hexadecimal 5A, FE;

When the end of the frame appears in the data area of the response frame, that is, hexadecimal 5A, FE, the escape character hexadecimal 00 needs to be inserted before the 5A, FE; the length of the data area does not include the inserted escape character.

A heterogeneous and multi-source data reconstruction transient reliable processing method designed by the invention is suitable for Virtex-5FPGA chip of Xilinx company.

The advantage of the present invention compared with prior art is:

(1) The traditional method of using three-mode redundancy to improve the reliability of FPGA dynamic reconfiguration not only increases the consumption of FPGA resources, but also only improves the reliability of the dynamic area through multiple backups, and does not solve the problem of reconfiguration at all. Transient problem of construction time. The invention can solve the problem that the data interaction between the static area and the dynamic area is interrupted when the FPGA is dynamically reconfigured, and can realize reliable processing of heterogeneous multi-source data.

(2) The state judgment of the FPGA dynamic area proposed by the present invention, the establishment of BRAM to cache data during reconstruction, and the query frame and response frame between the static area and the dynamic area can fundamentally solve the transient problem of FPGA reconstruction.

Description of drawings

Fig. 1 is a flowchart of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings.

The invention relates to a transient reliable processing method for heterogeneous multi-source data reconstruction, which adopts Virtex-5FPGA chip of Xilinx company. This method aims at the reconstruction transient problem in heterogeneous multi-source data processing based on FPGA dynamic reconstruction. The so-called FPGA reconstruction transient problem means that the data interaction between the static area and the dynamic area is interrupted during FPGA dynamic reconstruction. The method proposed by the invention can solve the transient problem of FPGA reconstruction and realize reliable processing of heterogeneous multi-source data.

Flow chart of the present invention is as shown in Figure 1, and specific implementation is as follows:

(1) FPGA dynamic area state judgment, the specific implementation is as follows:

① Establish a dual-port BRAM with a width of 1 and a depth of 1. Driven by the main clock of the FPGA, the static area sets the value of the BRAM to a high level through port A. After 10 main clock cycles, the static area passes Port A reads and judges the level state of the value of the BRAM: when it is high, it indicates that the dynamic area is in the process of reconstruction; when it is low, it indicates that the dynamic area is in the process of non-reconstruction;

②The dynamic area reads and judges the level state of the value of the BRAM through port B in real time under the drive of the FPGA main clock. When it is high, the level state of the value of the BRAM is reset to low in the next clock cycle. flat;

③When there are k dynamic areas, k dual-port BRAMs with a width of 1 and a depth of 1 need to be established in the static area, and the status of each dynamic area is judged as ① and ②;

(2) The data cache BRAM is established in the static area of the FPGA to realize the cache of the reconstructed transient data. The specific implementation is as follows:

① A BRAM is established in the static area of the FPGA. When the static area detects that the dynamic area is in the process of being reconstructed, the static area caches the data to be processed in this BRAM;

②The FPGA static area caches data in different offset addresses of the BRAM according to the coordinates of each dynamic area in the physical area of the FPGA chip and the function ID of the reconfigured code running on the dynamic area;

(3) After the reconstruction is completed, the FPGA dynamic area sends an inquiry frame to the static area, and the frame format is specifically implemented as follows:

①Byte 0-1 is the frame header, that is, hexadecimal 5A, 54;

②Byte 2-11 is the data area, where byte 2-3 indicates the abscissa of the upper left vertex of the dynamic area in the physical area inside the FPGA chip; byte 4-5 indicates that the dynamic area is in the upper left of the physical area inside the FPGA chip The ordinate of the vertex; bytes 6-7 indicate the abscissa of the dynamic area in the lower right vertex of the internal physical area of the FPGA chip; bytes 8-9 indicate the ordinate of the dynamic area in the lower right vertex of the internal physical area of the FPGA chip ;Bytes 10-11 represent the function ID of the refactored code running on this dynamic area;

③Byte 12 is the end identifier of the data area, that is, hexadecimal 00;

④Byte 13 is the checksum, that is, the logical sum of each byte in the data area takes the low byte;

⑤Byte 14-15 is the length of the data area, and byte 14 is the high byte;

⑥Byte 16-17 is the end of the frame, that is, hexadecimal 5A, FE;

When the frame end appears in the data area in the query frame, that is, hexadecimal 5A, FE, the escape character hexadecimal 00 needs to be inserted before the 5A, FE; the length of the data area does not include the inserted escape character;

(4) The FPGA static area parses the query frame sent by the dynamic area. When parsing the query frame, the inserted escape character needs to be removed to obtain the coordinates of the dynamic area in the physical area of the FPGA chip and the reconstruction running on the dynamic area. The function ID of the code, and then the static area reads the corresponding data in the data cache BRAM;

(5) The FPGA static area returns a response frame to the dynamic area, and the frame format is specifically implemented as follows:

①Byte 0-1 is the frame header, that is, hexadecimal 5A, 54;

②Byte 2-(n+1) is the data area, that is, the data cached in the BRAM during reconstruction, where n is the data byte length;

③Byte n+2 is the end identifier of the data area, that is, hexadecimal 00;

④Byte n+3 is the checksum, that is, the logical sum of each byte in the data area takes the low byte;

⑤Byte n+4, n+5 are the length of the data area, wherein byte n+4 is the high byte;;

⑥Bytes n+6, n+7 are the end of the frame, that is, hexadecimal 5A, FE;

When the end of the frame appears in the data area of the response frame, that is, hexadecimal 5A, FE, the escape character hexadecimal 00 needs to be inserted before the 5A, FE; the length of the data area does not include the inserted escape character.

In summary, the present invention discloses a reliable transient processing method for heterogeneous multi-source data reconstruction, including: FPGA dynamic area state judgment; The query frame sent by the static area and the response frame returned by the FPGA static area to the dynamic area. The method can solve the reconstruction transient problem in heterogeneous multi-source data processing based on FPGA dynamic reconstruction, and realize reliable processing of heterogeneous multi-source data.

The contents not described in detail in the description of the present invention belong to the prior art known to those skilled in the art.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (2)

1. a kind of isomerous multi-source data reconstruction transient state reliable treatments method, it is characterised in that: the following steps are included:

Step 1: the judgement of FPGA dynamic zone state is implemented as follows:

1. establishing a width is 1, the dual-port BRAM that depth is 1, under the driving of FPGA master clock, static zones pass through port The numerical value that A sets the BRAM is high level, and after 10 master clock cycles, static zones are read by port A and judge this The level state of the numerical value of BRAM: when for high level, show that dynamic area is in restructuring procedure: when for low level, showing Dynamic area is in non-restructuring procedure；

2. dynamic area is read in real time and is judged the level shape of the numerical value of the BRAM by port B under the driving of FPGA master clock The level state of the numerical value of the BRAM is reset to low level in next clock cycle when for high level by state；

3. needing to establish k width in static zones is 1, the dual-port BRAM that depth is 1, each dynamic when there is k dynamic area The judgement of zone state is as 1. and 2.；

Step 2: FPGA establishes static zones data buffer storage BRAM and realizes to the caching of reconstruct transient data, is implemented as follows:

1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones will be to The data buffer storage of processing is in this BRAM；

2. the static zones FPGA are run in the coordinate in fpga chip internal physical region and on the dynamic area according to each dynamic area Reconfiguration code functional identity difference, respectively by data buffer storage in the different offset address of the BRAM；

Step 3: after the completion of reconstruct, FPGA dynamic area sends inquiry frame to static zones, and frame format is implemented as follows:

1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；

2. byte 2-11 is data field, wherein byte 2-3 indicates that the dynamic area is pushed up in the upper left in fpga chip internal physical region The abscissa of point；Byte 4-5 indicates the dynamic area in the ordinate of the left upper apex in fpga chip internal physical region；Byte 6- 7 indicate the dynamic area in the abscissa of the bottom right vertex in fpga chip internal physical region；Byte 8-9 indicates that the dynamic area exists The ordinate of the bottom right vertex in fpga chip internal physical region；Byte 10-11 indicates the reconstruct generation run on the dynamic area The functional identity of code；

3. byte 12 is data field end identifier, i.e. hexadecimal 00；

4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；

5. byte 14-15 is the length of data field, wherein byte 14 is high byte；

6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；

When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape character before 5A, the FE Hexadecimal 00；The length of data field does not include the escape character of insertion；

Step 4: the static zones FPGA parse the inquiry frame that dynamic area is sent, and need when frame is inquired in parsing by the escape word of insertion Symbol removal obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconfiguration code run on the dynamic area Functional identity, then corresponding data in data buffer storage BRAM are read in static zones；

Step 5: the static zones FPGA return to acknowledgement frame to dynamic area, and frame format is implemented as follows:

1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；

2. byte 2- (n+1) is data field, that is, the data being buffered in BRAM when reconstructing, wherein n is data byte length；

3. byte n+2 is data field end identifier, i.e. hexadecimal 00；

4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；

5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；

6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；

When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape character before 5A, the FE Hexadecimal 00；The length of data field does not include the escape character of insertion.

2. a kind of isomerous multi-source data reconstruction transient state reliable treatments method as described in claim 1, it is characterised in that: described Method is suitable for Xilinx company Virtex-5FPGA chip.