CN108258028B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: etching the first work function layer, and reserving the first work function layer positioned in the second P area, the first N area and the second N area; after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area; etching and removing the second work function layer of the second N region until the gate dielectric layer of the second N region is exposed; performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region; etching and removing the second work function layer of the first N region until the gate dielectric layer of the first N region is exposed; and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region. The invention reduces the complexity of the semiconductor structure forming process and saves the process steps.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a method for forming the same.

Background technique

The main semiconductor devices of integrated circuits, especially very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's Law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale the feature size of the semiconductor structure. Among them, in the field of semiconductor fabrication, the most challenging thing is how to solve the problem of large leakage current of the semiconductor structure. The large leakage current of the semiconductor structure is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.

The currently proposed solution is to use high-k gate dielectric material instead of traditional silicon dioxide gate dielectric material, and use metal as gate electrode to avoid Fermi level pinning effect and boron Penetration effect. The introduction of the high-k metal gate reduces the leakage current of the semiconductor structure.

Although the introduction of the high-k metal gate can improve the electrical performance of the semiconductor structure to a certain extent, the semiconductor structure formed in the prior art has a complicated process.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which simplifies the process steps while meeting the different requirements for the threshold voltage of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first N region for forming a first N-type device, a second N-region for forming a second N-type device An N region, a first P region for forming a first P-type device, and a second P region for forming a second P-type device, and the threshold voltage of the first N-type device is lower than the threshold voltage of the second N-type device voltage, the threshold voltage of the first P-type device is greater than the threshold voltage of the second P-type device; a gate dielectric is formed on the substrates of the first N region, the second N region, the first P region and the second P region layer and the first work function layer located on the gate dielectric layer; etching the first work function layer, leaving the first work function layer located in the second P region, the first N region and the second N region ; After etching the first work function layer, a second work function layer is formed on the first N region, the second N region, the first P region and the second P region; etching to remove the second The second work function layer of the N region and the first work function layer, until the gate dielectric layer of the second N region is exposed, until the gate dielectric layer of the second N region is exposed; for the second N region The gate dielectric layer of the second N region is subjected to oxygen vacancy passivation treatment to reduce the oxygen vacancy content in the gate dielectric layer of the second N region; the second work function layer and the first work function layer of the first N region are removed by etching, until the gate dielectric layer of the first N region is exposed; on the gate dielectric layers of the first N region and the second N region, and the second work function layer of the first P region and the second P region A third work function layer is formed thereon.

Optionally, a wet etching process is used to etch and remove the second work function layer of the second N region until the gate dielectric layer of the second N region is exposed, and the wet etching process The etching liquid is oxidizing.

Optionally, the wet etching process includes a main etching process and an over-etching process, wherein the oxygen vacancy passivation treatment is performed by using the over-etching process.

Optionally, the etching liquid used in the wet etching process is SC1 solution, SC2 solution or SPM solution.

Optionally, the etching duration of the over-etching process is 10s˜2min.

Optionally, the oxygen vacancy passivation treatment is performed using a treatment solution containing hydrogen peroxide.

Optionally, in the treatment solution, the mass concentration of hydrogen peroxide is 5% to 20%, and the temperature of the treatment solution is 20°C to 50°C.

Optionally, the treatment solution is SC1 solution, SC2 solution or SPM solution.

Optionally, the oxygen vacancy passivation treatment is performed first, and then the second work function layer and the first work function layer of the first N region are removed by etching.

Optionally, the material of the gate dielectric layer is a high-k gate dielectric material.

Optionally, before forming the gate dielectric layer, an interface layer is also formed on the substrate of the first N region, the second N region, the first P region and the second P region.

Optionally, the material of the first work function layer, the material of the second work function layer and the material of the third work function layer are all P-type work function materials.

Optionally, the P-type work function material includes one or more of Ta, TiN, TaN, TaSiN or TiSiN.

Optionally, it also includes the step of: forming an N-type work function layer on the third work function layer of the first N region, the second N region, the first P region and the second P region, and the N-type work function layer is The material work function type of the functional layer is different from that of the third work function layer; a gate electrode layer is formed on the N-type work function layer.

Optionally, the material of the N-type work function layer is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

Optionally, the process step of etching the first work function layer includes: forming a first pattern layer on the first work function layer of the first N region, the second N region and the second P region; The first pattern layer is a mask, and the first work function layer located in the first P region is removed by etching; the first pattern layer is removed.

Optionally, the process step of removing the second work function layer and the first work function layer of the first N region by etching includes: on the gate dielectric layer of the second N region and the first P region and forming a second pattern layer on the second work function layer of the second P region; using the second pattern layer as a mask, etching and removing the second work function layer and the first work function layer of the first N region ; remove the second graphics layer. The present invention also provides a semiconductor structure, comprising: a substrate including a first N region with a first N-type device, a second N region with a second N-type device, and a first N region with a first P-type device A P region and a second P region having a second P-type device, and the threshold voltage of the first N-type device is smaller than the threshold voltage of the second N-type device, and the threshold voltage of the first P-type device is larger than the second P-type device The threshold voltage of the type device; the gate dielectric layer located on the substrate of the first N region, the second N region, the first P region and the second P region, wherein the oxygen in the gate dielectric layer of the first N region The vacancy content is greater than the oxygen vacancy content in the gate dielectric layer of the second N region; a first work function layer located on the gate dielectric layer of the second P region; located on the gate dielectric layer of the first P region; A second work function layer on the first work function layer of the second P region; on the gate dielectric layer of the first N region and the second N region, and the first P region and the second P region The third work function layer on the second work function layer.

Optionally, the material of the first work function layer, the material of the second work function layer, and the material of the third work function layer are all P-type work function materials.

Optionally, the semiconductor structure further includes: an N-type work function layer on the third work function layer; and a gate electrode layer on the N-type work function layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the method for forming a semiconductor structure provided by the embodiment of the present invention, in forming a first N-type device and a second N-type device with different threshold voltages, and a first P-type device and a second P-type device with different threshold voltages During the process of the device, the gate dielectric layer of the second N region is subjected to oxygen vacancy passivation treatment, so that the content of oxygen vacancies in the gate dielectric layer of the first N region is greater than the content of oxygen vacancies in the gate dielectric layer of the second N region. The difference in oxygen vacancy content makes the threshold voltages of the first N-type device and the second N-type device different; therefore, the third work function layer formed is located in both the first N region and the second N region, avoiding etching The process step of removing the third work function layer of the first N region does not need to form the fourth work function layer, thereby simplifying the process steps and meeting the requirement that the threshold voltage of the first N-type device is lower than the threshold voltage of the second N-type device. Moreover, the present invention reduces the number of the formed work function layers, makes the formed semiconductor structure simpler, and increases the process window for the subsequent formation of the gate electrode layer.

In an optional solution, a wet etching process is used to etch and remove the second work function layer located in the second N region, and the wet etching process includes a main etching process and an over-etching process. The oxygen vacancy passivation treatment is performed through an over-etching process, so no additional process steps are required to perform the oxygen vacancy passivation treatment.

Description of drawings

1 to 3 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure;

4 to 11 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that the electrical properties of the semiconductor structures formed in the prior art need to be improved. Especially when the semiconductor structure includes P-type devices with different threshold voltages (Threshold Voltage) and N-type devices with different threshold voltages, the problem of the complex formation process of the semiconductor structure is particularly significant.

In order to meet the requirements of improving the threshold voltage of NMOS transistors and PMOS transistors at the same time, different metal materials are usually used as the work function (WF, Work Function) layer material in the gate structure of the NMOS transistor and the PMOS transistor, and the work function layer in the NMOS transistor. The material may be referred to as an N-type work function material, and the material of the work function layer in the PMOS tube may be referred to as a P-type work function material. Usually, the thickness of the P-type work function layer between the gate dielectric layer and the N-type work function layer is adjusted to meet the requirements of different threshold voltages of the device.

1 to 3 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure.

Referring to FIG. 1, a substrate 11 is provided, the substrate 11 includes a first N region 101 and a second N region 102, the first N region 101 is used for forming a first N-type device, and the second N region 102 is used for forming a second N region type device, and the threshold voltage of the first N-type device is lower than that of the second N-type device; an interface layer 12 is formed on the substrate 11 ; a gate dielectric layer 13 is formed on the interface layer 12 ; A first work function layer 14 and a second work function layer 15 on the first work function layer 14 are formed on the gate dielectric layer 13 of an N region 101 ; on the second work function layer 15 of the first N region 101 and A third work function layer 16 is formed on the gate dielectric layer 13 of the second N region 102 .

The substrate further includes a first P region and a second P region, and the threshold voltage of the P-type device formed by the first P region is different from the threshold voltage of the P-type device formed by the second P region.

Referring to FIG. 2 , the third work function layer 16 , the second work function layer 15 (refer to FIG. 1 ) and the first work function layer 14 located on the first N region 101 are removed by etching, exposing the first N the surface of the gate dielectric layer 13 in the region 101 .

Referring to FIG. 3 , a fourth work function layer 17 is formed on the gate dielectric layer 13 of the first N region 101 and on the third work function layer 16 of the second N region 102 .

The above-mentioned formation method is complicated, and in order to meet different threshold voltage requirements of the first N-type device, the second N-type device, the first P-type device and the second P-type device, at least four work function layers need to be formed.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first N region for forming a first N-type device, a second N-region for forming a second N-type device An N region, a first P region for forming a first P-type device, and a second P region for forming a second P-type device, and the threshold voltage of the first N-type device is lower than the threshold voltage of the second N-type device voltage, the threshold voltage of the first P-type device is greater than the threshold voltage of the second P-type device; a gate dielectric is formed on the substrates of the first N region, the second N region, the first P region and the second P region layer and the first work function layer located on the gate dielectric layer; etching the first work function layer, leaving the first work function layer located in the second P region; etching the first work function layer After layering, a second work function layer is formed on the first N region, the second N region, the first P region and the second P region; the second work function layer of the second N region is removed by etching until exposing the gate dielectric layer of the second N region; performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the content of oxygen vacancies in the gate dielectric layer of the second N region; etching removing the second work function layer of the first N region until the gate dielectric layer of the first N region is exposed; on the gate dielectric layers of the first N region and the second N region, and the first N region A third work function layer is formed on the second work function layer of the first P region and the second P region.

The present invention saves the process steps, simplifies the process complexity while forming the first N-type device, the second N-type device, the first P-type device, and the second P-type device with different threshold voltages. The number of work function layers is small.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

4 to 11 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to Figure 4, a substrate 201 is provided.

The substrate 201 includes a first N region I1 for forming a first N-type device, a second N region I2 for forming a second N-type device, a first P region II1 for forming a first P-type device, and A second P region II2 for forming a second P-type device, and the threshold voltage of the first N-type device is smaller than the threshold voltage of the second N-type device, and the threshold voltage of the first P-type device is greater than the second P-type device threshold voltage of the device.

The first N region I1 is adjacent to the second N region I2, the second N region I2 is adjacent to the first P region II1, and the first P region II1 is adjacent to the second P region II2 Take as an example.

In this embodiment, taking the semiconductor structure formed as a planar device as an example, the base 201 is a planar substrate; the material of the base 201 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium , the substrate 201 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In other embodiments, when the formed semiconductor structure is a fin field effect transistor, the base includes a substrate and a fin on the substrate, and the base further includes a substrate exposed on the fin The isolation structure on the top of the isolation structure covers part of the sidewall of the fin, and the top of the isolation structure is lower than the top of the fin.

In this embodiment, the first N region I1 includes an N-type ultra-low threshold voltage (ULVT, Ultra-low VT) region and an N-type low threshold voltage (low VT) region; the second N region I2 is an N-type region Standard threshold voltage region (Standard VT). In other embodiments, the first N region may also include only one of an N-type low threshold voltage region or an N-type ultra-low threshold voltage region.

In this embodiment, the first P region II1 is a P-type standard threshold voltage region, and the second P region II2 includes a P-type ultra-low threshold voltage region and a P-type low threshold voltage region. In other embodiments, the second P region may also include only one of a P-type ultra-low threshold voltage region or a P-type low threshold voltage region.

It should be noted that, in this embodiment, before the subsequent formation of the gate dielectric layer 203, the method further includes: performing a first N-type threshold adjustment doping treatment on the substrate 201 corresponding to the N-type ultra-low threshold voltage region, The substrate 201 corresponding to the N-type low threshold voltage region is subjected to the second N-type threshold adjustment doping treatment; the substrate 201 corresponding to the P-type ultra-low threshold voltage region is subjected to the first P-type threshold adjustment doping treatment, and the P The substrate 201 corresponding to the P-type low threshold voltage region is subjected to the second P-type threshold adjustment doping treatment.

Specifically, the doping ions of the first N-type threshold adjustment doping treatment and the second N-type threshold adjustment doping treatment are N-type ions, and the N-type ions include P, As or Sb, and the first N-type threshold value The doping concentration of the adjustment doping treatment is smaller than the doping concentration of the second N-type threshold adjustment doping treatment. The doping ions of the first P-type threshold adjustment doping treatment and the second P-type threshold adjustment doping treatment are P-type ions, the P-type ions include B, Ga or In, and the first P-type threshold adjustment doping The doping concentration of the treatment is less than the doping concentration of the second P-type threshold adjustment doping treatment.

In this embodiment, the gate structure of the semiconductor structure is formed by using a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high k last metal gate last) as an example. Before forming the gate dielectric layer 203, the method further includes:

A dummy gate structure is formed on the substrate 201 of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, wherein the first N region I1 and the first P region are II1 is adjacent, so the dummy gate structure spans the first N region I1 and the first P region II1, and correspondingly, the gate electrode layer formed subsequently spans the first N region I1 and the first P region II1.

After the dummy gate structure is formed, source and drain doped regions of each device are formed in the substrate 201 on both sides of the dummy gate structure in each region; after the source and drain doped regions are formed, the dummy gate structure is exposed An interlayer dielectric layer is formed on the substrate 201, and the interlayer dielectric layer exposes the top of the dummy gate structure; after the interlayer dielectric layer is formed, the dummy gate structure is removed.

Subsequently, the gate dielectric layer 203 is formed on a portion of the substrate 201 of the first N region I1, the second N region I2, the first P region II1 and the second P region II2. It should be noted that, in other embodiments, the semiconductor structure may also be formed by a process of first forming a high-k gate dielectric layer and then forming a gate electrode layer (high k first metal gate last).

Continuing to refer to FIG. 4 , a gate dielectric layer 203 and a gate dielectric layer 203 are formed on the substrate 201 of the first N region I1 , the second N region I2 , the first P region II1 and the second P region II2 . The first work function layer 204 .

The material of the gate dielectric layer 203 is a high-k gate dielectric material, wherein the high-k gate dielectric material is a gate dielectric material with a relative permittivity greater than that of silicon oxide.

In this embodiment, the material of the gate dielectric layer 203 is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

In order to improve the interface performance between the substrate 201 and the gate dielectric layer 203, before forming the gate dielectric layer 203, an interface layer 202 is also formed on the substrate 201, correspondingly, the gate dielectric layer 203 on the surface of the interface layer 202 .

The interface layer 202 provides a good interface foundation for forming the gate dielectric layer 203, thereby improving the quality of the gate dielectric layer 203 formed and reducing the interface state density between the gate dielectric layer 203 and the substrate 201, In addition, adverse effects caused by the direct contact between the gate dielectric layer 203 and the substrate 201 are avoided.

In this embodiment, the material of the interface layer 202 is silicon oxide. In other embodiments, the material of the interface layer may also be silicon nitride or silicon oxynitride.

The material of the first work function layer 204 is a P-type work function material. Specifically, the first work function layer 204 located on the second P region II2 is used as a part of the work function layer corresponding to the second P type device to adjust the threshold voltage of the second P type device.

The P-type work function material has a work function ranging from 5.1 eV to 5.5 eV, eg, 5.2 eV, 5.3 eV or 5.4 eV. The material of the first work function layer 204 is one or more of Ta, TiN, TaN, TaSiN or TiSiN, and the first work function can be formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. Function layer 204 .

In this embodiment, the material of the first work function layer 204 is TiN, and the thickness of the first work function layer 204 is 10 angstroms to 30 angstroms.

Referring to FIG. 5 , the first work function layer 204 is etched, and the first work function layer 204 located in the second P region II2 , the first N region I1 and the second N region I2 remains.

In this embodiment, etching the first work function layer 204 and retaining the first work function layer 204 located in the first P region II2 includes: etching and removing the first work function in the first P region II1 The layer 204 retains the first work function layer 204 located in the first N region I1, the second N region II2 and the second P region II2.

Specifically, the process step of etching the first work function layer 204 includes: forming a first pattern on the first work function layer 204 of the first N region I1, the second N region I2 and the second P region II2 layer; using the first pattern layer as a mask, etching and removing the first work function layer 204 located in the first P region II1; removing the first pattern layer.

In this embodiment, in the process of etching the first work function layer 204, the first work function layer 204 located in the first N region I1 and the second N region I2 is reserved to avoid the first N region The gate dielectric layer 203 of the I1 and the second N region I2 causes etching damage, which reduces the damage to the gate dielectric layer 203 of the first N region I1 and the second N region I2 during the process.

Referring to FIG. 6 , after the first work function layer 204 is etched, a second work function layer is formed on the first N region I1 , the second N region I2 , the first P region II1 and the second P region II2 205.

In this embodiment, forming the second work function layer 205 includes: on the first work function layer 204 of the first N region I1, the second N region I2 and the second P region II2, and a first P The second work function layer 205 is formed on the gate dielectric layer 203 in the region II1.

The material of the second work function layer 205 is a P-type work function material. The second work function layer 205 located on the first P region II1 is a part of the work function layer corresponding to the first P type device, and plays the role of adjusting the threshold voltage of the first P type device; The second work function layer 205 on the two P regions II2 is a part of the work function layer corresponding to the second P-type device, and plays the role of adjusting the threshold voltage of the second P-type device.

The material of the second work function layer 205 is one or more of Ta, TiN, TaN, TaSiN or TiSiN.

In this embodiment, the material of the second work function layer 205 is TiN, and the thickness of the second work function layer 205 is 10 angstroms to 30 angstroms.

Referring to FIG. 7 , the second work function layer 205 and the first work function layer 204 of the second N region I2 are removed by etching, and the gate dielectric layer 203 of the second N region I2 is exposed.

In this embodiment, before the second work function layer 205 is formed, the first work function layer 204 located in the second N region I2 remains; therefore, the second N region I2 is removed by etching The work function layer 205 includes: etching and removing the second work function layer 205 of the second N region I2, and also etching and removing the first work function layer 204 of the second N region I2.

Before removing the second work function layer 205 of the second N region I2 by etching, the method further includes: the second work function layer 205 of the first N region I1, the first P region II1 and the second P region II2 A mask layer 200 is formed thereon.

In this embodiment, the material of the mask layer 200 is silicon nitride. In other embodiments, the material of the mask layer may also be a photoresist material.

The mask layer 200 serves to protect the second work function layer 205 of the first N region I1, the first P region II1 and the second P region II2 from being etched. In addition, in this embodiment, after the subsequent oxygen vacancy passivation treatment, the mask layer 200 is removed. The region II1 and the second P region II2 play a protective role.

Using a wet etching process, the second work function layer 205 and the first work function layer 204 of the second N region I2 are etched and removed until the gate dielectric layer 203 of the second N region I2 is exposed.

In this embodiment, the etching liquid of the wet etching process has an oxidizing property. The advantage is that the wet etching process can not only etch and remove the second work function layer 205 and the first work function layer 204 of the second N region I2, but also can etch and remove the exposed part of the second N region I2. The gate dielectric layer 203 is subjected to oxygen vacancy passivation treatment.

Specifically, the wet etching process includes a main etching process (main etch) and an overetching process (overetch), wherein the subsequent oxygen vacancy passivation treatment is performed by using the overetching process.

The etching liquid used in the wet etching process is SC1 solution, SC2 solution or SPM solution.

The SC1 solution is an aqueous solution of ammonia and hydrogen peroxide; the SC2 solution is an aqueous solution of hydrochloric acid and hydrogen peroxide; and the SPM solution is an aqueous solution of sulfuric acid and hydrogen peroxide.

Referring to FIG. 8 , oxygen vacancy passivation treatment 206 is performed on the gate dielectric layer 203 of the second N region I2 to reduce the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2 .

Defects are easily formed in the gate dielectric layer 203, and the defects include one or more of oxygen vacancies, dangling bonds or unbonded ions. In this embodiment, the gate dielectric layer 203 contains oxygen vacancy defects.

The oxygen vacancy passivation treatment 206 is performed on the gate dielectric layer 203 of the second N region I2, which is beneficial to reduce the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2, so that the gate of the first N region I1 is The content of oxygen vacancies in the dielectric layer 203 is greater than the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2.

Since the oxygen vacancy content in the gate dielectric layer 203 of the first N region I1 is greater than the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2, the dipole in the gate dielectric layer 203 of the first N region I1 is The number of dipoles is greater than the number of dipoles in the gate dielectric layer 203 of the second N region I2; correspondingly, the flat band voltage between the gate structure and the substrate 201 formed subsequently by the first N-type device is higher than that of the second N-type device. The flat-band voltage between the gate structure and the substrate 201 is formed so that the threshold voltage of the first N-type device formed is higher than the threshold voltage of the second N-type device.

In this embodiment, the oxygen vacancy passivation treatment 206 is performed by extending the etching duration of the over-etching process in the aforementioned wet etching process, so that the process operation of the oxygen vacancy passivation treatment 206 is simple, and no additional operation is required. process steps.

Specifically, the etching duration of the over-etching process should not be too short or too long. If the etching time of the over-etching process is too short, the reduction degree of oxygen vacancies in the gate dielectric layer 203 of the second N region I2 is low; if the etching time of the over-etching process is too long, Then, the oxygen vacancy passivation treatment 206 will adversely affect the gate dielectric layer 203 of the second N region I2.

Therefore, in this embodiment, the etching duration of the over-etching process is 10s˜2min.

In other embodiments, after the second work function layer and the first work function layer of the second N region are removed by etching, the oxygen vacancy passivation treatment may be performed by using a treatment solution containing hydrogen peroxide, The treatment solution may be an SC1 solution, an SC2 solution or an SPM solution.

It should be noted that, in the treatment solution, the content of hydrogen peroxide should not be too low or too high. If the hydrogen peroxide content is too low, the efficiency of the oxygen vacancy passivation treatment is low; if the hydrogen peroxide content is too high, the oxygen vacancy passivation treatment is likely to cause damage to the gate dielectric layer of the second N region adverse effects. Correspondingly, the temperature of the treatment solution should not be too low nor too high.

For this reason, when the oxygen vacancy passivation treatment is performed with a treatment solution containing hydrogen peroxide, the mass concentration of hydrogen peroxide in the treatment solution is 5%-20%, and the temperature of the treatment solution is 20-50°C.

After the oxygen vacancy passivation treatment 206 is performed, the mask layer 200 is removed.

Referring to FIG. 9 , the second work function layer 205 and the first work function layer 204 of the first N region I1 are removed by etching until the gate dielectric layer 203 of the first N region I1 is exposed.

In this embodiment, before the second work function layer 205 is formed, the first work function layer 204 located on the first N region I1 is reserved. Therefore, the first N region I1 is removed by etching. The second work function layer 205 includes: etching and removing the second work function layer 205 of the first N region I1, and also etching and removing the first work function layer 204 of the first N region I1.

Using a wet etching process, the second work function layer 205 and the first work function layer 204 of the first N region I1 are removed by etching. Specifically, the process steps of etching and removing the second work function layer 205 and the first work function layer 204 of the first N region I1 include: on the gate dielectric layer 203 of the second N region I2, and the A second pattern layer is formed on the second work function layer 205 of the first P region II1 and the second P region II2; using the second pattern layer as a mask, the second work function of the first N region I1 is removed by etching The function layer 205 and the first work function layer 204; the second graphics layer is removed.

In this embodiment, the oxygen vacancy passivation treatment 206 (refer to FIG. 8 ) is performed first, and then the second work function layer 205 and the first work function layer 204 of the first N region I1 are removed by etching to avoid the above The oxygen vacancy passivation treatment affects the gate dielectric layer 203 of the first N region I1.

It should also be noted that, in other embodiments, before performing the oxygen vacancy passivation treatment, the second work function layer and the first work function layer of the first N region may be removed by etching; In the same process step, the second work function layer and the first work function layer of the first N region and the second N region are removed by etching; and before the oxygen vacancy passivation treatment is performed, the method further includes: A protective layer is formed on the gate dielectric layer of the first N region.

Referring to FIG. 10 , a third layer is formed on the gate dielectric layer 203 of the first N region I1 and the second N region I2 and on the second work function layer 205 of the first P region II1 and the second P region II2 Work function layer 207 .

The third work function layer 204 located on the first N region I1 serves as a part of the work function layer corresponding to the first N-type device, and plays the role of adjusting the threshold voltage of the first N-type device; it is located in the second N region. As a part of the work function layer corresponding to the second N-type device, the third work function layer 204 on the I2 plays a role of adjusting the threshold voltage of the second N-type device.

The second work function layer 205 and the third work function layer 207 located on the first P region II1 serve as work function layers corresponding to the first P-type device, and play the role of adjusting the threshold voltage of the first P-type device; The first work function layer 204, the second work function layer 205 and the third work function layer 207 on the second P region II2 are used as work function layers corresponding to the second P-type device to adjust the threshold voltage of the second P-type device. effect.

For a P-type device, the thicker the work function layer is, the lower the threshold voltage of the correspondingly formed P-type device is. Since the thickness of the work function layer corresponding to the first P-type device is thinner than that of the work function layer corresponding to the second P-type device, the threshold voltage of the subsequently formed first P-type device is greater than the threshold voltage of the second P-type device .

The material of the third work function layer 207 is a P-type work function material; the material of the third work function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN.

In this embodiment, the material of the third work function layer 207 is TiN, and the thickness of the third work function layer 207 is 10 angstroms to 30 angstroms.

The third work function layer 207 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

The flat-band voltage Vfb between the gate structure of the first N-type device and the substrate 201 is related to the thickness of the work function layer of the first N-type device, and the flat-band voltage of the first N-type device is also It is related to the number of dipoles in the gate dielectric layer 203 of the first N region I1; the flat band voltage Vfb between the gate structure of the second N-type device and the substrate 201 is related to the second The thickness of the work function layer of the N-type device is related to the thickness of the work function layer of the N-type device, and the flat band voltage of the second N-type device is also related to the number of dipoles in the gate dielectric layer 203 of the second N-type region I2.

Since the oxygen vacancy passivation treatment 206 is performed on the gate dielectric layer 203 of the second N region I2, the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2 is lower than that of the gate dielectric of the first N region I1 The content of oxygen vacancies in the layer 203 makes the amount of dipoles in the gate dielectric layer 203 of the second N region I2 smaller than that in the gate dielectric layer 203 of the first N region I1. Therefore, even if the thickness of the work function layer of the first N-type device is equal to that of the second N-type device, the flat-band voltage of the first N-type device is greater than that of the second N-type device, so that the The threshold voltage of the first N-type device is formed to be higher than the threshold voltage of the second N-type device.

Therefore, in this embodiment, before the subsequent formation of the N-type work function layer, the thicknesses of the work function layers on the first N region I1 and the second N region I2 are the same, and there is no need to perform etching to remove the first N region The third work function layer 207 and the process steps of forming the fourth work function layer on the first N region and the second N region, thereby simplifying the formation process steps of the semiconductor structure, so that the number of work function film layers in the semiconductor structure is reduced .

Referring to FIG. 11, an N-type work function layer 208 is formed on the third work function layer 207 of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, and the N The material work function type of the type work function layer 208 is different from that of the third work function layer 207 ; a gate electrode layer (not shown) is formed on the N type work function layer 208 .

The third work function layer 207 and the N-type work function layer 208 located on the first N region I1 serve as work function layers corresponding to the first N-type device, and play the role of adjusting the threshold voltage of the first N-type device; The third work function layer 207 and the N-type work function layer 208 on the second N region I2 are used as work function layers corresponding to the second N-type device, and play a role in adjusting the threshold voltage of the second N-type device.

For an N-type device, since the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2 is less than the oxygen vacancy content in the gate dielectric layer 203 of the first N region I1, and the power corresponding to the first N-type device The thickness of the function layer is equal to the thickness of the work function layer corresponding to the second N-type device, so the threshold voltage of the second N-type device formed subsequently is greater than the threshold voltage of the first N-type device.

It should be noted that, in order to reduce the process steps and save the mask, in this embodiment, after the N-type work function layer 208 is formed, the N-type on the first P region II1 and the second P region II2 are reserved. Work function layer 208 .

The material of the N-type work function layer 208 is an N-type work function material, and the work function of the N-type work function material ranges from 3.9 eV to 4.5 eV, for example, 4 eV, 4.1 eV or 4.3 eV. The material of the N-type work function layer 208 is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN, and the N-type work function layer 208 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Type work function layer 208 .

In this embodiment, the material of the N-type work function layer 208 is TiAl, and the thickness of the N-type work function layer 208 is 10 angstroms to 50 angstroms.

The subsequent process steps further include: forming a gate electrode layer on the N-type work function layer 208 .

In this embodiment, the gate electrode layer spans the first N region I1, the first P region II1, the second P region II2 and the second N region I2. Correspondingly, the first N region I1, the first N region A P region II1, a second P region II2 and a second N region I2 share the same gate electrode layer. In other embodiments, the gate electrode layers located in the first N region, the second N region, the first P region and the second P region may also be independent of each other.

The material of the gate electrode layer includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

Specifically, the process step of forming the gate electrode layer includes: forming a gate electrode film on the N-type work function layer 208, and the top of the gate electrode film is higher than the top of the interlayer dielectric layer (not shown); The gate electrode film above the top of the interlayer dielectric layer is removed by grinding to form the gate electrode layer.

In the technical solution of the method for forming a semiconductor structure provided by the embodiment of the present invention, in forming a first N-type device and a second N-type device with different threshold voltages, and a first P-type device and a second P-type device with different threshold voltages During the process of the device, the gate dielectric layer 203 of the second N region I2 is subjected to oxygen vacancy passivation treatment, so that the content of oxygen vacancies in the gate dielectric layer 203 of the first N region I1 is greater than that of the gate dielectric layer 203 of the second N region I2 The content of internal oxygen vacancies makes the threshold voltages of the first N-type device and the second N-type device different due to the difference in the content of oxygen vacancies; therefore, the third work function layer formed is located in both the first N region I1 and the second N-type device. The N region I2 avoids the process step of etching and removing the third work function layer 207 of the first N region I1, and does not need to form a fourth work function layer, thereby simplifying the process steps and satisfying the threshold voltage of the first N-type device is less than The second N-type device threshold voltage requirement.

Correspondingly, the present invention also provides a semiconductor structure. Referring to FIG. 11 , the semiconductor structure includes:

a substrate comprising a first N-region I1 with a first N-type device, a second N-region I2 with a second N-type device, a first P-region II1 with a first P-type device, and a second P-type device The second P-region II2 of the device, and the threshold voltage of the first N-type device is smaller than the threshold voltage of the second N-type device, and the threshold voltage of the first P-type device is greater than the threshold voltage of the second P-type device ;

The gate dielectric layer 203 located on the substrate of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, wherein the gate dielectric layer 203 of the first N region I1 The oxygen vacancy content is greater than the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2;

a first work function layer 204 located on the gate dielectric layer 203 of the second P region II2;

a second work function layer 205 located on the gate dielectric layer 203 of the first P region II1 and the first work function layer 204 of the second P region II2;

The third work function layer 207 is located on the gate dielectric layer 203 of the first N region I1 and the second N region I2, and on the second work function layer 205 of the first P region II1 and the second P region II2.

The semiconductor structure provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For the description of the substrate 201 and the gate dielectric layer 203 , reference may be made to the corresponding descriptions of the foregoing embodiments, which will not be repeated here. In this embodiment, the semiconductor structure further includes: an interface layer 202 located between the substrate 201 and the gate dielectric layer 203 .

The semiconductor structure further includes: an N-type work function layer 208 located on the third work function layer 207 ; a gate electrode layer located on the N-type work function layer 208 .

The material of the first work function layer 204 is one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the second work function layer 205 is Ta, TiN, TaN, TaSiN or TiSiN. One or more; the material of the third work function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the N-type work function layer 208 is TiAl, TiAlC, TaAlN , one or more of TiAlN, TaCN and AlN.

In this embodiment, the material of the first work function layer 204 is TiN, the material of the second work function layer 205 is TiN, the material of the third work function layer 207 is TiN, and the N-type work function The material of layer 208 is TiAl. The thickness of the first work function layer 204 is 10 angstroms to 30 angstroms; the thickness of the second work function layer 205 is 10 angstroms to 30 angstroms; the thickness of the third work function layer 207 is 10 angstroms to 30 angstroms. ; The thickness of the N-type work function layer 208 is 10 angstroms to 50 angstroms.

In this embodiment, since the content of oxygen vacancies in the gate dielectric layer 203 of the first N region I1 is greater than the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2, and the third work function layer 207 and the N-type work function The layers 208 are both located on the first N region I and the second N region I2, so that the thicknesses of the work function layers on the first N region I1 and the second N region I2 are the same, and the threshold voltage of the first N-type device is smaller than that of the second N region I2. N-type device threshold voltage requirements.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first N region for forming a first N type device, a second N region for forming a second N type device, a first P region for forming a first P type device and a second P region for forming a second P type device, and the threshold voltage of the first N type device is less than the threshold voltage of the second N type device, and the threshold voltage of the first P type device is greater than the threshold voltage of the second P type device; forming a gate dielectric layer and a first work function layer on the gate dielectric layer on the substrate of the first N region, the second N region, the first P region and the second P region;

etching the first work function layer, and reserving the first work function layers positioned in the second P area, the first N area and the second N area;

after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area;

etching to remove the second work function layer and the first work function layer of the second N region until the gate dielectric layer of the second N region is exposed;

performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region;

etching to remove the second work function layer and the first work function layer of the first N region until the gate dielectric layer of the first N region is exposed;

and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.

2. The method for forming a semiconductor structure according to claim 1, wherein the second work function layer and the first work function layer in the second N region are removed by etching by using a wet etching process until the gate dielectric layer in the second N region is exposed, and an etching liquid in the wet etching process has an oxidizing property.

3. The method of forming a semiconductor structure of claim 2, wherein the wet etching process comprises a main etching process and an over-etching process, wherein the oxygen vacancy passivation process is performed using the over-etching process.

4. The method for forming a semiconductor structure according to claim 3, wherein the etching liquid used in the wet etching process is a SC1 solution, a SC2 solution, or a SPM solution.

5. The method for forming a semiconductor structure according to claim 3, wherein an etching time of the over-etching process is 10s to 2 min.

6. The method of forming a semiconductor structure of claim 1, wherein said oxygen vacancy passivation treatment is performed using a treatment solution containing hydrogen peroxide.

7. The method of claim 6, wherein the treatment solution has a hydrogen peroxide concentration of 5% to 20% by mass and a treatment solution temperature of 20 ℃ to 50 ℃.

8. The method of claim 6, wherein the treatment solution is a SC1 solution, a SC2 solution, or a SPM solution.

9. The method of claim 1, wherein the oxygen vacancy passivation is performed first, and then the second work function layer and the first work function layer of the first N region are removed by etching.

10. The method of claim 1, wherein the gate dielectric layer is formed of a high-k gate dielectric material.

11. The method of claim 10, further comprising forming an interfacial layer over the substrate of the first N region, the second N region, the first P region, and the second P region prior to forming the gate dielectric layer.

12. The method of claim 1, wherein the first work function layer, the second work function layer, and the third work function layer are all P-type work function materials.

13. The method of forming a semiconductor structure of claim 12, wherein the P-type work function material comprises one or more of Ta, TiN, TaN, TaSiN, or TiSiN.

14. The method of forming a semiconductor structure of claim 1, further comprising the steps of: forming an N-type work function layer on a third work function layer of the first N region, the second N region, the first P region and the second P region, wherein the type of a material work function of the N-type work function layer is different from that of the third work function layer; and forming a gate electrode layer on the N-type work function layer.

15. The method for forming a semiconductor structure according to claim 14, wherein a material of the N-type work function layer is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.

16. The method of forming a semiconductor structure of claim 1, wherein the process step of etching the first work function layer comprises: forming a first graph layer on the first work function layer of the first N area, the second N area and the second P area; etching and removing the first work function layer positioned in the first P area by taking the first graph layer as a mask; and removing the first graphic layer.

17. The method for forming a semiconductor structure according to claim 1, wherein the step of removing the second work function layer and the first work function layer of the first N region by etching comprises: forming a second graph layer on the gate dielectric layer of the second N region and the second work function layers of the first P region and the second P region; etching and removing the second work function layer and the first work function layer in the first N area by taking the second graph layer as a mask; and removing the second graphic layer.

18. A semiconductor structure, comprising:

a substrate comprising a first N region having a first N type device, a second N region having a second N type device, a first P region having a first P type device, and a second P region having a second P type device, and the first N type device having a threshold voltage less than the threshold voltage of the second N type device, the first P type device having a threshold voltage greater than the threshold voltage of the second P type device;

the gate dielectric layer is positioned on the substrate of the first N region, the second N region, the first P region and the second P region, wherein the content of oxygen vacancies in the gate dielectric layer of the first N region is greater than that of oxygen vacancies in the gate dielectric layer of the second N region;

the first work function layer is positioned on the gate dielectric layer of the second P area;

a second work function layer located on the gate dielectric layer of the first P region and on the first work function layer of the second P region;

and the third work function layer is positioned on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.

19. The semiconductor structure of claim 18, wherein the material of the first work function layer, the material of the second work function layer, and the material of the third work function layer are all P-type work function materials.

20. The semiconductor structure of claim 18, wherein the semiconductor structure further comprises: an N-type work function layer on the third work function layer; and the gate electrode layer is positioned on the N-type work function layer.

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