[go: up one dir, main page]

CN108333912B - A Time Correction Method for Switched Capacitor Array Chip - Google Patents

A Time Correction Method for Switched Capacitor Array Chip Download PDF

Info

Publication number
CN108333912B
CN108333912B CN201810135454.8A CN201810135454A CN108333912B CN 108333912 B CN108333912 B CN 108333912B CN 201810135454 A CN201810135454 A CN 201810135454A CN 108333912 B CN108333912 B CN 108333912B
Authority
CN
China
Prior art keywords
sampling
switched capacitor
capacitor array
time
array chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810135454.8A
Other languages
Chinese (zh)
Other versions
CN108333912A (en
Inventor
赵雷
秦家军
刘树彬
安琪
成博宇
陈晗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Science and Technology of China USTC
Original Assignee
University of Science and Technology of China USTC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Science and Technology of China USTC filed Critical University of Science and Technology of China USTC
Priority to CN201810135454.8A priority Critical patent/CN108333912B/en
Publication of CN108333912A publication Critical patent/CN108333912A/en
Application granted granted Critical
Publication of CN108333912B publication Critical patent/CN108333912B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G06F17/12—Simultaneous equations, e.g. systems of linear equations

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • Operations Research (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

本发明公开了一种用于开关电容阵列芯片的时间修正方法，该方法的创新点是通过利用采样信号周期与采样间隔之间的关系，构建超定线性方程组并求解，以获得开关电容阵列芯片实际的采样间隔，再利用该采样间隔对时间测量结果进行修正。这种方法具有算法简单高效，计算结果不受芯片模拟带宽以及各采样单元增益偏差限制，精度高等特点；可应用于基于开关电容阵列芯片的高精度时间测量领域，包括高能物理实验中的飞行时间探测系统、中微子测量、医疗成像领域的PET仪器等。

Figure 201810135454

The invention discloses a time correction method for a switched capacitor array chip. The innovation of the method is to construct an overdetermined linear equation system and solve it by using the relationship between the sampling signal period and the sampling interval to obtain a switched capacitor array The actual sampling interval of the chip, and then use the sampling interval to correct the time measurement result. This method has the characteristics of simple and efficient algorithm, the calculation results are not limited by the chip simulation bandwidth and the gain deviation of each sampling unit, and has the characteristics of high precision; it can be applied to the field of high-precision time measurement based on switched capacitor array chips, including the time of flight in high-energy physics experiments. Detection systems, neutrino measurement, PET instruments in the field of medical imaging, etc.

Figure 201810135454

Description

Time correction method for switched capacitor array chip
Technical Field
The invention relates to the field of precision time measurement, in particular to a time correction method for a switched capacitor array chip.
Background
Precision time measurement is widely applied to particle physics experiments, such as time-of-flight detector systems, neutron measurement experiments, gamma ray measurement, and plays a very important role in Positron Emission Tomography (PET) systems in the medical imaging field. The conventional Time measurement method is implemented based on a leading edge timing, multi-threshold discrimination or Constant Fraction timer (CFD) technique in conjunction with a Time To Digital Converter (TDC). In these methods both the timing circuit and the TDC circuit affect the final time measurement accuracy. Research in recent years shows that higher time measurement accuracy can be realized by firstly obtaining a complete waveform by using a full-waveform digitization technology and then obtaining time information by using a digital signal processing method. A classical waveform digitizing method is based on an analog-to-Digital converter (ADC), but as an alternative, a waveform digitizing technology based on a Switched Capacitor Array (SCA) Application Specific Integrated Circuit (ASIC) is receiving more and more attention and research due to its advantages of high sampling rate, low power consumption, high channel integration, and relatively low price.
In the current high-speed SCA chip, the sampling clock is generated by an inverter delay chain, which is schematically shown in fig. 1, so the sampling interval between adjacent sampling units is determined by the delay of the corresponding inverter. However, due to the influence of process variations, the delays of inverters at different levels in an actual chip are different, which results in a certain inconsistency between sampling intervals. This inconsistency, if not corrected, can limit the accuracy of the time measurement. So far, some documents have discussed this problem and proposed respective time correction schemes, wherein the most representative is "sine wave zero crossing" time correction method, which uses the characteristic that the slope of different sampling units at the sine wave "zero crossing" is not changed, i.e. the ratio of the sampling amplitude difference to the sampling time interval is fixed, and calculates the true sampling interval by measuring the amplitude difference, and the schematic diagram of the principle is shown in fig. 2. The method can be expressed simply as follows:
Figure GDA0002280500130000011
Figure GDA0002280500130000021
Figure GDA0002280500130000022
where N is the number of sampling units, Δ VnAnd Δ tnRespectively, the amplitude interval and the time interval between the nth sampling unit and the (n + 1) th sampling unit, and the zero point is positioned between the nth sampling unit and the (n + 1) th sampling unit, TclcIs the period of the Delay-chain phase-Locked Loop (DLL) input reference clock, and p is the sine wave slope at zero.
The method has a certain effect of improving the time measurement precision, but the method is easily influenced by the gain deviation and the bandwidth of each sampling unit, and the formula (1) is not strictly established, so that a certain deviation still exists between the obtained sampling interval and the real sampling interval, and the method has a limited improvement on the time measurement precision, and the effect is not obvious enough when the method is particularly applied to chips with lower bandwidth and larger gain deviation of each sampling unit.
Disclosure of Invention
The invention aims to provide a time correction method for a switched capacitor array chip, which is used for calculating and obtaining the real sampling interval between each sampling unit in an SCA chip and correcting the time measurement result by using the sampling interval. The key point of the invention is the construction of an over-determined linear equation set, which is theoretically insusceptible to the inconsistency of the bandwidth and the gain of each sampling unit.
The purpose of the invention is realized by the following technical scheme:
a time correction method for a switched capacitor array chip, comprising:
inputting a sine wave with known frequency as an input signal to a switched capacitor array chip, and calculating the zero crossing time of the sine wave sampled by the switched capacitor array chip;
establishing an equation by utilizing the relation between the time interval of two adjacent zero-crossing point times and the period of an input signal;
establishing an overdetermined linear equation set by using enough equations, and solving to obtain the actual sampling interval of the switched capacitor array chip;
the time measurement is corrected using the actual sampling interval.
Compared with the traditional 'sine wave zero-crossing' time correction method, the method provided by the invention has the advantages that although the final sampling interval calculation is finished by measuring the amplitude difference of the sampling points at two sides of the zero point, the difference is that the amplitude difference in the method does not directly participate in the final calculation, but is used for obtaining a voltage ratio as the coefficient of a variable in an equation. Although the bandwidth and gain deviation can affect the voltage amplitude value, the bandwidth and gain deviation can not affect the voltage ratio value, so the method can perfectly restore the real sampling interval theoretically. Compared with the traditional sine wave zero-crossing time correction method, the method is more accurate and stable, and the application range is wider.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of an SCA chip structure according to the background art of the present invention;
FIG. 2 is a schematic diagram of the conventional "sine wave zero crossing" time correction method provided in the background of the present invention;
FIG. 3 is a flowchart of a time correction method for a switched capacitor array chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a method for time correction of a switched capacitor array chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an actual sampling interval provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of a time measurement principle provided by an embodiment of the present invention;
FIG. 7 is a distribution graph of 3000 time measurements provided by an embodiment of the present invention; wherein, (a) is a time measurement result without time correction; (b) is a time measurement corrected by time.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a time correction method for a switched capacitor array chip, which comprises the following processes: inputting sine waves with known frequency to an SCA chip, carrying out necessary amplitude correction on waveforms obtained by sampling, firstly calculating time values corresponding to each zero crossing point by using a linear difference method, then expressing the time interval between two adjacent zero crossing points on the same rising edge (or the same falling edge) in a linear addition mode by using each sampling interval, and establishing an equation by using the relationship between the time interval between the two adjacent zero crossing points and the period of an input signal. Repeating the above process for enough times to obtain an overdetermined linear equation set, solving the equation set by using a least square method, wherein the solution of the equation set is a real sampling interval, and then applying the sampling interval to a time measurement result. The innovation point of the scheme is that an overdetermined linear equation set is constructed and solved by utilizing the relation between the sampling signal period and the sampling interval so as to obtain the actual sampling interval of the switched capacitor array chip, and the time measurement result is corrected by utilizing the sampling interval. The method has the characteristics of simple and efficient algorithm, high precision and the like, and the calculation result is not limited by the analog bandwidth of the chip and the gain deviation of each sampling unit; the method can be applied to the field of high-precision time measurement based on the switched capacitor array chip, including flight time detection systems in high-energy physical experiments, neutron measurement, PET instruments in the field of medical imaging and the like.
The flow of the time correction method for the switched capacitor array chip according to the embodiment of the present invention is shown in fig. 3, and mainly includes the following steps:
step 1, inputting a sine wave with a known frequency as an input signal to a switched capacitor array chip, and calculating the zero crossing time of the sine wave sampled by the switched capacitor array chip.
In the embodiment of the invention, a signal generator is used for generating a sine wave with a known frequency as an input signal; and sampling the input signal by using a switched capacitor array chip, performing amplitude correction on the sine waveform obtained by sampling, and calculating the zero crossing time by using a linear difference method.
For example, a SCA waveform digitizing chip with a maximum sampling rate of 5.2Gsps, which is independently designed by nuclear detection and nuclear electronics national emphasis laboratories, and which has 256 sampling units in a single channel, can be used, and the signal generator used is the RoHDE & SCHWARZ RF signal generator ROHDE & SCHWARZ SMA 100A. The method comprises the steps of generating a sine wave with a signal frequency of 139MHz by using a signal generator as an input signal, sampling the input signal by using an SCA chip, and performing necessary amplitude correction on a waveform obtained by sampling, wherein the amplitude correction comprises the steps of converting a quantized code value into an amplitude value and correcting the inherent direct current deviation of each sampling unit.
In the sampled waveform, there are sampling points on both sides of the zero point of the waveform, such as the sampling points 54 and 55, 92 and 93 in fig. 4, and the time values of the "zero-crossing" points a and b can be calculated by a linear difference method using these special sampling points.
And 2, establishing an equation by utilizing the relation between the time interval of two adjacent zero-crossing time and the period of the input signal.
In the embodiment of the present invention, it is assumed that: the zero crossing point a is at the sampling point n1And n1+1, with the zero crossing b at sample point n2And n2+ 1;
the time interval Δ t between two adjacent zero crossings a and ba,bExpressed as:
Figure GDA0002280500130000041
wherein, Δ tiRepresents the sampling time interval between sample point i and sample point i +1, then
Figure GDA0002280500130000042
Corresponds to a sampling point n1And n1+1, sample point n2And n2The sampling time interval between +1, α and β are both coefficients:
Figure GDA0002280500130000051
wherein, VDCRepresents the dc value of the input sine wave;
Figure GDA0002280500130000052
corresponds to a sampling point n1+1, sample point n2The voltage value of (d);
Figure GDA0002280500130000053
corresponds to a sampling point n1And n1+1, sample point n2And n2A voltage difference between + 1;
and a time interval Δ ta,bEqual to the period T of the known input signalSThus, the following equation is established:
Figure GDA0002280500130000054
for ease of understanding, the above process is described below with reference to the example shown in fig. 4. Time interval delta t between two adjacent zero-crossing points a and b in fig. 4a,bIt can be expressed in the form of a linear addition of all the sampling intervals between sample point 54 and sample point 93:
Figure GDA0002280500130000055
wherein, Δ tiRepresenting the sampling time interval between sample point i and sample point i +1, then Δ t54、Δt92Corresponding to the sample time interval between samples 54 and 55 and between samples 92 and 93, α and β are coefficients:
Figure GDA0002280500130000056
wherein, VDCRepresents the dc value of the input sine wave; v55、V92Corresponding to the voltage values at sample point 55 and sample point 92; Δ V54、ΔV92Corresponding to the difference in voltage between sample points 54 and 55 and between sample points 92 and 93.
The time interval between the zero-crossing points a and b is equal to the period T of the known input signalSThus, the following equation is established:
Figure GDA0002280500130000057
and 3, establishing an overdetermined linear equation set by using enough equations, and solving to obtain the actual sampling interval of the switched capacitor array chip.
Sufficient equations can be obtained through the preceding steps to establish an overdetermined system of linear equations. In the embodiment of the invention, 3000 equations are obtained, an over-determined linear equation set is established according to the 3000 equations, and the equation set is expressed in a matrix equation form as follows:
Figure GDA0002280500130000061
wherein M represents the number of equations, and N represents the number of sampling units. If the SCA waveform digitizing chip mentioned in step 1 is adopted, the number of sampling units (i.e., sampling points) is 256, so the size of the equation coefficient matrix is 3000 × 256.
And then, solving an overdetermined linear equation set by using a least square method, wherein the solution of the overdetermined linear equation set is the actual sampling interval of the switched capacitor array chip.
As shown in fig. 5, the average of the finally obtained sampling intervals provided by the embodiment of the present invention is 0.192ns, which corresponds to a sampling frequency of 5.2 Gsps.
And 4, correcting the time measurement result by utilizing the actual sampling interval.
There are various ways to measure time using the SCA chip, and the method used in this example is as follows:
a narrow pulse waveform with the rising edge and the falling edge of 1.0ns is generated by an arbitrary waveform signal generator Keysight 81160A, the waveform is divided into two parts by a power divider, and the two divided waveforms are accessed into two sampling channels of a chip through two cables with different lengths for sampling. Firstly, amplitude calibration is carried out on the sampled signals, and then the time of each sampling point is corrected by using the actual sampling interval obtained by calculation in the step 4. And then respectively carrying out polynomial fitting on the leading edges of the two corrected waveforms, setting a voltage threshold value of 400mV, and respectively calculating time values of overvoltage threshold value points, wherein two threshold crossing time intervals are signal delay time, and a schematic diagram of the principle is shown in FIG. 6. Repeating the process 3000 times, a statistical result can be obtained, the average value of the measurement result is 3.36ns, the average value is the actual delay value of the two channel signals, and the root mean square value can represent the time measurement precision. Compared with the result of no time correction, as shown in fig. 7, it can be seen that the time measurement accuracy is improved from 27.7ps to 7.8ps by the sampling interval correction, and the effect is significant.
Compared with the traditional 'sine wave zero-crossing' time correction method, the scheme provided by the embodiment of the invention completes the final sampling interval calculation by measuring the amplitude difference of the sampling points at two sides of the zero point, but has the difference that the amplitude difference in the method does not directly participate in the final calculation, but is used for obtaining a voltage ratio as the coefficient of a variable in an equation. Although the bandwidth and gain deviation can affect the voltage amplitude value, the bandwidth and gain deviation can not affect the voltage ratio value, so the method can perfectly restore the real sampling interval theoretically. Compared with the traditional sine wave zero-crossing time correction method, the method is more accurate and stable, and has wider application range
Through the above description of the embodiments, it is clear to those skilled in the art that the above embodiments can be implemented by software, and can also be implemented by software plus a necessary general hardware platform. With this understanding, the technical solutions of the embodiments can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (3)

1. A time correction method for a switched capacitor array chip, comprising:
inputting a sine wave with known frequency as an input signal to a switched capacitor array chip, and calculating the zero crossing time of the sine wave sampled by the switched capacitor array chip;
establishing an equation by utilizing the relation between the time interval of two adjacent zero-crossing point times and the period of an input signal;
establishing an overdetermined linear equation set by using equations with the number exceeding the unknown number in the equations, and solving to obtain the actual sampling interval of the switched capacitor array chip;
correcting the time measurement result by using the actual sampling interval;
wherein, the establishing an equation by using the relationship between the time interval of two adjacent zero-crossing time and the period of the input signal comprises:
suppose that: the zero crossing point a is at the sampling point n1And n1+1, with the zero crossing b at sample point n2And n2+ 1;
the time interval Δ t between two adjacent zero crossings a and ba,bExpressed as:
Figure FDA0002280500120000011
wherein, Δ tiRepresents the sampling time interval between sample point i and sample point i +1, then
Figure FDA0002280500120000012
Corresponds to a sampling point n1And n1+1, sample point n2And n2The sampling time interval between +1, α and β are both coefficients:
Figure FDA0002280500120000013
wherein, VDCRepresents the dc value of the input sine wave;
Figure FDA0002280500120000014
corresponds to a sampling point n1+1, sample point n2The voltage value of (d);
Figure FDA0002280500120000015
corresponds to a sampling point n1And n1+1 ofInterval and sampling point n2And n2A voltage difference between + 1;
and a time interval Δ ta,bEqual to the period T of the known input signalSThus, the following equation is established:
Figure FDA0002280500120000016
2. the method of claim 1, wherein a sine wave with a known frequency is input to the switched capacitor array chip as an input signal, and calculating the zero-crossing time of the sine wave sampled by the switched capacitor array chip comprises:
generating a sine wave of a known frequency as an input signal by using a signal generator;
the method comprises the steps of sampling an input signal by using a switched capacitor array chip, carrying out amplitude correction on a sine waveform obtained by sampling, and calculating zero crossing point time by using a linear difference method.
3. The method of claim 1, wherein the overdetermined linear equations are solved by a least square method, and the solutions of the overdetermined linear equations are actual sampling intervals of the switched capacitor array chip.
CN201810135454.8A 2018-02-09 2018-02-09 A Time Correction Method for Switched Capacitor Array Chip Active CN108333912B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810135454.8A CN108333912B (en) 2018-02-09 2018-02-09 A Time Correction Method for Switched Capacitor Array Chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810135454.8A CN108333912B (en) 2018-02-09 2018-02-09 A Time Correction Method for Switched Capacitor Array Chip

Publications (2)

Publication Number Publication Date
CN108333912A CN108333912A (en) 2018-07-27
CN108333912B true CN108333912B (en) 2020-03-31

Family

ID=62927452

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810135454.8A Active CN108333912B (en) 2018-02-09 2018-02-09 A Time Correction Method for Switched Capacitor Array Chip

Country Status (1)

Country Link
CN (1) CN108333912B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111367158B (en) * 2018-12-26 2021-04-23 中国科学技术大学 Waveform digital time measurement method and system based on SCA
CN114265300B (en) * 2021-12-30 2022-12-30 中国科学技术大学 Time correction method for switched capacitor array chip
CN116760846B (en) * 2023-08-21 2023-11-14 国网山东省电力公司日照供电公司 Double-end fault recording data synchronization method and system based on first zero crossing point identification

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101952895A (en) * 2007-10-01 2011-01-19 保罗·谢勒学院 Fast Readout Method and Switched Capacitor Array Circuit for Waveform Digitization
CN103762975A (en) * 2014-01-17 2014-04-30 中国科学院上海技术物理研究所 Time frequency synchronization calibration method of SCA-based multi-channel high-speed acquisition system
WO2015051824A1 (en) * 2013-10-08 2015-04-16 Eberhard Karls Universitaet Tuebingen Medizinische Fakultaet Method for the temporal calibration of a switched capacitor array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101952895A (en) * 2007-10-01 2011-01-19 保罗·谢勒学院 Fast Readout Method and Switched Capacitor Array Circuit for Waveform Digitization
WO2015051824A1 (en) * 2013-10-08 2015-04-16 Eberhard Karls Universitaet Tuebingen Medizinische Fakultaet Method for the temporal calibration of a switched capacitor array
CN103762975A (en) * 2014-01-17 2014-04-30 中国科学院上海技术物理研究所 Time frequency synchronization calibration method of SCA-based multi-channel high-speed acquisition system

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
A Correlation-based Timing Calibration and Diagnostic Technique for Fast Digitizing ASICs;Nishimura K 等;《Physics Procedia》;20121231(第37期);1707-1714 *
a new time calibration method for switched-capacitor-array based waveform samplers;Kim H 等;《Nuclear Instruments and Methods in Physics Research Section A》;20141231(第767期);67-74 *
evaluation of a fast pulse sampling module with switched capacitor arrays;Wang J 等;《IEEE transactions on nuclear science》;20121231;第59卷(第5期);2435-2443 *
Novel calibration method for switched capacitor arrays enables time measurements with sub-picosecond resolution;Stricker-shaver D 等;《IEEE transactions of nuclear science》;20141231;第61卷(第6期);3607-3617 *
基于先进ASIC芯片的多探测单元信号读出方法与电路设计;杨海波;《中国博士学位论文全文数据库》;20151015(第10期);64-89 *
基于开关电容矩阵的波形数字化技术研究;王进红;《中国博士学位论文全文数据库》;20121231;92-100 *
基于开关电容阵列ASIC芯片的多通道波形数字化系统设计;鲁一鸣 等;《原子核物理评论》;20171231;第34卷(第4期);755-761 *

Also Published As

Publication number Publication date
CN108333912A (en) 2018-07-27

Similar Documents

Publication Publication Date Title
Wang et al. A 3.0-ps rms precision 277-MSamples/s throughput time-to-digital converter using multi-edge encoding scheme in a Kintex-7 FPGA
Bardelli et al. Time measurements by means of digital sampling techniques: a study case of 100ps FWHM time resolution with a 100MSample/s, 12bit digitizer
JP6473509B2 (en) Scintillation pulse digitization method
Stricker-Shaver et al. Novel calibration method for switched capacitor arrays enables time measurements with sub-picosecond resolution
CN103961126B (en) A kind of threshold correction method of multi thresholds sampling digitizing device
CN108333912B (en) A Time Correction Method for Switched Capacitor Array Chip
US10416295B2 (en) Interpolation measurement of the arrival time and/or amplitude of a digitized electronic pulse
Perktold et al. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution
Qin et al. Design and performance of a 16-channel coarse-fine TDC prototype ASIC
CN105807128A (en) Method and system for measuring alternating voltages by applying multicycle strategy to digital-to-analogue conversion
Cheng et al. An overdetermined linear equations-based time calibration method for fast sampling ASICs
CN117235436B (en) Pulse digitization method, correction method, device, electronic equipment and storage medium
CN110954938B (en) Threshold correction method and device of comparator and sampling circuit
CN114265300B (en) Time correction method for switched capacitor array chip
Jokhovets et al. Improved rise approximation method for pulse arrival timing
Deng et al. Readout electronics of t0 detector in the external target experiment of CSR in HIRFL
Fan et al. Research and verification on real-time interpolated timing algorithm based on waveform digitization
Delagnes What is the theoretical time precision achievable using a dCFD algorithm?
Ferry et al. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing
Chen et al. Testing of SCA waveform digitization ASIC for high-precision time measurement
Župunski et al. On-line determination of the measurement uncertainty of the stochastic measurement method
Paraliev et al. Comparison of high resolution “balanced” and “direct conversion” measurement of SwissFEL resonant kicker amplitude
Joly et al. Sampling rate and ADC resolution requirements in digital front-end electronics for TOF PET
RU2591742C1 (en) Method of measuring frequency of harmonic signal and device therefor
Koike et al. A digital divider with extension bits for position-sensitive detectors

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant