CN108400116B - A method of manufacturing a semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate on which an interlayer dielectric layer is formed, and a gate trench is formed in the interlayer dielectric layer ; Form a high-k dielectric layer and a protective layer in turn on the bottom and sidewalls of the gate trench and on the surface of the interlayer dielectric layer; remove the protective layer on the surface of the interlayer dielectric layer the upper part; removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer; performing a first annealing process; and removing the protective layer. The method of the present invention can avoid the problem of excessive stress caused by the difference in thermal expansion coefficients between multiple film layers during the first annealing treatment, thereby avoiding the formation of crack defects in films such as high-k dielectric layers, ensuring that The isolation performance of the device, thereby improving the leakage current of the gate, and improving the performance and yield of the device.

Description

A method of manufacturing a semiconductor device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor device.

Background technique

With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits.

For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices can use Ge channels, while NMOS devices can use III-V compound semiconductors (such as InGaAs) as the channel to increase the carrier mobility. Due to the continuous shrinking of technology nodes, the application of a high-k dielectric layer can increase the physical thickness of the gate dielectric layer film while keeping the gate capacitance unchanged, thereby reducing the leakage current of the gate dielectric layer and improving the reliability of the device. In addition, in order to improve the interface characteristics between the high-k dielectric layer and the substrate, an interface layer (IL) is usually formed between the high-k dielectric layer and the substrate. The quality of the interface layer and the high-k dielectric is good. failure has a great impact on the performance of the device.

Currently, PCA annealing is commonly used to improve the quality of high-k dielectric layers and interfacial layers. An annealing process is performed, followed by removal of the protective layer; another method of post-deposition annealing (PDA) is also typically used to improve the quality of the high-k dielectric layer. However, the above annealing process can lead to stress caused by different thermal expansion coefficients, such as spacer silicon nitride (SiN), high-k dielectric layer, capping layer TiN on high-k dielectric layer and post-deposited silicon nitride on capping layer TiN Protective layer (for example, amorphous silicon) These films have different thermal expansion coefficients due to different materials used. The difference in thermal expansion coefficients causes stress between the films during the annealing process. Once the stress is too large, all the films Both may crack to produce crack defects, thereby degrading the isolation performance, resulting in high gate leakage, poor isolation performance of the contact (CT) electrically connected to the gate, and the like.

In view of the existence of the above-mentioned technical problems, it is necessary to propose a new method for manufacturing a semiconductor device.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In view of the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, an interlayer dielectric layer is formed on the semiconductor substrate, and a gate trench is formed in the interlayer dielectric layer;

forming a high-k dielectric layer and a protective layer in sequence on the bottom and sidewalls of the gate trench and on the surface of the interlayer dielectric layer;

removing the portion of the protective layer above the surface of the interlayer dielectric layer;

removing the portion of the high-k dielectric layer above the surface of the interlayer dielectric layer;

performing a first annealing treatment;

The protective layer is removed.

Further, after forming the high-k dielectric layer and before forming the protective layer, a step of forming a capping layer on the surface of the high-k dielectric layer is further included.

Further, the step of removing the portion of the protective layer above the surface of the interlayer dielectric layer includes the following steps:

forming a sacrificial material layer to fill the gate trench and cover the protective layer above the surface of the interlayer dielectric layer;

planarizing the sacrificial material layer until the protective layer is exposed;

A portion of the protective layer above the surface of the interlayer dielectric layer is removed.

Further, after the step of removing the high-k dielectric layer located above the surface of the interlayer dielectric layer, and before the step of the first annealing treatment, a step of removing the sacrificial material layer is further included.

Further, the temperature range of the first annealing treatment is 900°C to 1100°C.

Further, the material of the protective layer includes amorphous silicon.

Further, the thickness of the protective layer ranges from 40 angstroms to 120 angstroms.

Further, the material of the sacrificial material layer includes at least one of an organic distribution layer, a bottom anti-reflection coating and a photoresist.

Further, before forming the high-k dielectric layer, spacers are formed on sidewalls of the gate trenches.

Further, the sacrificial material layer is removed by wet etching using an etchant including tetramethylammonium hydroxide or ammonium hydroxide.

Further, when the sacrificial material layer is removed, the temperature of the etchant ranges from 25°C to 75°C.

Further, after forming the high-k dielectric layer and before forming the protective layer, the method further includes: performing a second annealing on the high-k dielectric layer.

According to the manufacturing method of the present invention, before performing the first annealing treatment, the portion of the protective layer located above the surface of the interlayer dielectric layer is removed, and the high-k dielectric layer located on the interlayer dielectric layer is removed The part above the surface can avoid the problem of excessive stress due to the difference in thermal expansion coefficient between multiple layers during the first annealing process, thereby avoiding the formation of crack defects in layers such as high-k dielectric layers, The isolation performance of the device is guaranteed, thereby improving the leakage current of the gate, and improving the performance and yield of the device.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

1A to FIG. 1I are schematic structural diagrams of a device obtained by related steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

For a thorough understanding of the present invention, detailed steps will be presented in the following description in order to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

In order to solve the aforementioned technical problems and improve the performance of the device, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in FIG. 2 , the method mainly includes:

Step S1, providing a semiconductor substrate, an interlayer dielectric layer is formed on the semiconductor substrate, and a gate trench is formed in the interlayer dielectric layer;

Step S2, forming a high-k dielectric layer and a protective layer in sequence on the bottom and sidewalls of the gate trench and on the surface of the interlayer dielectric layer;

Step S3, removing the part of the protective layer above the surface of the interlayer dielectric layer;

Step S4, removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer;

Step S5, performing a first annealing treatment;

Step S6, removing the protective layer.

According to the manufacturing method of the present invention, before performing the first annealing treatment, the portion of the protective layer located above the surface of the interlayer dielectric layer is removed, and the high-k dielectric layer located on the interlayer dielectric layer is removed The part above the surface can avoid the problem of excessive stress due to the difference in thermal expansion coefficient between multiple layers during the first annealing process, thereby avoiding the formation of crack defects in layers such as high-k dielectric layers, The isolation performance of the device is guaranteed, thereby improving the leakage current of the gate, and improving the performance and yield of the device.

Specifically, the method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to FIGS. 1A to 1I , wherein FIGS. 1A to 1I show a device obtained by related steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention. Schematic diagram of the structure.

First, step 1 is performed to provide a semiconductor substrate, an interlayer dielectric layer is formed on the semiconductor substrate, and a gate trench is formed in the interlayer dielectric layer.

Specifically, as shown in FIG. 1A , the semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), germanium-on-insulator Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

In one example, the semiconductor substrate includes an NMOS device region and a PMOS device region, wherein a gate trench 1021 is formed in the NMOS device region, and a gate trench 1022 is formed in the PMOS device region .

Exemplarily, the channel material under the gate trench in the NMOS device region may include a III-V group compound semiconductor, for example, a III-V group binary or ternary compound semiconductor. In this embodiment, the The III-V compound semiconductor is InGaAs, and the channel material under the gate trench in the PMOS device region includes an elemental semiconductor, wherein the elemental semiconductor material can be any used elemental semiconductor known to those skilled in the art, including but It is not limited to Ge or Si, or the channel material under the gate trench in the PMOS device region includes SiGe. In this embodiment, the element semiconductor is Ge, and the III-V compound semiconductor is used as the channel of the NMOS device. The use of elemental semiconductors as the channel of the PMOS device can improve the carrier mobility. Exemplarily, the common Si semiconductor material can also be used as the channel material in the NMOS device region and the PMOS device region.

It is worth mentioning that elemental semiconductors refer to semiconductors composed of a single element.

Exemplarily, the semiconductor device of the present invention is a FinFET device, then a first fin structure is formed on the semiconductor substrate in the NMOS device region, and a first fin structure is formed on the semiconductor substrate in each of the PMOS device regions. In the second fin structure, the gate trench 1021 exposes part of the surface of the first fin structure, and the gate trench 1022 exposes part of the surface of the second fin structure.

In one example, taking a FinFET device as an example, in order to obtain the structure shown in Figure 1A, the following steps A1 to A5 may be performed:

In one example, to obtain the structure shown in Figure 1A, the following process steps may be performed:

First, step A1 is performed to form a plurality of fin structures on a semiconductor substrate. For example, a first fin structure and a third fin structure are respectively formed in the NMOS device region and the PMOS device region on the semiconductor substrate. In a two-fin structure, the widths of the fin structures are all the same, or the fins are divided into a plurality of fin structure groups with different widths, and the lengths of the fin structures can also be different.

Specifically, the formation method of the fin structure is not limited to a certain one, and an exemplary formation method is given below: forming a hard mask layer (not shown in the figure) on a semiconductor substrate, forming the The hard mask layer can adopt various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process, and the hard mask layer can be an oxide layer and a silicon nitride layer stacked from bottom to top; pattern The hard mask layer is densified to form a plurality of isolated masks for etching the semiconductor substrate to form fins thereon, and in one embodiment, the self-aligned double patterning (SADP) process is used to implement the Patterning process; etching a semiconductor substrate to form fin structures thereon.

Subsequently, step A2 may also be performed to deposit an isolation material layer to cover all the aforementioned fin structures.

Specifically, a layer of isolation material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer can be selected from oxide, such as high aspect ratio process (HARP) oxide, specifically silicon oxide.

The isolation material layer is then etched back to a target height of the fin structure to form an isolation structure with a top surface lower than the top surface of the first fin structure and the second fin structure. Specifically, the isolation material layer is etched back to expose part of the fin structure, thereby forming a fin structure with a specific height.

Next, step A3 is performed to form a first dummy gate structure spanning the first fin structure and a second dummy gate structure spanning the second fin structure, wherein the dummy gate structures both include dummy gate dielectrics electrical layer and dummy gate material layer.

It should be pointed out that the term "span" used in the present invention, such as spanning the dummy gate structure of the fin structure (eg, the first fin structure, the second fin structure, etc.), refers to the fin structure A dummy gate structure is formed on both the upper surface and the side surface of a part of the semiconductor substrate, and the dummy gate structure is also formed on a part of the surface of the semiconductor substrate.

In one example, a dummy gate dielectric layer and a dummy gate material layer may be sequentially deposited on the semiconductor substrate first.

Wherein, the dummy gate dielectric layer can be selected from commonly used oxides, such as SiO ₂ , and the dummy gate material layer can be selected from semiconductor materials commonly used in the field, such as polysilicon, etc., and is not limited to a certain one. , will not be listed one by one here,

The deposition method of the dummy gate material layer may be chemical vapor deposition or atomic layer deposition.

The dummy gate dielectric layer and dummy gate material layer are then patterned to form the first and second dummy gate structures. Specifically, a photoresist layer is formed on the dummy gate material layer, then exposed and developed to form openings, then the dummy gate material layer is etched using the photoresist layer as a mask, and finally the photoresist layer is removed glue layer.

Afterwards, optionally, offset spacers (Spacers) are formed on the sidewalls of the first dummy gate structure and the second dummy gate structure.

Specifically, the offset spacers may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the offset spacers are composed of silicon oxide and silicon nitride. The specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a first silicon nitride layer on a semiconductor substrate. The silicon dioxide layer is then etched to form offset spacers. It is also possible to form a spacer material layer on both the top surface and the sidewall of the dummy gate structure, and in a subsequent step, by a planarization method, such as chemical mechanical polishing, the spacer material layer on the top surface is removed to form only a Offset side wall on side wall.

Optionally, an LDD ion implantation step and activation are performed on both sides of the first dummy gate structure and the second dummy gate structure.

Optionally, spacers 10 are formed on the offset sidewalls of the dummy gate structure.

Specifically, a spacer (Spacer) is formed on the formed offset sidewall, and the spacer may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the spacers are composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer and a second oxide layer on a semiconductor substrate The silicon layer is then etched to form spacers.

Next, step A4 is performed, and source-drain implantation can also be selectively performed, and the source/drain of the NMOS device is formed in the first fin structures on both sides of the aforementioned first dummy gate structure, and the source/drain of the NMOS device is formed in the second dummy gate structure. The source/drain of the PMOS device is formed in the second fin structure on both sides of the pole structure.

It also includes the steps of: growing a stress layer on the source/drain regions on both sides of the first dummy gate structure and the second dummy gate structure, in a CMOS transistor, a stress layer with tensile stress is usually formed on an NMOS transistor, and a stress layer with tensile stress is formed on the PMOS transistor. By forming a stress layer with compressive stress, the performance of the CMOS device can be improved by applying the tensile stress to the NMOS and the compressive stress to the PMOS. In the prior art, SiC is usually selected as the tensile stress layer in NMOS transistors, and SiGe is usually selected as the compressive stress layer in PMOS transistors.

Preferably, when the SiC is grown as a tensile stress layer, epitaxial growth can be performed on the substrate, and a raised source and drain are formed after ion implantation. When the SiGe layer is formed, a recess is usually formed in the substrate. grooves, and then deposit a SiGe layer in the grooves. More preferably, "Σ" shaped grooves are formed in the substrate.

Next, step A5 is performed, an interlayer dielectric layer 101 is deposited and planarized to fill the gaps between the dummy gate structures, and the interlayer dielectric layer 101 covers the entire surface of the semiconductor substrate and the stress layer.

Specifically, an interlayer dielectric layer 101 is deposited and planarized, and the pair of interlayer dielectric layers 101 is planarized to the top of the first dummy gate structure and the second dummy gate structure.

Wherein, the interlayer dielectric layer 101 can be selected from dielectric materials commonly used in the field, such as various oxides, etc. In this embodiment, the interlayer dielectric layer can be selected from SiO ₂ , and its thickness is not limited to a certain a value.

Non-limiting examples of the planarization process include mechanical planarization methods and chemical mechanical polishing planarization methods.

After that, removing the first dummy gate structure and the second dummy gate structure, including sequentially removing the dummy gate dielectric layer and the dummy gate material layer, to form a gate trench 1021 on the semiconductor substrate 100 in the NMOS device region , a gate trench 1022 is formed on the semiconductor substrate 100 in the PMOS device region, and the gate trench in the NMOS device region exposes part of the first fin structure in the extending direction of the first fin structure, The gate trench of the PMOS device region exposes part of the second fin structure in the extending direction of the second fin structure.

Finally, the structure shown in FIG. 1A is formed, wherein an interlayer dielectric layer 101 is formed on the semiconductor substrate 100 , and gate trenches 1021 and gates are formed in the interlayer dielectric layer 101 The trench 1022 and the spacers 10 formed in the preceding steps are located on the sidewalls of the gate trenches.

Next, step 2 is performed to form an interface layer at the bottom of the gate trench.

Specifically, as shown in FIG. 1B , an interface layer 103 is formed at the bottom of the gate trench. Exemplarily, the interface layer 103 is formed at the bottom of the gate trench 1022 of the PMOS device region and the gate trench 1021 of the NMOS device region, and the function of forming the interface layer (IL) 103 is to improve the high Interface properties between the k-dielectric layer and the semiconductor substrate.

The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layers. The interface layer may be formed by a suitable process such as thermal oxidation, chemical oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

In this embodiment, the interface layer 103 may be a chemical oxide layer. For example, a chemical oxidation layer may be formed as the interface layer 103 using a chemical oxidation method of an ozone (Ozone) treatment liquid. Specifically, the material of the interface layer 103 can be determined according to the channel material at the bottom of the gate trench 1022. In this embodiment, the channel of the PMOS device is Ge, and the interface layer 103 is an oxide of germanium, such as GeO ₂ .

The thickness of the interface layer 103 may be reasonably set according to actual process requirements. For example, the thickness of the interface layer 103 may range from 5 angstroms to 10 angstroms.

Next, step 3 is performed to form a high-k dielectric layer on the bottom and sidewalls of the gate trench and on the surface of the interlayer dielectric layer.

Exemplarily, continuing as shown in FIG. 1B , on the bottom and sidewalls of the gate trench 1022 of the PMOS device region and the gate trench 1021 of the NMOS device region and the surface of the interlayer dielectric layer 101 A high-k dielectric layer 104 is formed thereon.

The k value (dielectric constant) of the high-k dielectric layer 104 is generally 3.9 or more, and its constituent materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium oxide silicon, titanium oxide, and tantalum oxide , barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide or aluminum oxide. The high-k dielectric layer 104 may be formed using a suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

Optionally, the thickness of the high-k dielectric layer 104 is in the range of 10 angstroms to 30 angstroms, and can also be other suitable thicknesses.

In one example, after the high-k dielectric layer 104 is formed, an optional step of annealing may be performed.

Optionally, after the high-k dielectric layer 104 is formed, the high-k dielectric layer 104 may also be annealed. The annealing treatment in this step can be any suitable annealing method known to those skilled in the art, such as rapid thermal annealing, furnace tube annealing, spike anneal and the like. For example, atomic layer deposition is used to deposit hafnium oxide as the high-k dielectric layer 104. In order to obtain a pure crystalline structure of hafnium oxide, the high-k dielectric layer needs to be annealed. For example, the annealing temperature ranges from 600°C to 1000°C. , 650 ℃, 700 ℃, 750 ℃, 800 ℃, 850 ℃, 900 ℃, etc., the annealing time is 30s ~ 600s, this annealing treatment is called post deposition annealing (PDA).

Next, step 4 is performed to form a capping layer on the surface of the high-k dielectric layer.

Specifically, as shown in FIG. 1C , a capping layer is formed on the surface of the high-k dielectric layer.

Exemplarily, the capping layer 105 is formed on the surface of the high-k dielectric layer 104 on the bottom and sidewalls of the gate trench, and is further formed on the high-k dielectric layer 101 on the interlayer dielectric layer 101 . on the surface of the dielectric layer 104 .

The material of the capping layer 105 can be La ₂ O ₃ , AL ₂ O ₃ , Ga ₂ O ₃ , In ₂ O ₃ , MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN, TixN1-x or other suitable film layer. In this embodiment, the material of the cover layer 105 is TiN. The capping layer 105 may be formed by a suitable process such as CVD, ALD or PVD.

The thickness of the cover layer 105 ranges from 0 angstroms to 20 angstroms, and may also be other suitable thicknesses.

Next, step 5 is performed to form a protective layer on the surface of the cover layer.

Exemplarily, as shown in FIG. 1C , the protective layer 106 is formed on the surface of the capping layer 105 on the bottom and sidewalls of the gate trench, and is further formed on the interlayer dielectric layer 101 . on the surface of the cover layer 105 .

In one example, the protective layer 106 may be formed directly on the surface of the high-k dielectric layer without forming the capping layer first.

Further, the material of the protective layer 106 is an amorphous semiconductor material. Wherein, the amorphous semiconductor material includes amorphous silicon (a-Si) or amorphous germanium (a-Ge), and may also be other suitable amorphous semiconductor materials.

Methods of forming sacrificial layers include chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and also Generally similar methods such as sputtering and physical vapor deposition (PVD) can be used.

Wherein, the thickness of the formed protective layer 106 ranges from 40 angstroms to 120 angstroms, and may also be other suitable thicknesses.

Next, step 5 is performed to remove the portion of the protective layer above the surface of the interlayer dielectric layer.

In one example, the step of removing the portion of the protective layer over the surface of the interlayer dielectric layer includes the steps of:

First, as shown in FIG. 1D , a sacrificial material layer 107 is formed to fill the gate trench and cover the protective layer 106 over the surface of the interlayer dielectric layer 101 . Exemplarily, the sacrificial material layer 107 fills the gate trenches of the PMOS device region and the gate trenches of the NMOS device region.

Optionally, the sacrificial material layer 107 can be any suitable material, including but not limited to at least one of an organic distribution layer (ODL), a bottom anti-reflective coating (BARC) and a photoresist species, or other suitable materials.

The sacrificial material layer 107 may be formed by spin coating or chemical vapor deposition.

Next, as shown in FIG. 1E , the sacrificial material layer 107 is planarized until the protective layer 106 is exposed, so that the top surface of the protective layer above the surface of the interlayer dielectric layer and the top surface of the sacrificial material layer are Flush, ie, planarization, stops on the top surface of the protective layer.

The planarization of the surface can be accomplished using conventional planarization methods in the field of semiconductor fabrication. Non-limiting examples of such planarization methods include mechanical planarization methods and chemical mechanical polishing (CMP) planarization methods. Among them, the chemical mechanical polishing planarization method is preferably used.

Among them, the introduced sacrificial material layer can protect the film layer formed in the gate trench in the subsequent multi-step etching process, and can avoid using the mask multiple times in the subsequent etching, and make the process complication and increased cost.

Subsequently, as shown in FIG. 1F , the portion of the protective layer 106 located above the surface of the interlayer dielectric layer 101 is removed.

The protective layer 106 and a portion of the sacrificial material layer 107 may be etched simultaneously using any suitable etching method to remove the portion of the protective layer 106 above the surface of the interlayer dielectric layer 101, for example , when a cover layer is formed under the protection layer, the protection layer is etched until the top surface of the cover layer is exposed, so that the top surface of the remaining sacrificial material layer 107 and the exposed top surface of the cover layer 105 are flush.

Exemplarily, dry etching or wet etching can be used to perform the etching in this step, wherein the dry etching can be reactive ion etching, ion beam etching, plasma etching, and laser ablation. Or any combination of these methods. A single etching method may also be used, or more than one etching method may be used.

The etching method employs an etching method with a high etching rate for the sacrificial material layer and the protective layer, and a low etching rate for the capping layer.

Next, step 6 is performed to remove the part of the high-k dielectric layer above the surface of the interlayer dielectric layer.

In one example, as shown in FIG. 1G , the portion of the capping layer 105 and the high-k dielectric layer 104 located above the surface of the interlayer dielectric layer 101 is removed, and the remaining capping layer 105 is removed. The top surface, the remaining top surface of the high-k dielectric layer 104 and the top surface of the interlayer dielectric layer 101 are flush with the top surface of the protective layer 106 and the top surface of the sacrificial material layer 107 top.

Among them, it is possible to use a high etch rate for the capping layer 105 and the high-k dielectric layer 104, and a low etching rate for the protective layer 106, the sacrificial material layer 107 and the interlayer dielectric layer. The cover layer 105 and the high-k dielectric layer 104 are etched by an etching method with a high etching rate, so as to sequentially remove the cover layer 105 and the high-k dielectric layer 104 located in the interlayer The portion above the surface of the electrical layer 101 exposes the top surface of the interlayer dielectric layer.

Exemplarily, dry etching or wet etching can be used to perform the etching in this step, wherein the dry etching can be reactive ion etching, ion beam etching, plasma etching, and laser ablation. Or any combination of these methods. A single etching method may also be used, or more than one etching method may be used.

Next, step 7 is performed to remove the sacrificial material layer.

As shown in FIG. 1H , the sacrificial material layer can be removed using any suitable method known to those skilled in the art, specifically, a suitable removal method can be selected according to the material of the sacrificial material layer used, including but not limited to wet etching The method of etching or dry etching, preferably, can use a sacrificial material layer with a high etch rate, and the interlayer dielectric layer, spacer, high-k dielectric layer, capping layer and protective layer. The sacrificial material layer is removed by a wet etch method of an etch rate.

In one example, when the material of the sacrificial material layer is photoresist, the sacrificial material layer may also be removed by an ashing method.

Next, step 8 is performed to perform annealing treatment.

Specifically, with continued reference to FIG. 1H , the device is subjected to annealing treatment, and the effect of the annealing treatment is to improve the quality of film layers such as the high-k dielectric layer and the interface layer.

Optionally, the temperature of the annealing treatment ranges from 900°C to 1100°C, and may also be other suitable temperatures.

The annealing treatment may use any suitable annealing method, such as furnace tube annealing, spike anneal, laser anneal, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light sources (such as halogen lamps, arc lamps, graphite heating) rapid annealing. In this embodiment, preferably, peak annealing or laser annealing is used for the annealing treatment.

In the annealing process of this step, since the high-k dielectric layer, cover layer, protective layer and other film layers covering the surface of the interlayer dielectric layer are removed, during the annealing process, it can be The stress generated between the film layers is well released, avoiding excessive stress and causing crack defects in all film layers such as spacers, high-k dielectric layers, cover layers and protective layers, thereby ensuring isolation performance.

Then, step 9 is performed to remove the protective layer.

Specifically, as shown in FIG. 1I, the protective layer may be removed by any suitable method known to those skilled in the art, including but not limited to dry etching or wet etching.

In one example, the material of the protective layer includes amorphous silicon, and the sacrificial material layer may be removed by wet etching using an etchant including tetramethylammonium hydroxide or ammonium hydroxide.

Exemplarily, when removing the protective layer, the temperature of the etchant ranges from 25°C to 75°C.

Finally, a conventional metal gate structure process is performed, in one example, process steps B1 to B5 are performed:

Step B1, forming a first diffusion barrier layer on the bottom and sidewalls of the gate trenches in the NMOS device region and the PMOS device region;

Specifically, the first diffusion barrier layer can also be selectively provided, and the material of the first diffusion barrier layer 106 can be selected from, but not limited to, TaN, Ta, TaAl or other suitable thin film layers. In this embodiment, TaN is used as the material of the first diffusion barrier layer. The first diffusion barrier layer 106 may be formed by a suitable process such as CVD, ALD or PVD. The thickness of the first diffusion barrier layer 106 ranges from 0 angstroms to 20 angstroms.

Further, the first diffusion barrier layer is located on the surface of the cover layer.

Step B2, a P-type work function layer is formed on the bottom and sidewalls of the gate trench in the PMOS device region, and the P-type work function layer is located on the surface of the first diffusion barrier layer.

Specifically, the material of the P-type work function layer can be selected from, but not limited to, TixN1-x, TaC, MoN, TaN or a combination thereof or other suitable thin film layers. In this embodiment, the P-type work function layer is selected from TiN. The P-type work function layer 107 may be formed by a suitable process such as CVD, ALD or PVD. The thickness of the P-type work function layer ranges from 10 angstroms to 580 angstroms, but is not limited to this numerical range.

Step B3, an N-type work function layer is formed on the bottom and sidewalls of the gate trenches in the NMOS device region and the PMOS device region, wherein the N-type work function layer is located in the NMOS device region. On the surface of the first diffusion barrier layer, the N-type work function layer of the PMOS device region is located on the surface of the P-type work function layer.

The material of the N-type work function layer can be selected as, but not limited to, TaAlC, TaC, Ti, Al, TixAl1-x or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The N-type work function layer can be formed by a suitable process such as CVD, ALD or PVD. The thickness of the N-type work function layer may range from 10 angstroms to 80 angstroms.

Step B4, forming a second diffusion barrier layer on the bottom and sidewalls of the gate trenches in the NMOS device region and the PMOS device region, where the second diffusion barrier layer is located on the N-type work function layer on the surface.

The second diffusion barrier layer can also be selectively provided, and the material of the second diffusion barrier layer can be selected from, but not limited to, TaN, Ta, TaAl or other suitable thin film layers.

After the above-mentioned film layers are formed, a planarization process, such as chemical mechanical polishing, etc., may also be performed on the surface of the interlayer dielectric layer 101 to remove excess film layers on the surface of the interlayer dielectric layer 101 .

In step B5, a gate electrode layer is filled in the gate trenches of the NMOS device region and the PMOS device region, so as to finally form a metal gate structure in both the NMOS device region and the PMOS device region.

The gate electrode layer fills the gate trenches, and the material of the gate electrode layer can be selected from, but not limited to, Al, W or other suitable thin film layers. The gate electrode layer may be formed by a suitable process such as CVD, ALD or PVD.

In one example, a gate electrode layer may be deposited to fill the gate trenches and cover the surface of the interlayer dielectric layer, and then a planarization process, such as chemical mechanical polishing, may be performed, stopping on the surface of the interlayer dielectric layer.

The detailed description of the manufacturing method of the semiconductor device of the present invention has been completed so far, and other process steps may be required for the manufacture of a complete device, which will not be repeated here.

To sum up, according to the manufacturing method of the present invention, before performing the first annealing treatment, the portion of the protective layer located above the surface of the interlayer dielectric layer is removed, and the high-k dielectric layer and the interlayer dielectric layer are removed. The part of the cover layer located above the surface of the interlayer dielectric layer can avoid the problem of excessive stress caused by the difference in the thermal expansion coefficients between the plurality of film layers during the first annealing process, so as to avoid the problem of excessive stress in the high-k dielectric layer. Crack defects are formed in the film layers such as the electrical layer, the cover layer and the protective layer to ensure the isolation performance of the device, thereby improving the leakage current of the gate, and improving the performance and yield of the device.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (12)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer;

sequentially forming a high-k dielectric layer and a protective layer on the bottom and the side wall of the gate trench and the surface of the interlayer dielectric layer;

removing the part of the protective layer above the surface of the interlayer dielectric layer;

removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer;

carrying out first annealing treatment;

and removing the protective layer.

2. The method of manufacturing of claim 1, further comprising the step of forming a capping layer on a surface of the high-k dielectric layer after forming the high-k dielectric layer and before forming the protective layer.

3. The method of manufacturing of claim 1, wherein the step of removing the portion of the protective layer over the surface of the interlayer dielectric layer comprises the steps of:

forming a sacrificial material layer to fill the gate trench and cover the protective layer over the surface of the interlayer dielectric layer;

planarizing the sacrificial material layer until the protective layer is exposed;

and removing the part of the protective layer above the surface of the interlayer dielectric layer.

4. The method of manufacturing of claim 3, further comprising the step of removing the layer of sacrificial material after the step of removing the high-k dielectric layer over the surface of the interlevel dielectric layer and before the step of first annealing.

5. The manufacturing method according to claim 1, wherein the temperature range of the first annealing treatment is 900 ℃ to 1100 ℃.

6. The method of manufacturing according to claim 1, wherein a material of the protective layer comprises amorphous silicon.

7. The method of manufacturing of claim 1, wherein the protective layer has a thickness in a range of 40 angstroms to 120 angstroms.

8. The method of claim 3, wherein the material of the sacrificial material layer comprises at least one of an organic distribution layer, a bottom anti-reflective coating, and a photoresist.

9. The method of manufacturing of claim 1, wherein spacers are formed on sidewalls of the gate trench prior to forming the high-k dielectric layer.

10. The manufacturing method according to claim 3, wherein the sacrificial material layer is removed by wet etching using an etchant comprising tetramethylammonium hydroxide or ammonium hydroxide.

11. The manufacturing method according to claim 10, wherein the temperature of the etchant when removing the sacrificial material layer is in a range of 25 ℃ to 75 ℃.

12. The method of manufacturing of claim 1, wherein after forming the high-k dielectric layer and before forming the protective layer, further comprising: and performing a second annealing step on the high-k dielectric layer.

Images