CN108447823A - A kind of semiconductor device and its manufacturing method and electronic device - Google Patents

Abstract

A kind of semiconductor devices of present invention offer and its manufacturing method and electronic device, the method includes：Semiconductor substrate is provided, active area and drain region is arranged in semiconductor substrate MOS device area in the semiconductor substrate in MOS device area；It is respectively formed on extension coating on the surface in source region and drain region, doped with impurity in extension coating；In the forming metal layer on surface of extension coating；It reacts at least partly extension coating to form metal silicide with metal layer, wherein the interface between the semi-conducting material that impurity fractional condensation is contacted to metal silicide and metal silicide.The method of the present invention, impurity is segregated to the interface between metal silicide and the semi-conducting material of Metal-silicides Contact, it captures the impurity being entrained in source region and drain region in interface, it forms dopant and detaches Schottky, schottky barrier height is reduced, has been also prevented from the impurity that is captured in extension coating to external diffusion.

Description

A kind of semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

As the integration of semiconductor devices continues to increase, the critical dimensions of semiconductor devices continue to decrease, and many problems have appeared correspondingly, such as the surface resistance and contact resistance of the source and drain regions of the device have increased accordingly, resulting in a decrease in the response speed of the device and signal occurrence. Delay. Therefore, an interconnection structure with low resistivity becomes a key element in the manufacture of highly integrated semiconductor devices.

In order to reduce the contact resistance of the source/drain region of the device, the process method of metal silicide is introduced. Usually, metal silicide is formed on the surface of the source and drain region of the device. The metal silicide has a lower resistivity and can significantly reduce Contact resistance of the source/drain region. Metal silicides and salicides and their formation processes have been widely used to reduce the surface resistance and contact resistance of device sources and drains, thereby reducing the resistance-capacitance delay time.

For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices can use Ge channels, while NMOS devices can use III-V compound semiconductors (such as InGaAs) as channels to increase carrier density. mobility. For the above channel material devices, how to form the metal silicide on the surface of the source and drain regions and how to apply the metal silicide and the contact process are the main problems at present.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

Aiming at the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device on the one hand, the method comprising:

A semiconductor substrate is provided, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region;

forming an epitaxial covering layer on the surfaces of both the source region and the drain region, wherein doping impurities are doped in the epitaxial covering layer;

forming a metal layer on the surface of the epitaxial covering layer;

reacting at least part of the epitaxial capping layer with the metal layer to form a metal silicide, wherein the dopant impurity is segregated to an interface between the metal silicide and a semiconductor material with which the metal silicide contacts .

Further, the MOS device area includes at least one of a PMOS device area and an NMOS device area;

The doping impurities in the epitaxial covering layer of the PMOS device region include Sb and/or N;

The doping impurities in the epitaxial covering layer of the NMOS device region include Ga and/or C.

Further, the entire thickness of the epitaxial covering layer is reacted with the metal layer to form the metal silicide, and the dopant impurity is segregated to the metal silicide and the source region as well as the metal silicide and at the interface between the drain regions; or,

The surface portion of the epitaxial covering layer reacts with the metal layer to form the metal silicide, and the dopant impurity is segregated to the interface between the metal silicide and the epitaxial covering layer.

Further, before forming the epitaxial covering layer, the following step is also included: forming a stress layer in the source region and the drain region, and the epitaxial covering layer is formed on the surface of the stress layer.

Further, the method for forming the stress layer includes:

etching a portion of the semiconductor substrate to form grooves in the source region and the drain region;

The stress layer is in-situ doped by epitaxial growth in the groove.

Further, the MOS device region includes a PMOS device region and an NMOS device region, and the PMOS device region is formed before forming the epitaxial covering layer of the PMOS device region, or after forming the epitaxial covering layer of the PMOS device region Before the metal layer of the NMOS device region, the epitaxial covering layer is formed on the surface of the source region and the drain region of the NMOS device region.

Further, the metal silicide is formed by reacting the epitaxial covering layer with the metal layer through an annealing treatment.

Another aspect of the present invention provides a semiconductor device, comprising:

a semiconductor substrate, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region;

An epitaxial covering layer is formed on the surfaces of the source region and the drain region, wherein doping impurities are doped in the epitaxial covering layer;

A metal silicide is formed on the surface of the epitaxial covering layer, wherein the dopant impurity is segregated to the interface between the metal silicide and the semiconductor material that the metal silicide contacts.

Further, the MOS device area includes at least one of a PMOS device area and an NMOS device area;

The doping impurities in the epitaxial cover layer of the PMOS device region include Sb and/or N;

The doping impurities in the epitaxial covering layer of the NMOS device region include Ga and/or C.

Further, the dopant impurity condenses to the interface between the metal silicide and the source region and the metal silicide and the drain region; or,

The dopant impurity is segregated to the interface between the metal silicide and the epitaxial cladding layer.

Further, a stress layer is formed in the source region and the drain region, and the epitaxial covering layer is formed on the surface of the stress layer.

Another aspect of the present invention provides an electronic device, which includes the aforementioned semiconductor device.

In the manufacturing method of the present invention, an epitaxial covering layer is formed on the surface of the source region and the drain region of the semiconductor substrate in the MOS device region, wherein the epitaxial covering layer is doped with doping impurities, and the epitaxial covering layer A metal layer is formed on the surface of the layer; at least part of the epitaxial covering layer reacts with the metal layer to form a metal silicide, wherein the doping impurities segregate to the metal silicide and the semiconductor in contact with the metal silicide The interface between the materials, and the doping impurities (such as N-type doping impurities or P-type doping impurities) in the source region and the drain region are captured at the interface, thereby forming a dopant separation Schottky (Dopant segregated Schottky, DSS for short), thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, so that the external parasitic resistance of the transistor is also reduced accordingly, in the The doping impurities doped in the epitaxial covering layer can also prevent the doping impurities captured from the source region and the drain region in the epitaxial covering layer from diffusing outward, therefore, the method of the present invention can improve the performance of the device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

1A to 1G show schematic cross-sectional views of devices obtained in related steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 3 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, detailed steps will be provided in the following description to explain the technical solution proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

Embodiment one

In order to solve the foregoing technical problems, the present invention provides a method for manufacturing a semiconductor device, as shown in Figure 2, mainly comprising the following steps:

Step S1, providing a semiconductor substrate, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region;

Step S2, forming an epitaxial covering layer on the surfaces of both the source region and the drain region, wherein the epitaxial covering layer is doped with doping impurities;

Step S3, forming a metal layer on the surface of the epitaxial covering layer;

Step S4, reacting at least part of the epitaxial covering layer with the metal layer to form a metal silicide, wherein the dopant impurity is segregated between the metal silicide and the semiconductor material in contact with the metal silicide at the interface.

In the manufacturing method of the present invention, an epitaxial covering layer is formed on the surface of the source region and the drain region of the semiconductor substrate in the MOS device region, wherein the epitaxial covering layer is doped with doping impurities, and the epitaxial covering layer A metal layer is formed on the surface of the layer; at least part of the epitaxial covering layer reacts with the metal layer to form a metal silicide, wherein the doping impurities segregate to the metal silicide and the semiconductor in contact with the metal silicide The interface between the materials, and the doping impurities in the source region and the drain region are captured at the interface, thereby forming a dopant segregated Schottky (DSS for short), thereby reducing the Schottky The potential barrier height (SBH) reduces the contact resistance (Rc) of the source/drain region, so that the external parasitic resistance of the transistor is also reduced accordingly, and the doping impurities doped in the epitaxial covering layer can also prevent the epitaxial covering The dopant impurity captured from the source region and the drain region in the layer diffuses outward, therefore, the method of the present invention can improve the performance of the device.

Next, the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to FIGS. 1A to 1G , wherein FIGS. 1A to 1G show the cross-section of the device obtained in the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention. schematic diagram.

First, step 1 is performed to provide a semiconductor substrate, the semiconductor substrate includes a PMOS device region, a first gate structure is arranged on the semiconductor substrate in the PMOS device region, and the first gate structure A first source region and a first drain region are arranged in the semiconductor substrate of the PMOS device region on both sides, wherein P-type dopant impurities are doped in the first source region and the first drain region.

Specifically, as shown in FIG. 1A, the semiconductor substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), insulator Silicon germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), etc.

In one example, the semiconductor device includes a MOS device region, and the MOS device region includes at least one of a PMOS device region and an NMOS device region.

In one example, the semiconductor substrate includes an NMOS device region and a PMOS device region, wherein a first gate structure is formed on the semiconductor substrate of the PMOS device region, and a first gate structure is formed on the semiconductor substrate of the NMOS device region A second gate structure is formed on it.

Wherein, the first gate structure and the second gate structure may be dummy gate structures, and the dummy gate structures include dummy gate structures stacked from bottom to top, each of which includes a dummy gate dielectric layer and a dummy gate pole material layer.

Exemplarily, the first gate structure and the second gate structure may also be metal gate structures.

Exemplarily, the channel material under the first gate structure in the PMOS device region includes an elemental semiconductor, wherein the elemental semiconductor material can be any elemental semiconductor known to those skilled in the art, including but not limited to Ge or Si or SiGe, the channel material under the second gate structure in the NMOS device region may include III-V group compound semiconductors, for example, III-V group binary or ternary compound semiconductors, in this embodiment, the The III-V group compound semiconductor is InGaAs. In this embodiment, the elemental semiconductor is Ge, and the III-V group compound semiconductor is used as the channel of the NMOS device, and the elemental semiconductor is used as the channel of the PMOS device, which can improve the loading capacity. Flow rate.

Further, a second source region and a second drain region are set in the semiconductor substrate of the NMOS device region on both sides of the second gate structure, and doped in the second source region and the second drain region Doped with N-type doping impurities.

Exemplarily, the semiconductor device of the present invention is a FinFET device, a first fin structure 1011 is formed on the semiconductor substrate in each of the PMOS device regions, and a fin structure 1011 is formed on the semiconductor substrate in the NMOS device region. The second fin structure 1012 , the first gate structure straddles the first fin structure 1011 , and the second gate structure straddles the second fin structure 1012 .

In one example, taking a FinFET device as an example, in order to obtain the structure shown in Figure 1A, the following steps A1 to A4 can be performed:

First, step A1 is performed to form a plurality of fin structures on the semiconductor substrate, for example, a first fin structure and a second fin structure are respectively formed in the PMOS device region and the NMOS device region on the semiconductor substrate. For the two-fin structure, the widths of the fin structures are all the same, or the fins are divided into multiple fin structure groups with different widths, and the lengths of the fin structures may also be different.

Specifically, the forming method of the fin structure is not limited to a certain one, and an exemplary forming method is given below: forming a hard mask layer (not shown in the figure) on the semiconductor substrate, forming the The hard mask layer can adopt various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process, and the hard mask layer can be an oxide layer and a silicon nitride layer stacked from bottom to top; pattern The hard mask layer is formed to form a plurality of masks isolated from each other for etching the semiconductor substrate to form fins thereon. In one embodiment, the self-aligned double patterning (SADP) process is used to implement the Patterning process; etching a semiconductor substrate to form fin structures thereon.

Subsequently, step A2 may also be performed to deposit an isolation material layer to cover all the aforementioned fin structures.

Specifically, a layer of isolation material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be oxide, such as high aspect ratio process (HARP) oxide, specifically silicon oxide.

Then etch back the isolation material layer to the target height of the fin structure to form the isolation structure 102, the top surface of the isolation structure 102 is lower than the top of the first fin structure and the second fin structure. noodle. Specifically, the isolation material layer is etched back to expose part of the fin structure, thereby forming a fin structure with a specific height.

Next, step A3 is performed to form a first dummy gate structure 104p across the first fin structure and a second dummy gate structure 104n across the second fin structure, wherein the dummy gate structures both include A dummy gate dielectric layer 1041 and a dummy gate material layer 1042 are sequentially stacked on top of it.

It should be pointed out that the term "straddling" used in the present invention, for example, straddles the dummy gate structure (or gate structure) of the fin structure (such as the first fin structure, the second fin structure, etc.), It means that a dummy gate structure is formed on both the upper surface and the side surface of part of the fin structure, and the dummy gate structure is also formed on a part of the surface of the semiconductor substrate.

In one example, the dummy gate dielectric layer 1041 and the dummy gate material layer 1042 may be sequentially deposited on the semiconductor substrate first.

Wherein, the dummy gate dielectric layer can be a commonly used oxide, such as SiO ₂ , and the dummy gate material layer can be a semiconductor material commonly used in the field, such as polysilicon, etc., and is not limited to a certain kind. , will not be listed here,

The deposition method of the dummy gate material layer 1042 may be chemical vapor deposition or atomic layer deposition.

Then pattern the dummy gate dielectric layer and the dummy gate material layer to form the first dummy gate structure and the second dummy gate structure. Specifically, a hard mask layer 105 is formed on the dummy gate material layer, a photoresist layer is formed on the hard mask layer 105, and then exposed and developed to form a first dummy gate structure and a second dummy gate structure. A patterned photoresist layer for patterning the dummy gate structure, and then using the photoresist layer as a mask to sequentially etch the hard mask layer 105, the dummy gate material layer 1042 and the dummy gate dielectric layer 1041 , to form the first dummy gate structure and the second dummy gate structure, and finally remove the photoresist layer.

Wherein, the hard mask layer 105 still remains on the dummy gate material layer 1042 .

After that, optionally, an offset spacer (not shown) can be formed on the sidewalls of the first dummy gate structure and the second dummy gate structure.

Specifically, the offset sidewall may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the offset sidewall is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second silicon nitride layer on a semiconductor substrate. The silicon dioxide layer is then etched to form offset sidewalls. It is also possible to form a sidewall material layer on both the top surface and the sidewall of the dummy gate structure, and in a subsequent step, the sidewall material layer on the top surface is removed by a planarization method, such as chemical mechanical polishing, to form only Offset side walls on side walls.

Optionally, an LDD ion implantation step is performed on both sides of the first dummy gate structure and the second dummy gate structure, and annealing is activated.

LDD ion implantation to form a lightly doped drain (LDD) structure in the source/drain region can reduce the electric field and can significantly improve the hot electron effect.

Perform LDD ion implantation to the first fin structures on both sides of the first dummy gate structure in the PMOS region to form a P-type lightly doped drain (LDD), and the implanted ions can be any P-type dopant ions, including But not limited to boron (B) ions and indium (In) ions.

LDD ion implantation is performed on the second fin structures on both sides of the second dummy gate structure in the NMOS region to form an N-type lightly doped drain (LDD), and the implanted ions can be any suitable N-type Doping ions include but not limited to phosphorus (P) ions and arsenic (As) ions.

Next, step A4 is performed to form a first stress layer in the first source region and the first drain region, and the P-type dopant impurity is doped in the first stress layer.

In one example, the method for forming the first stress layer includes the following steps:

As shown in FIG. 1A , first, a first spacer material layer 106p is formed to cover the semiconductor substrate 100 and the first gate structure.

Specifically, the first spacer material layer 106p covers the semiconductor substrate 100 in the PMOS device region and the NMOS device region and the surfaces of the first dummy gate structure 104p and the second dummy gate structure 104n.

The first spacer material layer 106p may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation manner of this embodiment, the first spacer material layer 106 is composed of silicon oxide and silicon nitride.

Next, part of the first spacer material layer 106p is removed by etching to expose the surfaces of the first source region and the first drain region, and a first dummy gate structure 104p is formed on the sidewall. a spacer wall 1061 .

Specifically, the first spacer material layer 106p on the top surface of the first dummy gate structure 104p can be etched away, while the first fin structure and the second fin structure outside the first dummy gate structure 104p The first spacer material layer 106p may remain on the sheet structure as a protection layer for the subsequent epitaxial growth of the first stress layer.

Exemplarily, a patterned photoresist layer can be formed through a photolithography process, and the photoresist layer covers the NMOS device region and exposes the first source region and the first drain region in the PMOS device region The first spacer material layer on the surface and the first spacer material layer on the surface of the first dummy gate structure can also expose the first spacer material layer 106p formed on the isolation structure 102, and then the patterning The photoresist layer is used as a mask, and the exposed first spacer material layer is etched away to expose the surfaces of the first source region and the first drain region, and the first dummy gate structure 104p A first gap wall is formed on the side wall.

The etching method can use any suitable method such as dry etching or wet etching known to those skilled in the art.

After the etching is completed, the photoresist layer can be removed by a method such as ashing.

Subsequently, a part of the semiconductor substrate is removed by etching to form a first groove in the first source region and the first drain region, and then a first stress layer 1031 is formed in the first groove.

In one example, etching part of the first fin structure on both sides of the first dummy gate structure 104p to form a first groove in a region where the first source region and the first drain region are scheduled to be formed; then The first stress layer 1031 is selectively epitaxially grown in the first groove. More preferably, the first groove can also be a "Σ" shaped groove.

Exemplarily, using an epitaxial growth process to epitaxially grow the first stress layer in-situ doped with the P-type dopant impurity in the first groove, because the first spacer material layer 106p and the dummy gate The protective effect of the hard mask layer 105 on the electrode material layer, therefore, the first stress layer 1031 is only selectively grown on the surface of the semiconductor substrate in the exposed first groove, and, due to the first spacer material layer 104n completely covers the NMOS device region, so the first stress layer 1031 will not grow on the semiconductor material of the NMOS device region.

Selective epitaxy can be grown using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE). kind of.

The material of the first stress layer 1031 may include SiGe or other suitable materials that can provide compressive stress. Specifically, in-situ doped SiGe can be grown by chemical vapor deposition or gas source molecular beam epitaxy, using silane or disilane as a silicon source, and adding a certain amount of germane. For example, GeH ₄ and SiH ₂ Cl ₂ are selected as the reaction gas, and H ₂ is selected as the carrier gas, wherein the flow ratio of the reaction gas and the carrier gas is 0.01-0.1, and the deposition temperature is 300°C-1000°C, preferably 650°C -750°C, the gas pressure is 1Torr-50Torr, preferably 20Torr-40Torr, and optionally during the deposition process by providing boron, boron difluoride (BF ₂ ) and/or diborane (B ₂ H ₆ ) and other dopants to make the SiGe epitaxial layer include P-type dopant impurities such as boron.

Wherein, the first stress layer doped with P-type impurity in-situ can be used to form source/drain regions in the PMOS device region, such as heavily doped source/drain regions.

A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying compressive stress to the PMOS.

Further, the first stress layer 1031 is formed in the first fin structure, and the top surface of the first stress layer 1031 is higher than the top surface of the first fin structure.

In one example, the first stress layer is not provided in the first source region and the first drain region, and the first source region and the first drain region are P-type doped by means of source/drain ion implantation The impurity doping, wherein, the source/drain ion implantation method can use the method commonly used by those skilled in the art, and further, the heavily doped first source region and the first drain region can be formed.

So far, the structure as shown in FIG. 1A is obtained through the above steps.

Next, step 2 is performed to form a first epitaxial covering layer on the surfaces of the first source region and the first drain region, wherein the first epitaxial covering layer is doped with first dopant impurities.

Specifically, as shown in FIG. 1B , a first epitaxial covering layer 107 is formed on the surfaces of the first source region and the first drain region, wherein the first epitaxial covering layer 107 is doped with the first Doped with impurities.

In one example, a first stress layer 1031 is formed in the first source region and the first drain region, and the first epitaxial covering layer 107 is formed on the surface of the first stress layer 1031 .

Wherein, the material of the first epitaxial covering layer 107 may be any suitable silicon-containing semiconductor material, including but not limited to SiGe, Si and the like. In this embodiment, the material of the first epitaxial cladding layer 107 is preferably SiGe.

Optionally, the first doping impurity includes Sb and/or N. In this embodiment, preferably, the first doping impurity includes Sb and N.

In one example, the first epitaxial capping layer 107 doped in-situ with the first dopant impurity is epitaxially grown on the surface of the first stress layer 1031 by using an epitaxial growth process, because the first spacer material layer 106p, therefore, the first epitaxial cladding layer 107 is only selectively grown on the exposed surface of the first stress layer 1031.

Selective epitaxy can be grown using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE). kind of.

In one example, the material of the first epitaxial cladding layer 107 may include SiGe, specifically, in-situ doped SiGe may be grown by chemical vapor deposition or gas source molecular beam epitaxy, using silane or disilane as the silicon source, At the same time, a certain amount of germane was added. For example, GeH ₄ and SiH ₂ Cl ₂ are selected as the reaction gas, and H ₂ is selected as the carrier gas, wherein the flow ratio of the reaction gas and the carrier gas is 0.01-0.1, and the deposition temperature is 300°C-1000°C, preferably 650°C -750°C, the gas pressure is 1Torr-50Torr, preferably 20Torr-40Torr, and optionally during the deposition process by providing dopants such as Sb and N so that the SiGe epitaxial layer includes such as Sb and/or N Such as the first dopant impurity.

Optionally, the thickness of the first epitaxial covering layer 107 may be reasonably selected according to actual process requirements. For example, the thickness of the first epitaxial covering layer 107 may range from 5 angstroms to 20 angstroms, or other suitable thicknesses.

Next, step 3 is performed to form a second stress layer in the second source region and the second drain region, and the N-type impurity is doped in the second stress layer.

In one example, the method for forming the second stress layer 1032 includes the following steps:

First, as shown in FIG. 1C, a second spacer material layer 106n is formed to cover the semiconductor substrate 100, the first gate structure and the second gate structure in the PMOS device region and the NMOS device region. grid structure.

Exemplarily, in the isolation structure 102, the first spacer material layer, the first spacer 1061, the first fin structure, the second fin structure, the first epitaxial covering The second gap material layer 106n is formed on the exposed surfaces of the layer 107, the first dummy gate structure 104p and the second dummy gate structure 104n.

The second spacer material layer 106n may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an implementation of this embodiment, the second spacer material layer 106n is composed of silicon oxide and silicon nitride. It can be formed using any suitable deposition method, including but not limited to methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

Next, as shown in FIG. 1C , part of the second spacer material layer is etched away to expose the surfaces of the second source region and the second drain region, and on the sides of the second gate structure A second spacer wall 1062 is formed on the wall.

Exemplarily, a patterned photoresist layer can be formed through a photolithography process, and the photoresist layer covers the PMOS device region and exposes the second source region and the second drain region in the NMOS device region The second spacer material layer on the surface and the second spacer material layer on the surface of the second dummy gate structure 104n may also expose part of the second spacer material layer 106n formed on the isolation structure 102 in the NMOS device region, Then use the patterned photoresist layer as a mask to etch and remove the exposed second spacer material layer and the first spacer material layer below it to expose the first source region and the first drain region, and form a second spacer 1062 on the sidewall of the second dummy gate structure 104n.

Wherein, the part of the second spacer material layer 106n located in the PMOS device region is reserved to serve as a protection layer.

The etching method can use any suitable method such as dry etching or wet etching known to those skilled in the art.

After the etching is completed, the photoresist layer can be removed by a method such as ashing.

Subsequently, a part of the semiconductor substrate is removed by etching to form a second groove in the second source region and the second drain region, and then a second stress layer 1032 is formed in the second groove.

In one example, etching part of the second fin structure on both sides of the second dummy gate structure 104n to form a second groove in the area where the second source region and the second drain region are scheduled to be formed; then The second stress layer 1032 is selectively epitaxially grown in the second groove.

Exemplarily, using an epitaxial growth process to epitaxially grow the second stress layer in-situ doped with the N-type impurity in the second groove, because the second spacer material layer 106n and the dummy gate The protective effect of the hard mask layer 105 on the electrode material layer, therefore, the second stress layer 1032 is only selectively grown on the surface of the semiconductor substrate in the exposed second groove, and, due to the second spacer material layer 106n covers the first epitaxial covering layer 107 and the entire PMOS device region, so no second stress layer will grow in the PMOS device region.

Selective epitaxy can be grown using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE). kind of.

In the NMOS device region, the second stress layer 1032 generally has tensile stress. The material of the second stress layer 1032 can be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stress layer 1032 .

Further, SiP can be grown by chemical vapor deposition or gas source molecular beam epitaxy, using silane or disilane as the silicon source, and phosphine as the phosphorus source, thereby forming a phosphorus in-situ doped Si epitaxial layer.

Further, the second stress layer 1032 is formed in the second fin structure, and the top surface of the second stress layer 1032 is higher than the top surface of the second fin structure.

Wherein, the first stress layer doped with N-type impurity in-situ can be used to form source/drain regions in the NMOS device region, such as heavily doped source/drain regions.

In one example, the second stress layer is not provided in the second source region and the second drain region, and the second source region and the second drain region are N-type doped by means of source/drain ion implantation The impurity doping, wherein, the source/drain ion implantation method can use the method commonly used by those skilled in the art, and further, a heavily doped second source region and a second drain region can be formed.

Subsequently, step 4 is performed to form a second epitaxial covering layer on the surfaces of the second source region and the second drain region, wherein the second epitaxial covering layer is doped with second dopant impurities.

Exemplarily, as shown in FIG. 1D , a second epitaxial covering layer 108 is formed on the surfaces of the second source region and the second drain region, wherein the second epitaxial covering layer 108 is doped with The second doping impurity.

In one example, a second stress layer 1032 is formed in the second source region and the second drain region, and the second epitaxial covering layer 108 is formed on the surface of the second stress layer 1032 .

Wherein, the material of the second epitaxial cladding layer 108 may be any suitable silicon-containing semiconductor material, including but not limited to SiGe, Si and the like. In this embodiment, the material of the second epitaxial cladding layer 108 is preferably SiGe.

Optionally, the second dopant impurity includes Ga and/or C. In this embodiment, preferably, the second dopant impurity includes Ga and C.

In one example, the second epitaxial cladding layer 108 doped in-situ with the second dopant impurity is epitaxially grown on the surface of the second stress layer 1032 by using an epitaxial growth process, because the second spacer material layer 106n and the protective effect of the hard mask layer 105, therefore, the second epitaxial covering layer 108 is only selectively grown on the exposed surface of the second stress layer 1032.

Selective epitaxy can be grown using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE). kind of.

In one example, the material of the second epitaxial cladding layer 108 may include SiGe, specifically, in-situ doped SiGe may be grown by chemical vapor deposition or gas source molecular beam epitaxy, using silane or disilane as the silicon source, At the same time, a certain amount of germane was added. For example, GeH ₄ and SiH ₂ Cl ₂ are selected as the reaction gas, and H ₂ is selected as the carrier gas, wherein the flow ratio of the reaction gas and the carrier gas is 0.01-0.1, and the deposition temperature is 300°C-1000°C, preferably 650°C -750°C, the gas pressure is 1Torr-50Torr, preferably 20Torr-40Torr, it is also possible to selectively provide dopants such as Ga and C during the deposition process to make the SiGe epitaxial layer include Ga and/or C The second dopant impurity of the class.

Optionally, the thickness of the second epitaxial covering layer 108 may be reasonably selected according to actual process requirements, for example, the thickness of the second epitaxial covering layer 108 may range from 5 angstroms to 20 angstroms, or other suitable thicknesses.

It is worth mentioning that in this embodiment, the first stress layer in the PMOS device region, the first epitaxial covering layer, and the doping of the first dopant impurity are first formed, and then the second stress layer in the NMOS device region, the second stress layer, and the like are formed. Steps such as the doping of the second epitaxial covering layer and the second doping impurity, and the reasonable exchange of the order of other steps are also applicable to the present invention, for example, the second stress layer of the NMOS device region, the second epitaxial covering layer and Steps such as doping the second doping impurity, and then forming the first stress layer in the PMOS device region, the first epitaxial covering layer, and doping the first doping impurity.

Next, step 5 is performed to form a first interlayer dielectric layer on the semiconductor substrate, the top surface of the first interlayer dielectric layer is connected to the first gate structure and the second gate structure flush with the top.

Exemplarily, as shown in FIG. 1E, the first gate structure is a first dummy gate structure 104p, the second gate structure is a second dummy gate structure 104n, and a first interlayer dielectric layer is deposited 1091 to cover the entire surface of the semiconductor substrate, and then perform a planarization step, stopping on the top surfaces of the first dummy gate structure 104p and the second dummy gate structure 104n, the first dummy gate structure can be flattened by planarization The hard mask layer on the top surfaces of the structure 104p and the second dummy gate structure 104n is removed.

Wherein, the first interlayer dielectric layer 1091 can be selected from dielectric materials commonly used in this field, such as various oxides, etc. In this embodiment, the interlayer dielectric layer can be selected from SiO ₂ , and its thickness is not limited. at a certain value.

Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.

Next, step six is performed, removing the first dummy gate structure and the second dummy gate structure to form a first gate trench and a second gate trench.

removing the first dummy gate structure and the second dummy gate structure, including sequentially removing the dummy gate dielectric layer and the dummy gate material layer, so as to form a first gate trench on the semiconductor substrate 100 in the PMOS device region, Forming a second gate trench on the semiconductor substrate 100 in the NMOS device region, the gate trench in the PMOS device region exposes part of the first fin structure in the extending direction of the first fin structure, The gate trench of the NMOS device region exposes part of the second fin structure in the extending direction of the second fin structure.

The method of removing the first dummy gate structure and the second dummy gate structure may be any suitable dry etching or wet etching method.

Next, step seven is performed, forming a first metal gate structure in the first gate trench, and forming a second metal gate structure in the second gate trench.

Exemplarily, as shown in FIG. 1E , a first metal gate structure 1101 is formed in the first gate trench, and a second metal gate structure 1102 is formed in the second gate trench.

Exemplarily, the first metal gate structure 1101 includes an interface layer formed at the bottom of the gate trench in the PMOS device region, sequentially formed on the bottom and sidewalls of the gate trench and located above the interface layer The high-k dielectric layer, the first diffusion barrier layer, the P-type work function layer, the N-type work function layer and the second diffusion barrier layer, and the gate electrode layer filling the gate trench.

Exemplarily, the second metal gate structure 1102 includes an interface layer formed at the bottom of the gate trench in the NMOS device region, sequentially formed on the bottom and sidewalls of the gate trench and located above the interface layer The high-k dielectric layer, the first diffusion barrier layer, the N-type work function layer and the second diffusion barrier layer, and the gate electrode layer filling the gate trench.

Wherein, the first metal gate structure and the second metal gate structure may be formed using any suitable method known to those skilled in the art, and details will not be repeated here.

It is worth mentioning that the first gate structure and the second gate structure of the present invention can also be other types of gate structures, for example, the gate structure includes gate dielectric layers and For the gate layer, the gate dielectric layer may be a dielectric material such as silicon oxide, and the gate layer may be a material such as polysilicon.

Next, step 8 is performed, forming a second interlayer dielectric layer on the surfaces of the first interlayer dielectric layer, the first gate structure, and the second gate structure.

Specifically, as shown in FIG. 1F , the second interlayer dielectric layer 1092 covers the first interlayer dielectric layer 1091 and the first metal gate structure 1101 and the second metal gate structure 1102 surface and flatten it.

The second interlayer dielectric layer 1092 may be a silicon oxide layer, including doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermalCVD) manufacturing process or a high density plasma (HDP) manufacturing process. Layers of material such as undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped Tetraethoxysilane (BTEOS).

The thickness of the second interlayer dielectric layer 1092 can be any suitable value, which is not specifically limited here. The top surface of the second interlayer dielectric layer 1092 is higher than the first metal gate structure 1101 and the first metal gate structure 1101 The top surface of the two metal gate structure 1102 .

Next, perform step nine, forming a first contact hole opening in the second interlayer dielectric layer and the first interlayer dielectric layer, the first contact hole opening exposing the first epitaxial covering layer A second contact hole opening is formed in the second interlayer dielectric layer and the first interlayer dielectric layer, and the second contact hole opening exposes the surface of the second epitaxial covering layer.

In one example, the method of forming the first contact hole opening and the second contact hole opening includes the following steps:

First, as shown in FIG. 1F, the etching of the interlayer dielectric layer (including the second interlayer dielectric layer 1092 and the first interlayer dielectric layer 1091) stops at the first epitaxial capping layer 107 and the second epitaxy on the surface of the capping layer 108 to form a first contact hole opening 1111 and a second contact hole opening 1112 .

Further, the bottom of the first contact opening 1111 is located in the first epitaxial covering layer 107 , and the bottom of the second contact opening 1112 is located in the second epitaxial covering layer 108 .

Specifically, a patterned photoresist layer can be firstly formed on the surface of the second interlayer dielectric layer 1092, and the photoresist layer defines the positions and sizes of the predetermined first contact hole opening and the second contact hole opening. etc., and then use the patterned photoresist as a mask to sequentially etch the second interlayer dielectric layer and the first interlayer dielectric layer, stopping at the first epitaxial covering layer 107 and the second epitaxial covering layer 108 respectively. to form a first contact hole opening 1111 and a second contact hole opening 1112 .

Subsequently, the patterned photoresist layer is removed, for example, using ashing method to remove the photoresist layer.

Subsequently, step ten is performed, forming a third contact hole opening and a fourth contact hole opening in the second interlayer dielectric layer, wherein the third contact hole opening exposes the top surface of the first gate structure , the opening of the fourth contact hole exposes the top surface of the second gate structure.

Specifically, as shown in FIG. 1F, a third contact hole opening 1113 and a fourth contact hole opening 1114 are formed in the second interlayer dielectric layer 1092, wherein the third contact hole opening 1113 exposes the first The top surface of a metal gate structure 1101 , the fourth contact opening 1114 exposes the top surface of the second metal gate structure 1102 .

Exemplarily, a patterned photoresist layer is formed on the second interlayer dielectric layer 1092, and the patterned photoresist layer defines the position, size and pattern of the opening of the third contact hole and the opening of the fourth contact hole, etc. parameters, and then use the patterned photoresist layer as a mask to etch the second interlayer dielectric layer 1092 to stop on the surface of the first metal gate structure 1101 and the second metal gate structure 1102, so as to form the The third contact hole opening 1113 and the fourth contact hole opening 1114 are described above.

Subsequently, the photoresist layer may be removed using methods such as ashing.

Subsequently, step eleven is performed to perform a pre-cleaning step to remove the natural oxide layer.

Specifically, as shown in FIG. 1G, a pre-cleaning step is performed to remove the oxide layer at the bottom of the first contact hole opening, the second contact hole opening, the third contact hole opening and the fourth contact hole opening, such as a natural oxide layer. .

The pre-cleaning can use any suitable method known to those skilled in the art, for example, using a cleaning solution including hydrofluoric acid and the like.

Subsequently, step 12 is performed, forming a metal layer on the bottoms and sidewalls of the first contact hole opening and the second contact hole opening.

Specifically, as shown in FIG. 1G , a metal layer 112 is formed on the bottom and sidewalls of the first contact opening, the second contact opening, the third contact opening and the fourth contact opening.

The material of the metal layer may be titanium (Ti), nickel, cobalt, platinum or a combination thereof. In this embodiment, Ti is preferably used as the material of the metal layer.

The metal layer 112 can be deposited by any suitable method known to those skilled in the art, including but not limited to chemical vapor deposition or physical vapor deposition.

Subsequently, step 13 is performed to form a covering layer (not shown) on the metal layer 112 .

The covering layer can be prepared by physical vapor deposition (PVD), and the covering layer can be formed at a temperature between -40°C and 400°C and a pressure between 0.1 mTorr and 100 mTorr. . The material of the covering layer is metal or metal compound layer material such as tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, tungsten nitride, alloys or compositions thereof. In addition, the covering layer may also include multiple film layers. In this embodiment, the covering layer includes a TiN layer.

Subsequently, step fourteen is performed to perform an annealing step.

This annealing step can use any suitable annealing method, such as furnace tube annealing, laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light sources (such as halogen lamps, arc lamps, graphite heating) rapid annealing. In this embodiment, preferably, the annealing treatment uses laser annealing (laser anneal).

Wherein, the annealing temperature range may be 800-1100°C, preferably, the annealing temperature is 900°C. The annealing time may be any suitable time, for example, the annealing time may range from 400 μs to 800 μs, and the annealing time is also the dwell time (dwell time) when laser annealing is used.

During the annealing process in this step, the metal layer at the bottom of the opening of the first contact hole and the first epitaxial covering layer 107 in contact with it react to form a first metal silicide (for example, TiSi), so that the bottom of the opening of the second contact hole The metal layer reacts with the second epitaxial capping layer 108 in contact with it to form a second metal silicide (for example, TiSi).

In one example, the first metal silicide surrounds the bottom of the opening of the first contact hole, and the bottom of the first metal silicide is located in the first epitaxial capping layer 107 and higher than the surface of the semiconductor substrate.

In one example, the first metal silicide surrounds the bottom of the opening of the second contact hole, and the bottom of the first metal silicide is located in the second epitaxial capping layer 108 and higher than the surface of the semiconductor substrate.

At the same time, the annealing step also segregates the first dopant impurities (Sb and N) to the interface between the first metal silicide and the semiconductor material it contacts, and captures the P-type impurity at the interface. Doping impurities (for example, the P-type doping impurities are P-type doping impurities in-situ doped in the first stress layer), thereby forming dopant separation Schottky (Dopantsegregated Schottky, DSS for short), P-type doping The impurities are finally located on the side of the metal silicide at the interface, thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, and reducing the external parasitic resistance of the transistor accordingly. The impurity first dopant impurity can also prevent the P-type dopant impurity in the first epitaxial cladding layer from diffusing out (for example, diffusing into the first stress layer).

In one example, the entire thickness of the first epitaxial cladding layer reacts with the metal layer to form the first metal silicide, and the first dopant impurity is segregated into the first metal silicide and the first metal silicide. At the interface between the first source region and the first metal silicide and the first drain region, for example, the first dopant impurity is condensed to the first metal silicide and the first drain region. interface of the stress layer.

In one example, the surface portion of the first epitaxial cladding layer reacts with the metal layer to form the first metal silicide, and the first dopant impurity is segregated into the first metal silicide and the first metal silicide. at the interface between the first epitaxial cladding layers.

Further, at the same time, the annealing step also causes the second dopant impurity (Ga and/or C) to segregate to the interface between the second metal silicide and the semiconductor material it contacts, and at the interface Capture the N-type dopant impurity (for example, the N-type dopant impurity is the N-type dopant impurity doped in-situ in the second stress layer), and then form a dopant segregated Schottky (DSS for short) ), N-type doping impurities are finally located on the side of the metal silicide at the interface, thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, and making the external parasitic of the transistor The resistance is correspondingly reduced, and the doped second dopant impurity can also prevent the N-type dopant impurity in the second epitaxial covering layer from diffusing out (for example, diffusing into the second stress layer).

In one example, the entire thickness of the second epitaxial cladding layer reacts with the metal layer to form the second metal silicide, and the second dopant impurity is segregated into the second metal silicide and the second metal silicide. At the interface between the second source region and the second metal silicide and the second drain region, for example, the second dopant impurity condenses to the second metal silicide and the second interface of the stress layer.

In one example, the surface portion of the second epitaxial cladding layer reacts with the metal layer to form the second metal silicide, and the second dopant impurity is segregated to the second metal silicide and the second metal silicide. at the interface between the second epitaxial cladding layer.

It should be noted that the annealing in this step can also be performed before forming the covering layer and after forming the metal layer.

Afterwards, step fifteen is performed, forming a conductive layer to fill the first contact hole opening, the second contact hole opening, the third contact hole opening and the fourth contact hole opening, so as to respectively form the first contact hole, the second contact hole, the a third contact hole and a fourth contact hole.

Specifically, as shown in FIG. 1G, a conductive layer 113 is formed to fill the opening of the first contact hole, the opening of the second contact hole, the opening of the third contact hole and the opening of the fourth contact hole and planarized to form the first contact hole opening, respectively. A contact hole, a second contact hole, a third contact hole, and a fourth contact hole.

Conductive materials can be formed by low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques.

Wherein, the conductive layer may be any suitable conductive material known to those skilled in the art, including but not limited to metal materials. Preferably, the conductive layer is made of tungsten material. In another embodiment, the conductive layer may be cobalt (Co), molybdenum (Mo), titanium nitride (TiN), and conductive materials containing tungsten, or a combination thereof.

Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method. The planarization stops on the surface of the second ILD layer 1092 .

The first contact hole structure is electrically connected to the source/drain region in the PMOS device region, the second contact hole structure is electrically connected to the source/drain region in the NMOS device region, and the third contact hole The structure is electrically connected to the first gate structure, and the fourth contact hole structure is electrically connected to the second gate structure.

So far, the introduction of the key steps of the manufacturing method of the semiconductor device of the present invention is completed, and other steps are required for the preparation of a complete device, which will not be repeated here.

In summary, in the manufacturing method of the present invention, a first epitaxial covering layer is formed on the surfaces of the first source region and the first drain region of the semiconductor substrate in the PMOS device region, wherein, in the first epitaxial The covering layer is doped with a first doping impurity (for example, Sb and/or N), a metal layer is formed on the surface of the first epitaxial covering layer, and at least part of the first epitaxial covering layer reacts with the metal layer forming a first metal silicide, wherein the first dopant impurity segregates to the interface between the first metal silicide and the semiconductor material it contacts, and captures the P-type dopant at the interface Impurities, and then form dopant segregated Schottky (DSS for short), thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, making the transistor The external parasitic resistance of is also correspondingly reduced, and the doped first dopant impurity can also prevent the outward diffusion of the P-type dopant impurity in the first epitaxial cladding layer;

In addition, a second epitaxial covering layer is formed on the surface of the second source region and the second drain region of the semiconductor substrate in the NMOS device region, wherein the second epitaxial covering layer is doped with a second impurity (for example, Ga and/or C), forming a metal layer on the surface of the second epitaxial covering layer, at least part of the second epitaxial covering layer reacts with the metal layer to form a second metal silicide, wherein the The second dopant impurity condenses to the interface between the first metal silicide and the semiconductor material it contacts, and captures the N-type dopant impurity at the interface, thereby forming a dopant separation Schottky (Dopant segregated Schottky, DSS for short), thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, so that the external parasitic resistance of the transistor is also reduced accordingly, and the doped The second dopant impurity can also prevent the N-type dopant impurity in the second epitaxial covering layer from diffusing out. Therefore, the method of the present invention can improve the performance of the device.

Embodiment two

The present invention also provides a semiconductor device, which is prepared by the manufacturing method in the first embodiment above.

The structure of the semiconductor device of the present invention will be described in detail below with reference to FIG. 1G. Wherein, in this embodiment, a FinFET device is mainly taken as an example.

Specifically, as shown in FIG. 1G , the semiconductor device of the present invention includes: a semiconductor substrate 100 including a MOS device region.

In one example, the MOS device area includes at least one of a PMOS device area and an NMOS device area.

In this embodiment, the present invention will be described mainly in the case that the semiconductor substrate includes a PMOS device region and an NMOS device region.

Wherein, the semiconductor substrate 100 is a bulk silicon substrate, which may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compounds Semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) And germanium on insulator (GeOI) and so on.

In one example, a first gate structure is disposed on the semiconductor substrate 100 in the PMOS device region, and a second gate structure is disposed on the semiconductor substrate 100 in the NMOS device region.

Exemplarily, the semiconductor device of the present invention is a FinFET device, a first fin structure 1011 is formed on the semiconductor substrate in each of the PMOS device regions, and a fin structure 1011 is formed on the semiconductor substrate in the NMOS device region. There is a second fin structure 1012 across which the first gate structure spans and a second gate structure straddles the second fin structure.

Exemplarily, the first gate structure is a first metal gate structure 1101, which includes an interface layer formed at the bottom of the gate trench in the PMOS device region, and is sequentially formed on the bottom and sidewall of the gate trench A high-k dielectric layer, a first diffusion barrier layer, a P-type work function layer, an N-type work function layer, and a second diffusion barrier layer on and above the interface layer, and a gate electrode layer filling the gate trench .

Exemplarily, the second gate structure is a second metal gate structure 1102, which includes an interface layer formed at the bottom of the gate trench in the NMOS device region, and is sequentially formed on the bottom and sidewall of the gate trench A high-k dielectric layer on and above the interface layer, a first diffusion barrier layer, an N-type work function and a second diffusion barrier layer, and a gate electrode layer filling the gate trench.

Wherein, the first metal gate structure and the second metal gate structure may be formed using any suitable method known to those skilled in the art, and details will not be repeated here.

It is worth mentioning that the first gate structure and the second gate structure of the present invention can also be other types of gate structures, for example, the gate structure includes gate dielectric layers and For the gate layer, the gate dielectric layer may be a dielectric material such as silicon oxide, and the gate layer may be a material such as polysilicon.

Exemplarily, the channel material under the first gate structure in the PMOS device region includes an elemental semiconductor, wherein the elemental semiconductor material can be any elemental semiconductor known to those skilled in the art, including but not limited to Ge or Si or SiGe, the channel material under the second gate structure in the NMOS device region may include III-V group compound semiconductors, for example, III-V group binary or ternary compound semiconductors, in this embodiment, the The III-V group compound semiconductor is InGaAs. In this embodiment, the elemental semiconductor is Ge, and the III-V group compound semiconductor is used as the channel of the NMOS device, and the elemental semiconductor is used as the channel of the PMOS device, which can improve the loading capacity. Flow rate.

In one example, a first spacer 1061 is formed on a sidewall of the first gate structure, and a second spacer 1062 is formed on a sidewall of the second gate structure.

In one example, a first source region and a first drain region are provided in the semiconductor substrate of the PMOS device region on both sides of the first gate structure, wherein the first source region and the first drain region The region is doped with P-type doping impurities. Optionally, the P-type doping impurities include boron.

Exemplarily, a first stress layer 1031 is formed in the first source region and the first drain region, and the P-type impurity is doped in the first stress layer 1031 .

The material of the first stress layer 1031 may include SiGe or other suitable materials that can provide compressive stress. Specifically, SiGe doped in-situ with P-type dopant impurities can be grown by chemical vapor deposition or gas source molecular beam epitaxy.

A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying compressive stress to the PMOS.

Further, the first stress layer 1031 is formed in the first fin structure, and the top surface of the first stress layer 1031 is higher than the top surface of the first fin structure.

Further, a first epitaxial covering layer 107 is formed on the surfaces of the first source region and the first drain region, wherein the first epitaxial covering layer 107 is doped with first doping impurities.

In one example, a first stress layer 1031 is formed in the first source region and the first drain region, and the first epitaxial covering layer 107 is formed on the surface of the first stress layer 1031 .

Wherein, the material of the first epitaxial covering layer 107 may be any suitable silicon-containing semiconductor material, including but not limited to SiGe, Si and the like. In this embodiment, the material of the first epitaxial cladding layer 107 is preferably SiGe.

Optionally, the first doping impurity includes Sb and/or N. In this embodiment, preferably, the first doping impurity includes Sb and N.

In one example, the first epitaxial cladding layer 107 doped in-situ with the first dopant impurity is formed by epitaxial growth on the surface of the first stress layer 1031 by using an epitaxial growth process.

Optionally, the thickness of the first epitaxial covering layer 107 may be reasonably selected according to actual process requirements. For example, the thickness of the first epitaxial covering layer 107 may range from 5 angstroms to 20 angstroms, or other suitable thicknesses.

Further, a second source region and a second drain region are set in the semiconductor substrate of the NMOS device region on both sides of the second gate structure, and doped in the second source region and the second drain region Doped with N-type dopant impurities, optionally, the N-type dopant impurities include at least one of phosphorus or arsenic.

In one example, a second stress layer 1032 is formed in the second source region and the second drain region, and the N-type impurity is doped in the second stress layer.

In the NMOS device region, the second stress layer 1032 generally has tensile stress. The material of the second stress layer 1032 can be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stress layer 1032 .

Further, SiP can be grown by chemical vapor deposition or gas source molecular beam epitaxy, using silane or disilane as the silicon source, and phosphine as the phosphorus source, thereby forming a phosphorus in-situ doped Si epitaxial layer.

Further, the second stress layer 1032 is formed in the second fin structure, and the top surface of the second stress layer 1032 is higher than the top surface of the second fin structure.

Exemplarily, a second epitaxial covering layer 108 is formed on the surfaces of the second source region and the second drain region, wherein the second epitaxial covering layer 108 is doped with second doping impurities .

In one example, a second stress layer 1032 is formed in the second source region and the second drain region, and the second epitaxial covering layer 108 is formed on the surface of the second stress layer 1032 .

Wherein, the material of the second epitaxial cladding layer 108 may be any suitable silicon-containing semiconductor material, including but not limited to SiGe, Si and the like. In this embodiment, the material of the second epitaxial cladding layer 108 is preferably SiGe.

Optionally, the second dopant impurity includes Ga and/or C. In this embodiment, preferably, the second dopant impurity includes Ga and C.

In one example, the second epitaxial cladding layer 108 doped in-situ with the second dopant impurity is formed by epitaxial growth on the surface of the second stress layer 1032 by using an epitaxial growth process.

Optionally, the thickness of the second epitaxial covering layer 108 may be reasonably selected according to actual process requirements, for example, the thickness of the second epitaxial covering layer 108 may range from 5 angstroms to 20 angstroms, or other suitable thicknesses.

Further, in the PMOS device region, on the side of the first spacer 1061 and part of the surface of the first epitaxial cover layer 107 and the exposed surface of the first fin structure and part of the surface of the isolation structure A second spacer material layer 106n is formed thereon.

In one example, in the NMOS device region, a first spacer material layer and a second spacer material layer are formed from bottom to top on a part of the surface of the second fin structure 1012 and a part of the surface of the isolation structure. Floor.

In one example, a first interlayer dielectric layer 1091 is formed on the semiconductor substrate, the top surface of the first interlayer dielectric layer is in contact with the first gate structure and the second gate structure flush with the top.

In one example, a second interlayer dielectric layer is formed on surfaces of the first interlayer dielectric layer and the first gate structure and the second gate structure.

Specifically, the second interlayer dielectric layer 1092 covers the surfaces of the first interlayer dielectric layer 1091 and the first metal gate structure 1101 and the second metal gate structure 1102 .

The second interlayer dielectric layer 1092 may be a silicon oxide layer, including doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermalCVD) manufacturing process or a high density plasma (HDP) manufacturing process. Layers of material such as undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped Tetraethoxysilane (BTEOS).

The thickness of the second interlayer dielectric layer 1092 can be any suitable value, which is not specifically limited here. The top surface of the second interlayer dielectric layer 1092 is higher than the first metal gate structure 1101 and the first metal gate structure 1101 The top surface of the two metal gate structure 1102 .

In one example, a first contact hole opening is formed in the second interlayer dielectric layer 1092 and the first interlayer dielectric layer 1091, and the first contact hole opening exposes the first epitaxial capping layer. 107, a second contact hole opening is formed in the second interlayer dielectric layer 1092 and the first interlayer dielectric layer 1091, and the second contact hole opening exposes the second epitaxial covering layer 108 s surface.

Further, the bottom of the opening of the first contact hole is located in the epitaxial covering layer 107 , and the bottom of the opening of the second contact hole is located in the second epitaxial covering layer 108 .

Further, a third contact hole opening and a fourth contact hole opening are formed in the second interlayer dielectric layer 1092, wherein the third contact hole opening exposes the top surface of the first metal gate structure 1101 , the opening of the fourth contact hole exposes the top surface of the second metal gate structure 1102 .

Further, a metal layer 112 is formed on the bottoms and sidewalls of the first contact hole opening, the second contact hole opening, the third contact hole opening and the fourth contact hole opening.

The material of the metal layer may be titanium (Ti), nickel, cobalt, platinum or a combination thereof. In this embodiment, Ti is preferably used as the material of the metal layer.

Further, a cover layer (not shown) is formed on the metal layer 112 .

The material of the covering layer is metal or metal compound layer material such as tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, tungsten nitride, alloys or compositions thereof. In addition, the covering layer may also include multiple film layers. In this embodiment, the covering layer includes a TiN layer.

Further, the metal layer 112 reacts with the contacted first epitaxial covering layer and the second epitaxial covering layer through annealing, thereby forming a first metal silicide and a second metal silicide (for example, TiSi).

Further, a first metal silicide is formed on the surface of the first epitaxial covering layer 107, wherein the first dopant impurity condenses between the first metal silicide and the semiconductor material it contacts at the interface.

In one example, the first metal silicide surrounds the bottom of the opening of the first contact hole, and the bottom of the first metal silicide is located in the first epitaxial capping layer 107 and higher than the surface of the semiconductor substrate.

In one example, the first metal silicide surrounds the bottom of the opening of the second contact hole, and the bottom of the first metal silicide is located in the second epitaxial capping layer 108 and higher than the surface of the semiconductor substrate.

At the same time, the annealing causes the first dopant impurities (Sb and N) to segregate to the interface between the first metal silicide and the semiconductor material it contacts, and captures the P-type dopant at the interface. impurities (for example, the P-type dopant impurity is the P-type dopant impurity doped in-situ in the first stress layer), and then forms a dopant segregated Schottky (DSS for short), and the P-type dopant impurity finally Located on the side of the metal silicide at the interface, thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, so that the external parasitic resistance of the transistor is also reduced accordingly, and the doped The first dopant impurity can also prevent the P-type dopant impurity in the first epitaxial cladding layer from diffusing out (for example, diffusing into the first stress layer).

In one example, the entire thickness of the first epitaxial cladding layer reacts with the metal layer to form the first metal silicide, and the first dopant impurity is segregated into the first metal silicide and the first metal silicide. At the interface between the first source region and the first metal silicide and the first drain region, for example, the first dopant impurity is condensed to the first metal silicide and the first drain region. interface of the stress layer.

In one example, the surface portion of the first epitaxial cladding layer reacts with the metal layer to form the first metal silicide, and the first dopant impurity is segregated into the first metal silicide and the first metal silicide. at the interface between the first epitaxial cladding layers.

In one example, a second metal silicide is formed on the surface of the second epitaxial cladding layer, wherein the second dopant impurity is segregated to the second metal silicide and the semiconductor material in contact with it at the interface between them, and capture the N-type dopant impurities.

Further, at the same time, the annealing step also causes the second dopant impurity (Ga and/or C) to segregate to the interface between the second metal silicide and the semiconductor material it contacts, and at the interface Capture the N-type dopant impurity (for example, the N-type dopant impurity is the N-type dopant impurity doped in-situ in the second stress layer), and then form a dopant segregated Schottky (DSS for short) ), N-type doping impurities are finally located on the side of the metal silicide at the interface, thereby reducing the Schottky barrier height (SBH), reducing the contact resistance (Rc) of the source/drain region, and making the external parasitic of the transistor The resistance is correspondingly reduced, and the doped second dopant impurity can also prevent the N-type dopant impurity in the second epitaxial covering layer from diffusing out (for example, diffusing into the second stress layer).

In one example, all of the second epitaxial cladding layer reacts with the metal layer to form the second metal silicide, and the second dopant impurity is segregated into the second metal silicide and the first metal silicide. At the interface between the two source regions and the second metal silicide and the second drain region, for example, the second dopant impurity condenses to the second metal silicide and the second stress layer at the interface.

In one example, the surface portion of the second epitaxial cladding layer reacts with the metal layer to form the second metal silicide, and the second dopant impurity is segregated to the second metal silicide and the second metal silicide. at the interface between the second epitaxial cladding layer.

In one example, the first contact hole opening, the second contact hole opening, the third contact hole opening and the fourth contact hole opening are filled with a conductive layer 113 to form the first contact hole, the second contact hole, the second contact hole, respectively. three contact holes and a fourth contact hole.

The first contact hole is electrically connected to the source/drain region in the PMOS device region, the second contact hole is electrically connected to the source/drain region in the NMOS device region, and the third contact hole is electrically connected to The first gate structure and the fourth contact hole are electrically connected to the second gate structure.

So far, the introduction of the key structure of the semiconductor device of the present invention is completed, and the complete device may also include other components, which will not be repeated here.

The semiconductor device of the present invention also has the above-mentioned advantages due to the adoption of the above-mentioned manufacturing method.

The semiconductor device of the invention has low Schottky barrier height and low contact resistance, so its external parasitic capacitance is also lower and has higher device performance.

Embodiment Three

The present invention also provides an electronic device, including the semiconductor device described in Embodiment 2, and the semiconductor device is prepared according to the method described in Embodiment 1.

The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

Among them, FIG. 3 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

Wherein the mobile phone includes the semiconductor device described in Embodiment 2, and the semiconductor device includes:

a semiconductor substrate, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region;

An epitaxial covering layer is formed on the surfaces of the source region and the drain region, wherein doping impurities are doped in the epitaxial covering layer;

A metal silicide is formed on the surface of the epitaxial covering layer, wherein the dopant impurity is segregated to the interface between the metal silicide and the semiconductor material that the metal silicide contacts.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (12)

1. A method for manufacturing a semiconductor device, characterized in that the method comprises: A semiconductor substrate is provided, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region; forming an epitaxial covering layer on the surfaces of both the source region and the drain region, wherein doping impurities are doped in the epitaxial covering layer; forming a metal layer on the surface of the epitaxial covering layer; reacting at least part of the epitaxial capping layer with the metal layer to form a metal silicide, wherein the dopant impurity is segregated to an interface between the metal silicide and a semiconductor material with which the metal silicide contacts . 2. The manufacturing method according to claim 1, wherein the MOS device region comprises at least one of a PMOS device region and an NMOS device region; The doping impurities in the epitaxial covering layer of the PMOS device region include Sb and/or N; The doping impurities in the epitaxial covering layer of the NMOS device region include Ga and/or C. 3. The manufacturing method according to claim 1, characterized in that, the entire thickness of the epitaxial covering layer is reacted with the metal layer to form the metal silicide, and the dopant impurity is segregated into the metal at the interface between the silicide and the source region and the metal silicide and the drain region; or, The surface portion of the epitaxial covering layer reacts with the metal layer to form the metal silicide, and the dopant impurity is segregated to the interface between the metal silicide and the epitaxial covering layer. 4. The manufacturing method according to any one of claims 1 to 3, characterized in that, before forming the epitaxial covering layer, further comprising the following steps: forming a stress layer in the source region and the drain region, The epitaxial capping layer is formed on the surface of the stressor layer. 5. The manufacturing method according to claim 4, wherein the method for forming the stress layer comprises: etching a portion of the semiconductor substrate to form grooves in the source region and the drain region; The stress layer is in-situ doped by epitaxial growth in the groove. 6. The manufacturing method according to claim 2, wherein the MOS device region comprises a PMOS device region and an NMOS device region, before forming the epitaxial covering layer of the PMOS device region, or, after forming the PMOS After the epitaxial covering layer of the device region and before forming the metal layer of the PMOS device region, the epitaxial covering layer is formed on the surfaces of the source region and the drain region of the NMOS device region. 7. The manufacturing method according to claim 1, wherein the metal silicide is formed by reacting the epitaxial covering layer and the metal layer by annealing. 8. A semiconductor device, characterized in that it comprises: a semiconductor substrate, the semiconductor substrate includes a MOS device region, and an active region and a drain region are arranged in the semiconductor substrate of the MOS device region; An epitaxial covering layer is formed on the surfaces of the source region and the drain region, wherein doping impurities are doped in the epitaxial covering layer; A metal silicide is formed on the surface of the epitaxial covering layer, wherein the dopant impurity is segregated to the interface between the metal silicide and the semiconductor material that the metal silicide contacts. 9. The semiconductor device according to claim 8, wherein the MOS device region comprises at least one of a PMOS device region and an NMOS device region; The doping impurities in the epitaxial cover layer of the PMOS device region include Sb and/or N; The doping impurities in the epitaxial covering layer of the NMOS device region include Ga and/or C. 10. The semiconductor device according to claim 8, wherein the dopant impurity segregates to the interface between the metal silicide and the source region and the metal silicide and the drain region ;or, The dopant impurity is segregated to the interface between the metal silicide and the epitaxial cladding layer. 11. The semiconductor device according to claim 8, wherein a stress layer is formed in the source region and the drain region, and the epitaxial covering layer is formed on a surface of the stress layer. 12. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 8 to 11.