CN108470678A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108470678A CN108470678A CN201810271146.8A CN201810271146A CN108470678A CN 108470678 A CN108470678 A CN 108470678A CN 201810271146 A CN201810271146 A CN 201810271146A CN 108470678 A CN108470678 A CN 108470678A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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Abstract
A kind of semiconductor structure and forming method thereof, wherein the forming method includes：Initial substrate structure is provided, the initial substrate structure includes the firstth area；The first photoresist is formed on the initial substrate structure surface；By the first dry lithography first groove is formed in first photoresist in firstth area；Form the first side wall for covering the first groove side wall；It is formed after the first groove and the first side wall, the first working process is carried out to the initial substrate structure as mask using first photoresist and the first side wall, forms substrat structure.The forming method can improve the performance of semiconductor structure while reducing process costs.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
Photoetching process is common technique in semiconductor technology, has important application in semiconductor technology.Photoetching process
Method include：Photoresist layer is formed on wafer using spin coating proceeding；Heat treatment is carried out to the photoresist layer and is placed on exposure
In equipment, the photoresist layer is exposed by exposure technology, the pattern on mask plate is transferred in photoresist layer；It connects
It and is heat-treated after being exposed to the photoresist layer after exposure, and developed by developing process, formed in photoresist layer
Photoengraving pattern.
With the rapid development of semiconductor fabrication, the direction of semiconductor devices towards high density, high integration is developed.
To photoetching process, more stringent requirements are proposed for the diminution of dimensions of semiconductor devices.
Immersed photoetching machine has the characteristics that high-resolution, can reduce the line width of litho pattern, therefore liquid immersion lithography
Extensive use in a lithographic process.However, it is expensive due to immersed photoetching machine, lead to the formation process of semiconductor structure
Cost is higher.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can reduce to form semiconductor junction
The process costs of structure, and improve the performance of semiconductor structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Initial substrate knot is provided
Structure, the initial substrate structure include the firstth area；The first photoresist is formed on the initial substrate structure surface；It is dry by first
Method photoetching forms first groove in first photoresist in firstth area；Form the first side for covering the first groove side wall
Wall；Formed after first side wall, using first photoresist and the first side wall as mask to the initial substrate structure into
The first working process of row forms substrat structure.
Optionally, the method for formation first side wall includes：In the first groove and the first photoresist table
Face forms the first contracting agent；First baking processing is carried out to first contracting agent, the first of first groove sidewall surfaces is made to receive
Contracting dosage form is at the first side wall；After the first baking processing, unreacted first contracting agent is removed.
Optionally, the material of first contracting agent includes water-soluble macromolecule and interlinkage molecule.
Optionally, the width of the first groove is greater than or equal to 35nm；The thickness of first side wall be 5nm~
15nm。
Optionally, the initial substrate structure includes substrate and the first graph layer positioned at the substrate surface；Described
The step of one working process includes：First is carried out to first graph layer as mask using first photoresist and the first side wall
Etching, the first pattern grooves are formed in first graph layer of the firstth area；It is formed after the first pattern grooves, removal described the
One photoresist and the first side wall.
Optionally, the number in firstth area is multiple, and the initial substrate structure further includes multiple secondth areas, described the
2nd area are alternately arranged with the firstth area；After removing first photoresist and the first side wall, the forming method further includes：Institute
It states initial substrate structure surface and forms the second photoresist；By the second dry lithography in second photoresist in secondth area shape
At second groove；Form the second side wall for covering the second groove side wall；The step of first working process further includes：Shape
After second groove and the second side wall, first graph layer is carried out as mask using second side wall and the second photoresist
Second etching, forms second graph groove in first graph layer of the secondth area, is formed after the second graph groove, gone
Except second photoresist and the second side wall.
Optionally, the step of formation second side wall includes：In the second groove and the second photoresist table
Face forms the second contracting agent；Second baking processing is carried out to second contracting agent, the second of second groove sidewall surfaces is made to receive
Contracting dosage form is at the second side wall；After the second baking processing, unreacted second contracting agent is removed.
Optionally, the initial substrate structure further includes：Hard mask layer between the substrate and the first graph layer.
Optionally, the forming method further includes：The first sacrificial layer is formed in first pattern grooves；Described
The second sacrificial layer is formed in two pattern grooves；It is formed after first sacrificial layer and the second sacrificial layer, removes first figure
Shape layer；It is mask to the hard mask layer using first sacrificial layer and the second sacrificial layer after removing first graph layer
Third etching is carried out, forms the first mask groove in the hard mask layer.
Optionally, the material of first sacrificial layer and first graph layer differs, second sacrificial layer and institute
The material for stating the first graph layer differs；The material of first sacrificial layer is silica, silicon nitride or silicon oxynitride；Described
The material of two sacrificial layers is silica, silicon nitride or silicon oxynitride；The material of first graph layer be silica, silicon nitride or
Silicon oxynitride.
Optionally, the forming method further includes：Second graph layer is formed in the first pattern grooves sidewall surfaces；Shape
After the second graph layer, first graph layer is removed；After removing first graph layer, with the second graph
Layer is that mask carries out the 4th etching to the hard mask layer, and the second mask groove is formed in the hard mask layer；Alternatively, described
Forming method further includes：Initial graphics layer is formed in first pattern grooves；In first graph layer and initial graphics
Initial light photoresist is formed on layer；The part initial light photoresist on initial graphics layer is removed, forms the on the initial graphics layer
Three photoresists and gap positioned at third photoresist both sides；The initial graphics layer is carried out using the third photoresist as mask
5th etching, forms third graph layer in first pattern grooves.
Optionally, the step of first dry lithography includes：First photoresist is exposed under gas atmosphere
After the exposure-processed, development treatment is carried out to first photoresist for light processing.
Compared with prior art, technical scheme of the present invention has the following advantages：
The forming method of the semiconductor structure of the present invention, the first photoresist by the first dry lithography in firstth area
Middle formation first groove.Since the cost of dry lithography technique is relatively low, so as to reduce the formation process of semiconductor structure
Cost.Before first working process, the first side wall for covering the first groove side wall is formed, then first side wall can be adjusted
The width for saving first groove, so as to adjust by the area in the region of the first working process in initial substrate structure, to have
Conducive to making the initial substrate structure region of the first working process of carry out meet design requirement, and then first processing can be improved
The precision of processing improves the performance of formed semiconductor structure.
Further, since the first groove side wall has the first side wall, the width of first pattern grooves can be reduced
Degree, therefore under conditions of distance between the center of adjacent first pattern grooves is certain, adjacent first pattern grooves can be made
Between spacing it is larger, to be conducive in first graph layer in secondth area formed second graph groove, so as to
Increase the density of pattern grooves in the first graph layer, and then the integrated level of formed semiconductor structure can be improved.
Further, since the first groove side wall has the first side wall, the thickness of adjusting first side wall can be passed through
Degree adjusts the width of the first pattern grooves, and then is easy to make the spacing in same first area between adjacent second graph layer to be equal to
The width of the first graph layer between adjacent first pattern grooves, and then the even width of the second mask groove can be made, improve
The performance of formed semiconductor structure.
Description of the drawings
Fig. 1 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific implementation mode
There are problems for the forming method of semiconductor structure, such as：The forming method cost of existing semiconductor structure
It is higher.
In the forming method of semiconductor structure, in order to reduce the line width of the exposure figure formed after photoetching, increase is formed
The integrated level of semiconductor structure carries out photoetching usually using immersed photoetching machine to photoresist.Immersed photoetching machine has higher
Resolution ratio, the smaller figure of line width can be formed, the resolution ratio of the immersed photoetching machine of the prior art is 36nm~55nm.So
And it is expensive due to immersed photoetching machine, cause the formation process cost of semiconductor structure higher.
In order to reduce the process costs to form semiconductor structure, photoetching can be carried out to photoresist by dry lithography machine.
However, since the resolution ratio of dry lithography machine is smaller, it is not easy to meet technological requirement.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, including：Described first
Beginning substrat structure surface forms the first photoresist；Is formed in first photoresist in firstth area by the first dry lithography
One groove；Form the first side wall for covering the first groove side wall；It is formed after the first groove and the first side wall, with institute
It is that mask carries out the first working process to the initial substrate structure to state the first photoresist and the first side wall.The forming method energy
Enough performances for improving semiconductor structure while reducing process costs.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Another structure sheaf of certain structure layer surface " be located at " in the embodiment of the present invention, " certain structure sheaf is located at another structure
" surface " in layer surface " and " forming another structure sheaf in certain structure layer surface " only indicates the position between two structure sheafs
Relationship can have other structures layer between double-layer structure layer.
Referring to FIG. 1, providing initial substrate structure 100, the initial substrate structure 100 includes the first area I.
In the present embodiment, the initial substrate structure 100 includes：Substrate 101；Hard positioned at 101 surface of the substrate is covered
Film layer 102；The first graph layer 103 positioned at 102 surface of the hard mask layer, the hard mask layer 102 are located at first figure
Between shape layer 103 and substrate 101.In other embodiments, the initial substrate structure can not include the first graph layer and hard
One or both of mask layer combines.
The substrate 101 is the semiconductors such as silicon substrate, germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator lining
Bottom.
In the present embodiment, the material of the hard mask layer 102 is titanium nitride or tantalum nitride.In other embodiments, described
The material of hard mask layer can be silica, silicon nitride or silicon oxynitride.
The material of the material and the hard mask layer 102 of first graph layer 103 differs.Specifically, the present embodiment
In, the material of first graph layer 103 is silica.In other embodiments, the material of first graph layer can be
Silicon nitride or silicon oxynitride.
Referring to FIG. 2, forming the first photoresist 110 on 100 surface of the initial substrate structure；Pass through the first dry lithography
First groove 111 is formed in the first photoresist 110 of the firstth area I.
First photoresist 110 is used as subsequently carrying out substrate 101 mask of first working process.
First groove 111 is formed in the first photoresist 110 of the firstth area I by the first dry lithography.Due to dry
Method etching machine bench price is relatively low, so as to reduce semiconductor structure formation process cost.
The step of first dry lithography includes：Place is exposed to first photoresist 110 under gas atmosphere
Reason；After the exposure-processed, development treatment is carried out to first photoresist 110.
It should be noted that since the resolution ratio of dry etching board is relatively low, be formed by the width of first groove 111 compared with
Greatly, by subsequently forming the first side wall in 111 side wall of first groove in the present embodiment, to make up dry etching board resolution ratio
Relatively low disadvantage so as to keep the width for the first pattern grooves being subsequently formed smaller, and then improves formed semiconductor junction
The integrated level of structure.
The width of the first groove 111 is the first groove 111 along the first area I and the II orientations of the secondth area
Size.
If the width of the first groove 111 is excessive, in order to keep the width for the first pattern grooves being subsequently formed smaller,
The thickness for the first side wall being then subsequently formed is larger, to be easy the technology difficulty that increase is subsequently formed the first side wall；By institute
It states first groove 111 to be formed by the first dry lithography, the resolution ratio of dry etching board is relatively low, therefore the first groove
111 width cannot be too small.Specifically, the width of the first groove 111 is greater than or equal to 35nm.
Due to the limitation of optical proximity effect, the distance between adjacent first trenches 111 cannot be too small；If adjacent first
The distance between groove 111 is excessive, is easily reduced the integrated level of formed semiconductor structure.Specifically, in the present embodiment, it is adjacent
The distance between first groove 111 selects suitable distance according to technological requirement.Specifically, in the present embodiment, adjacent first ditch
The distance between slot 111 is two times of used technique line width period.
Referring to FIG. 3, forming the first side wall 112 for covering 111 side wall of first groove.
First side wall 112 is used as subsequently carrying out initial substrate structure 100 mask of first working process.
Before first working process, form the first side wall 112 for covering 111 side wall of first groove, then described first
Side wall 112 can reduce the width of first groove 111, so as to adjust in initial substrate structure 100 by the first working process
Region area, and then the performance of formed semiconductor structure can be improved.
The step of forming the first side wall 112 include：In the first groove and the shape of first photoresist surface
At the first contracting agent；First baking processing is carried out to first contracting agent, makes the first contracting agent of first groove sidewall surfaces
Form the first side wall；After the first baking processing, unreacted first contracting agent is removed.
The material of first contracting agent includes water-soluble macromolecule and interlinkage molecule.
The step of forming the first side wall 112 further includes carrying out the first exposure imaging processing to first contracting agent.
Described first includes the step of baking processing：Before the first exposure imaging processing, to first contracting agent
(PAB) processing is baked after being bonded；After the first exposure imaging processing, dried after being exposed to first contracting agent
Roast (PEB) processing.
If the thickness of first side wall 112 is too small, it is unfavorable for reducing first pattern grooves being subsequently formed
Width to be unfavorable for reducing the width of the follow-up substrate for carrying out the first working process, and then is unfavorable for improving to be formed partly leading
The integrated level of body structure；If the thickness of first side wall 112 is excessive, it is easy to block the first groove 111.Specifically,
In the present embodiment, the thickness of first side wall 112 is 5nm~15nm, such as 10nm.
It is subsequently formed after the first groove 111, with first photoresist, 110 and first side wall 112 for mask pair
The initial substrate structure 100 carries out the first working process, forms substrat structure.
In the present embodiment, the forming method further includes：The is formed on the 100 second area surfaces II of the initial substrate structure
Two photoresists；By the second dry lithography second groove is formed in second photoresist；It is formed and covers the second groove
Second side wall of side wall.
The step of first working process includes：It is mask to institute with first photoresist, 110 and first side wall 112
It states the first graph layer 103 and carries out the first etching, the first pattern grooves are formed in first graph layer 103；Form the second ditch
It is that mask carries out the second etching to first graph layer 103 with second side wall, 142 and second photoresist 140 after slot,
Second graph groove is formed in first graph layer 103；The first sacrificial layer is formed in first pattern grooves；Institute
It states and forms the second sacrificial layer in second graph groove.
First working process, and form the second photoresist, second groove, the second side wall, the first pattern grooves, the
The step of two pattern grooves, the first sacrificial layer and the second sacrificial layer, is as shown in Fig. 4 to Fig. 9.
Referring to FIG. 4, (as shown in Figure 3) to cover with first photoresist 110 (as shown in Figure 3) and the first side wall 112
Film carries out the first etching to first graph layer 103, and the first pattern grooves 121 are formed in first graph layer 103；Shape
After first pattern grooves 121, first photoresist 110 and first side wall 112 are removed.
First etching is mask with first photoresist, 110 and first side wall 112, then is formed by the first figure
The width of groove 121 is less than the width of the first groove 111, specifically, the width of first pattern grooves 121 is equal to institute
The width for stating first groove 111 subtracts the width of twice of first side walls 112.Be formed by the width of the first pattern grooves 121 compared with
It is small, under conditions of the distance between the center of adjacent first pattern grooves 121 is certain, between adjacent first pattern grooves 121
Spacing it is larger, to be conducive to form second graph groove 122 in the first graph layer 103 of the secondth area II, to
The density of pattern grooves in the first graph layer 103 can be increased, and then the integrated level of formed semiconductor structure can be improved.
The technique of first etching includes the combination of one or both of dry etching or wet etching.
The technique for removing first photoresist 110 and first side wall 112 includes cineration technics or wet etching work
Skill.
The first sacrificial layer is subsequently formed in the first groove 111.
In the present embodiment, formed first sacrificial layer the step of it is as shown in Figure 5 and Figure 6.
Referring to FIG. 5, being formed just on first pattern grooves 121 (as shown in Figure 4) and first graph layer 103
Beginning sacrificial layer 120.
The initial sacrificial layer 120 is for being subsequently formed the first sacrificial layer 131.
In the present embodiment, after removing first photoresist 110, first sacrificial layer 131 is formed.
The material of the initial sacrificial layer 120 and the material of first graph layer 103 differ, and the initial sacrificial
The material of the material and the hard mask layer 102 of layer 120 differs.
In the present embodiment, the material of the initial sacrificial layer 120 is silicon nitride.In other embodiments, described initial sacrificial
The material of domestic animal layer can be silica or silicon oxynitride.
The technique for forming the initial sacrificial layer 120 includes chemical vapor deposition method, atom layer deposition process or physics
Gas-phase deposition.
Referring to FIG. 6, removing the initial sacrificial layer 120 on first graph layer 103, the first sacrificial layer 131 is formed.
First sacrificial layer 131 is used as the mask of hard mask layer 102 described in subsequent etching.
The technique for removing the initial sacrificial layer 120 on first graph layer 103 includes chemical mechanical milling tech.
It is subsequently formed after the first sacrificial layer 131, forms second in the first graph layer 103 of the secondth area II and sacrifice
Layer.
In the present embodiment, formed the second sacrificial layer 132 the step of it is as shown in Figure 7 to 10.
Referring to FIG. 7, protective layer 130 is formed on first graph layer 103 and first sacrificial layer 131, it is described
The material of protective layer 130 and the material of first sacrificial layer 131 differ.
The protective layer 130 is used to protect first sacrificial layer 131 in follow-up second etching process, prevents described first
Sacrificial layer 131 is removed.
The width of first sacrificial layer 131 is the first sacrificial layer 131 along the first area I and the II orientations of the secondth area
Size.
In the present embodiment, in order to improve the integrated level of formed semiconductor structure, the width of first sacrificial layer 131 compared with
It is small, it is easily removed in subsequent second etching, therefore before second etching, form the protective layer 130.At other
The protective layer can not be formed in embodiment.
In the present embodiment, the material identical of the material of the protective layer 130 and first graph layer 103.The protection
The material identical of the material and first graph layer 103 of layer 130, can be by identical technological parameter to the protective layer
130 and first graph layer 103 perform etching.In other embodiments, the material of the protective layer and first graph layer
Material can differ.
Specifically, the material of the protective layer 130 is silica.
Referring to FIG. 8, forming the second photoresist 140 on first graph layer 103；By the second dry lithography in institute
It states in second the second photoresists of area II 140 and forms second groove；Form the second side wall 142 for covering the second groove side wall.
Second side wall 142 is formed, the size for the second graph groove 122 being subsequently formed can be made smaller, so as to
Enough prevent first pattern grooves 121 and 122 break-through of second graph groove.
In the present embodiment, formed the second side wall 142 the step of include：In the second groove 141 and described the
Two photoresists, 140 surface forms the second contracting agent；Second baking processing is carried out to second contracting agent, makes second groove 141
Second contracting agent of sidewall surfaces forms the second side wall；After the second baking processing, unreacted second contracting agent is removed.
The step of forming second side wall further include：Second exposure imaging processing is carried out to second contracting agent.
Described second includes the step of baking processing：Before the processing of second exposure imaging, second contracting agent is carried out
(PAB) processing is baked after second bonding；After the processing of second exposure imaging, dried after carrying out the second exposure to second contracting agent
Roast (PEB) processing.
The material of second contracting agent includes water-soluble macromolecule and cross linking agent.
To prevent the first pattern grooves 121 and 122 break-through of second graph groove, the width of the second graph groove 122
Less than the spacing between adjacent first pattern grooves 121.In the present embodiment, width and the first groove 111 of the second groove
It is of same size.
In the present embodiment, the width of the second groove is of same size with first groove 111.Second side wall 142
Width and the first side wall 112 it is of same size, the even width of the device formed in successive substrates can be made, same technique
Line width is consistent.
In other embodiments, the width of the second groove and the width of first groove can differ；Described second
The width of side wall and the width of the first side wall can differ.
In other embodiments, the second groove can be formed by immersion lithography process with filtered air；Described second is not formed
Side wall.
Referring to FIG. 9, being formed after second groove, with second side wall 142 (as shown in Figure 8) and the second photoresist
140 it is (as shown in Figure 8) for mask to first graph layer 103 carry out second etching, formed in first graph layer 103
Second graph groove 122；It is formed after the second graph groove 122, removes 140 and second side wall of the second photoresist
142。
The technique of second etching includes the combination of one or both of wet-etching technology or dry etch process.
In the present embodiment, second etching also performs etching the protective layer 130, the shape in the protective layer 130
At protection groove.
In the present embodiment, the technique for removing 140 and second side wall 142 of the second photoresist includes cineration technics or wet method
Etching technics.
Referring to FIG. 10, forming the second sacrificial layer 132 in the second graph groove 122 (as shown in Figure 9).
Second sacrificial layer 132 is used as the mask of follow-up first working process.
Second sacrificial layer 132 is also located in the protection groove.
In the present embodiment, remove second photoresist 140 (as shown in Figure 8) and the second side wall 142 (as shown in Figure 8) it
Afterwards, the second sacrificial layer 132 is formed.
In the present embodiment, the material identical of the material of second sacrificial layer 132 and first sacrificial layer 131.At it
In his embodiment, the material of second sacrificial layer and the material of first sacrificial layer can differ.
In the present embodiment, the width of second sacrificial layer 132 is of same size with first sacrificial layer 131.
1 is please referred to Fig.1, is formed after second sacrificial layer 132, removes first graph layer 103 (such as Figure 10 institutes
Show).
The technique for removing first graph layer 103 includes：One or both of dry etching or wet etching combine.
Before removing first graph layer 103, further include：Remove the protective layer 130.
In the present embodiment, is formed after second sacrificial layer 132, remove the protective layer 130.In other embodiment
In, the material of the protective layer and first graph layer differs, and is differed with the material of the mask layer, then can be with shape
After second graph groove, is formed before the second sacrificial layer, remove the protective layer.
Please refer to Fig.1 2, with first sacrificial layer, 131 and second sacrificial layer 132 be mask to the hard mask layer 102
Third etching is carried out, forms the first mask groove 150 in the hard mask layer 102；After third etching, removal described first
Sacrificial layer 131 (as shown in figure 11) and the second sacrificial layer 132 (as shown in figure 11).
Mask layer with the first mask groove 150 is used as subsequently carrying out substrate 101 mask of second working process.
The technique for removing first sacrificial layer, 131 and second sacrificial layer 132 includes in dry etching or wet etching
One or two combination.
It is formed after the first mask groove 150, the step of first working process further includes：With the hard mask
Layer 102 carries out the second working process for mask to the substrate.
In the present embodiment, second working process in the substrate 101 for forming isolated groove；Described second adds
The technique of work processing includes etching technics.The forming method further includes：Isolation structure is formed in the isolation trench.
In other embodiments, second working process in the substrate 101 for forming active area.Described second
The technique of working process includes ion implantation technology.
Further include removing the hard mask layer 102 after second working process.
It should be noted that in the present embodiment, since 111 side wall of the first groove has the first side wall 112, can subtract
The width of small first pattern grooves 121, therefore the item that distance between the center of adjacent first pattern grooves 121 is certain
Under part, the spacing between adjacent first pattern grooves 121 is larger, to be conducive to the first graph layer in the secondth area II
Second graph groove 122 is formed in 103, so as to increase the density of pattern grooves in the first graph layer 103, and then can be carried
The integrated level of high formed semiconductor structure.
In the present embodiment, the method for forming the second graph groove 122 is Double-patterning method, the second graph
The width of groove 122 is greater than or equal to 35nm.In other embodiments, the method for forming the second graph groove can be three
The heavy graphical or patterned method of quadruple, then the width of the second graph groove is less than 35nm.
The embodiment of the present invention also provides the forming method of another semiconductor structure, the forming method and Fig. 1 to Figure 12
Something in common, this will not be repeated here, and difference includes：
The initial substrate includes the hard mask layer between first graph layer and substrate；
The forming method includes：After removing first photoresist and the first side wall, in first pattern grooves
Sidewall surfaces form second graph layer；It is formed after the second graph layer, removes first graph layer；Remove described first
After graph layer, the 4th etching is carried out to the hard mask layer using the second graph layer as mask, in the hard mask layer
Form the second mask groove.
Since the first groove side wall has the first side wall, the can be adjusted by adjusting the thickness of first side wall
The width of one pattern grooves, and then it is easy to make the spacing in same first area between adjacent second graph layer to be equal to adjacent first
The width of the first graph layer between pattern grooves, and then the even width of the second mask groove can be made, improvement forms half
The performance of conductor structure.
The embodiment of the present invention also provides the forming method of another semiconductor structure, the forming method and Fig. 1 to Figure 12
Something in common, this will not be repeated here, and difference includes：
The forming method includes：Initial graphics layer is formed in first pattern grooves；In first graph layer
With initial light photoresist is formed on initial graphics layer；The part initial light photoresist on initial graphics layer is removed, in the initial graphics
Third photoresist and the gap positioned at third photoresist both sides are formed on layer；It is mask to described initial using the third photoresist
Graph layer carries out the 5th etching, and third graph layer is formed in first pattern grooves.
In the present embodiment, the part initial light photoresist on initial graphics layer is removed by third dry lithography.Dry lithography
Cost is relatively low, so as to process costs.In other embodiments, initial graphics layer can be removed by immersion lithography process with filtered air
On part initial light photoresist.
In the present embodiment, before the 5th etching, further include：Third side wall is formed in the gap sidewall surfaces.Described
Five etchings are also using the third side wall as mask.
The width of the third graph layer can be adjusted in the third side wall, and then improves formed semiconductor junction
The performance of structure.
In other embodiments, the third side wall can not be formed.
Above example is illustrated by taking Dual graphing as an example, in other embodiments, forms the figure ditch
The method of slot can also be that single is graphical, the triple graphical or patterned methods of quadruple.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Initial substrate structure is provided, the initial substrate structure includes the firstth area；
The first photoresist is formed on the initial substrate structure surface；
By the first dry lithography first groove is formed in first photoresist in firstth area；
Form the first side wall for covering the first groove side wall；
Formed after first side wall, using first photoresist and the first side wall as mask to the initial substrate structure into
The first working process of row forms substrat structure.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the method for forming first side wall
Including：In the first groove and first photoresist surface forms the first contracting agent；First contracting agent is carried out
First baking is handled, and the first contracting agent of first groove sidewall surfaces is made to form the first side wall；After the first baking processing,
Remove unreacted first contracting agent.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the material packet of first contracting agent
Include water-soluble macromolecule and interlinkage molecule.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the width of the first groove is more than
Or it is equal to 35nm；The thickness of first side wall is 5nm~15nm.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the initial substrate structure includes lining
Bottom and the first graph layer positioned at the substrate surface；The step of first working process includes：With first photoresist
It is that mask carries out the first etching to first graph layer with the first side wall, first is formed in first graph layer of the firstth area
Pattern grooves；It is formed after the first pattern grooves, removes first photoresist and the first side wall.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the number in firstth area is more
A, the initial substrate structure further includes multiple secondth areas, and secondth area and the firstth area are alternately arranged；
After removing first photoresist and the first side wall, the forming method further includes：In the initial substrate structure table
Face forms the second photoresist；By the second dry lithography second groove is formed in second photoresist in secondth area；It is formed
Cover the second side wall of the second groove side wall；
The step of first working process further includes：Formed after second groove and the second side wall, with second side wall and
Second photoresist is that mask carries out the second etching to first graph layer, and second is formed in first graph layer of the secondth area
Pattern grooves are formed after the second graph groove, and second photoresist and the second side wall are removed.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the step of forming second side wall
Including：In the second groove and second photoresist surface forms the second contracting agent；Second contracting agent is carried out
Second baking is handled, and the second contracting agent of second groove sidewall surfaces is made to form the second side wall；After the second baking processing,
Remove unreacted second contracting agent.
8. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the initial substrate structure also wraps
It includes：Hard mask layer between the substrate and the first graph layer.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the forming method further includes：
The first sacrificial layer is formed in first pattern grooves；The second sacrificial layer is formed in the second graph groove；Described in formation
After first sacrificial layer and the second sacrificial layer, first graph layer is removed；After removing first graph layer, with described
One sacrificial layer and the second sacrificial layer are that mask carries out third etching to the hard mask layer, and first is formed in the hard mask layer
Mask groove.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that first sacrificial layer with it is described
The material of first graph layer differs, and the material of second sacrificial layer and first graph layer differs；
The material of first sacrificial layer is silica, silicon nitride or silicon oxynitride；The material of second sacrificial layer is oxidation
Silicon, silicon nitride or silicon oxynitride；The material of first graph layer is silica, silicon nitride or silicon oxynitride.
11. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the forming method further includes：
The first pattern grooves sidewall surfaces form second graph layer；It is formed after the second graph layer, removes first figure
Shape layer；After removing first graph layer, the 4th etching is carried out to the hard mask layer using the second graph layer as mask,
The second mask groove is formed in the hard mask layer；
Alternatively, the forming method further includes：Initial graphics layer is formed in first pattern grooves；In first figure
Initial light photoresist is formed on layer and initial graphics layer；The part initial light photoresist on initial graphics layer is removed, in the initial graph
Third photoresist and the gap positioned at third photoresist both sides are formed on shape layer；Using the third photoresist be mask to it is described just
Beginning graph layer carries out the 5th etching, and third graph layer is formed in first pattern grooves.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of first dry lithography
Suddenly include：Processing is exposed to first photoresist under gas atmosphere, after the exposure-processed, to first light
Photoresist carries out development treatment.
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| CN110707004A (en) * | 2018-10-11 | 2020-01-17 | 联华电子股份有限公司 | Semiconductor device and method of forming the same |
| CN110783189A (en) * | 2019-09-23 | 2020-02-11 | 珠海格力电器股份有限公司 | Preparation method of chip groove and preparation method of chip |
| CN111799150A (en) * | 2019-04-08 | 2020-10-20 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN112133706A (en) * | 2019-06-25 | 2020-12-25 | 上海箩箕技术有限公司 | Semiconductor structure and forming method thereof |
| CN113113349A (en) * | 2020-01-10 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN114823485A (en) * | 2021-01-22 | 2022-07-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN115347090A (en) * | 2022-08-31 | 2022-11-15 | 北京北方华创微电子装备有限公司 | Preparation method of nanoscale patterned substrate and nanoscale patterned substrate |
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