CN108494232B - A kind of synchronous commutating control circuit for preventing electric current from flowing backward - Google Patents

Abstract

The invention relates to a synchronous rectification control circuit for preventing current backfeeding, which belongs to the technical field of electronic circuits. It includes a voltage detection module, a logic control module and a drive module. The voltage detection module is used to detect the voltage difference between the drain and source of the external rectifier, and judge the state of the parasitic diode of the rectifier. The logic control module generates the minimum conductance of the rectifier. On-time and blanking time, and at the same time detect the current polarity of the rectifier tube during the minimum on-time, avoid current backflow phenomenon during the minimum on-time, and also avoid the oscillation of the rectifier tube driving waveform under the condition of small current, the drive module is used It is used to provide the gate drive of the rectifier. The control circuit provided by the invention is safe and reliable, and at the same time can realize lower conduction loss, improve the overall efficiency of the generator, and play the role of saving energy and being clean and environment-friendly.

Description

A Synchronous Rectification Control Circuit Preventing Current Backflow

technical field

The invention belongs to the field of switching power supplies, and in particular relates to a control circuit for a rectifier circuit used for motor power generation.

Background technique

At present, the generator rectifier mainly uses silicon diodes as rectification elements. The forward voltage drop of silicon diodes is about 0.3-1V, and the on-state power consumption is very large when the current is high. With the popularization of automobiles, the power consumption caused by silicon diode rectification cannot be ignored.

Synchronous rectification technology (Synchronous Rectification, SR) uses a low-voltage power metal-oxide semiconductor field effect transistor (Power MOSFET) as a rectifier device, and its channel on-state resistance can be used to reduce the overall power consumption of the rectifier module. The main difficulty of using synchronous rectification technology lies in the grid control of the rectifier tube. If the polarity of the current flowing through the rectifier tube changes suddenly, there is a current path from the input/output port to the battery or ground plane, which constitutes backflow, which may Cause damage to the rectifier and control circuits.

The drive of the rectifier mainly adopts the pulse width modulation PWM method, and its implementation is relatively complicated, and it is necessary to establish a space vector mathematical model and perform complex transformation solutions. Therefore, a large amount of logic processing is required in the circuit composition, which increases technical difficulty and cost; The generator is affected by the speed of the car, which increases the difficulty of the control algorithm, and the application cost is too high, which is not conducive to the popularization of synchronous rectification technology.

Contents of the invention

The purpose of the present invention is to propose a control circuit for the rectification circuit used to control motor power generation, which has a simple structure and low power consumption, in view of the problems of high technical difficulty, high cost and high power consumption in the current synchronous rectification technology. The overall efficiency of the motor can be improved, and current backflow can be prevented, so that the rectification circuit is safer and more reliable.

Technical scheme of the present invention is:

A synchronous rectification control circuit for preventing current backflow, used for controlling rectifier tubes in a synchronous rectification system, including a voltage detection module, a logic control module and a drive module,

The voltage detection module is used to detect the drain-source voltage of the rectifier and generate a first detection signal, a second detection signal, a third detection signal and a fourth detection signal;

The voltage detection module includes a fourth NDMOS transistor M4, a fourth comparator Comp4 and a fourth voltage source, the non-inverting input terminal of the fourth comparator Comp4 is connected to the source of the fourth NDMOS transistor M4, and the inverting input terminal of the fourth comparator Comp4 is connected to the fourth The positive end of the voltage source, the output end of which outputs the fourth detection signal; the gate of the fourth NDMOS transistor M4 is connected to the power supply voltage, and its drain is connected to the drain of the rectifier tube; the negative end of the fourth voltage source connecting the source of the rectifier;

The logic control module includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a first counter Counter1, and a second counter Counter2 , the first inverter G1, the second inverter G2, the third inverter G5, the fourth inverter G7, the fifth inverter G9, the sixth inverter G13, the seventh inverter G14, The first NOR gate G3, the second NOR gate G4, the third NOR gate G6, the fourth NOR gate G8, the fifth NOR gate G11, the first NAND gate G10, the second NAND gate G12, the An AND gate G15, a first monostable flip-flop and a second monostable flip-flop,

The input terminal of the second inverter G2 is connected to the first detection signal, and the output terminal thereof is connected to the first input terminal of the first NOR gate G3;

The input terminal of the first inverter G1 is connected to the enable signal ENA, and the output terminal thereof is connected to the second input terminal of the first NOR gate G3;

The clock terminal of the first D flip-flop D1 is connected to the clock terminal of the second D flip-flop D2, the first input terminal of the second NOR gate G4 and the output terminal of the first NOR gate G3, and its reset terminal is connected to the seventh inverter The output terminal of the device G14, its Q output terminal is connected to the second input terminal of the second NOR gate G4, and its Q non-output terminal is connected to the first input terminal of the third NOR gate G6;

The reset terminal of the second D flip-flop D2 is connected to the enable signal ENA, and its Q non-output terminal is connected to the second input terminal of the third NOR gate G6 and the third input terminal of the second NOR gate G4; the second OR The output terminal of the NOT gate G4 is connected to the input terminal of the third inverter G5, the reset terminal of the third D flip-flop D3, the fourth D flip-flop D4 and the fifth D flip-flop D5;

The enabling terminal of the first counter Counter1 is connected to the output terminal of the third NOR gate G6, its clock terminal is connected to the clock signal, and its maximum bit output is connected to the input terminal of the seventh inverter G14;

The enabling terminal of the second counter Counter2 is connected to the output terminal of the fifth NOR gate G11, its clock terminal is connected to the clock signal, and its maximum bit output is connected to the input terminal of the fifth inverter G9;

The input terminal of the fourth inverter G7 is connected to the second detection signal, and the output terminal thereof is connected to the first input terminal of the fourth NOR gate G8;

The second input terminal of the fourth NOR gate G8 is connected to the output terminal of the fifth inverter G9, and its output terminal is connected to the clock terminal of the third D flip-flop D3;

The input terminal of the first monostable flip-flop is connected to the third detection signal, and its output terminal is connected to the clock terminal of the fourth D flip-flop D4;

The first input end of the first NAND gate G10 is connected to the Q non-output end of the third D flip-flop D3, and its second input end is connected to the Q output end of the fourth D flip-flop D4;

The first input end of the fifth NOR gate G11 is connected to the output end of the third inverter G5, its second input end is connected to the output end of the first NAND gate G10, and its output end is connected to the second NAND gate G12. An input terminal and the first input terminal of the first AND gate G15;

The second input end of the second NAND gate G12 is connected to the Q non-output end of the fifth D flip-flop D5, and its output end is connected to the input end of the sixth inverter G13;

The second input terminal of the first AND gate G15 is connected to the output terminal of the fifth inverter G9, and its output terminal is connected to the reset terminal of the fourth comparator Comp4 in the voltage detection module;

The input terminal of the second monostable flip-flop is connected to the fourth detection signal, and its output terminal is connected to the clock terminal of the fifth D flip-flop D5;

The data input ends of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4 and the fifth D flip-flop D5 are connected to the power supply voltage;

The input end of the driving module is connected to the output end of the sixth inverter G13, and the output end thereof is connected to the gate of the rectifier tube.

Specifically, the voltage detection module further includes a first comparator Comp1, a second comparator Comp2, a third comparator Comp3, a first voltage source, a second voltage source, a third voltage source, a first NDMOS transistor M1, a first Two NDMOS transistors M2 and a third NDMOS transistor M3,

The drains of the first NDMOS transistor M1, the second NDMOS transistor M2 and the third NDMOS transistor M3 are all connected to the drains of the rectifier transistors, and the gates thereof are all connected to the power supply voltage;

The non-inverting input terminal of the first comparator Comp1 is connected to the source of the first NDMOS transistor M1, the inverting input terminal thereof is connected to the positive terminal of the first voltage source, and the output terminal thereof outputs the first detection signal;

The non-inverting input terminal of the second comparator Comp2 is connected to the source of the second NDMOS transistor M2, its inverting input terminal is connected to the positive terminal of the second voltage source, and its output terminal outputs the second detection signal;

The non-inverting input terminal of the third comparator Comp3 is connected to the source of the third NDMOS transistor M3, the inverting input terminal thereof is connected to the positive terminal of the third voltage source, and the output terminal thereof outputs the third detection signal;

The reset terminals of the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3 are connected to the output terminal of the second NOR gate G4 in the voltage detection module;

Negative terminals of the first voltage source, the second voltage source and the third voltage source are connected to the source of the rectifier tube.

Specifically, the clock signal is generated by an oscillator OSC, and the oscillator OSC generates a square wave signal with an oscillation frequency of 320Khz as the clock signal.

Specifically, the first monostable flip-flop and the second monostable flip-flop have the same structure,

The first monostable flip-flop includes an eighth inverter G16, a ninth inverter G17, a tenth inverter G18 and a sixth NOR gate G19,

The input terminal of the eighth inverter G16 is connected to the first input terminal of the sixth NOR gate G19 and serves as the input terminal of the first monostable flip-flop;

The input end of the ninth inverter G17 is connected to the output end of the eighth inverter G16, and the output end thereof is connected to the input end of the tenth inverter G18;

The second input terminal of the sixth NOR gate G19 is connected to the output terminal of the tenth inverter G18, and the output terminal thereof serves as the output terminal of the first monostable flip-flop.

Specifically, the first counter Comp1 and the second counter Comp2 are composed of cascaded D flip-flops.

Specifically, the driving module includes an even number of cascaded inverters.

The beneficial effects of the present invention are as follows: the control circuit proposed by the present invention is used to control the rectification circuit of the motor to generate electricity, has a simple structure, can greatly reduce the power consumption of the rectification circuit, reduces the temperature of the rectification bridge, and improves the reliability of the system; The lower conduction loss can improve the overall efficiency of the generator, save energy, and be clean and environmentally friendly; at the same time, the rectifier circuit is safer and more reliable through the anti-current backflow circuit.

Description of drawings

FIG. 1 is a schematic structural diagram of a synchronous rectification control circuit for preventing current backfeeding proposed by the present invention.

Fig. 2 is a schematic diagram of the internal structure of the first monostable flip-flop given in the embodiment.

FIG. 3 is a working flowchart of a synchronous rectification control circuit for preventing current backfeeding proposed by the present invention.

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

The present invention proposes a synchronous rectification control circuit for preventing current backfeeding, which is used to control the rectifier in the synchronous rectification system. The working principle of the present invention will be described in detail below using a power MOSFET as the rectifier as an example.

As shown in Figure 1, the control circuit proposed by the present invention includes a voltage detection module, a logic control module and a drive module, and generates a control signal to control the power MOSFET on and off by detecting the drain-source voltage difference of the power MOSFET, wherein the voltage detection The module is used to detect the voltage difference between the drain and source of the external power MOSFET, and judge the state of the parasitic diode of the power MOSFET. The logic control module generates the minimum conduction time and blanking time of the power MOSFET, and detects the power within the minimum conduction time The current polarity of the MOSFET avoids the phenomenon of current backflow during the minimum on-time, and also avoids the oscillation of the power MOSFET driving waveform under the condition of small current. The driving module is used to provide the gate drive of the power MOSFET.

The voltage detection module is used to detect the drain-source voltage of the rectifier and generate the first detection signal, the second detection signal, the third detection signal and the fourth detection signal; a realization circuit structure of the voltage detection circuit is shown in Fig. 1, Including the first comparator Comp1, the second comparator Comp2, the third comparator Comp3, the fourth comparator Comp4, the first voltage source, the second voltage source, the third voltage source, the fourth voltage source, the first NDMOS transistor M1 , the second NDMOS transistor M2, the third NDMOS transistor M3 and the fourth NDMOS transistor M4, the drains of the first NDMOS transistor M1, the second NDMOS transistor M2, the third NDMOS transistor M3 and the fourth NDMOS transistor M4 are all connected to the rectifier The drain and its gate are both connected to the power supply voltage; the non-inverting input terminal of the first comparator Comp1 is connected to the source of the first NDMOS transistor M1, its inverting input terminal is connected to the positive terminal of the first voltage source, and its output terminal outputs the first A detection signal; the noninverting input terminal of the second comparator Comp2 is connected to the source of the second NDMOS transistor M2, its inverting input terminal is connected to the positive terminal of the second voltage source, and its output terminal outputs the second detection signal; the third comparator The noninverting input terminal of the comparator Comp3 is connected to the source of the third NDMOS transistor M3, its inverting input terminal is connected to the positive terminal of the third voltage source, and its output terminal outputs the third detection signal; the noninverting input terminal of the fourth comparator Comp4 is connected to The source of the fourth NDMOS transistor M4, its inverting input terminal is connected to the positive terminal of the fourth voltage source, and its output terminal outputs the fourth detection signal; the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3 The reset end of the reset terminal is connected to the output end of the second NOR gate G4 in the voltage detection module; the reset end of the fourth comparator Comp4 is connected to the output end of the first AND gate G15 in the voltage detection module; the first voltage source, the second voltage source, Negative terminals of the third voltage source and the fourth voltage source are connected to the source of the rectifier.

Wherein the first comparator Comp1, the second comparator Comp2, the third comparator Comp3 and the fourth comparator Comp4 are voltage comparators, the comparison voltage of the first comparator Comp1 is reset threshold voltage V _TH3 , the second comparator Comp2 The comparison voltage is the turn-off threshold voltage V _TH2 , the comparison voltage of the third comparator Comp3 is the turn-on threshold voltage V _TH1 , and the comparison voltage of the fourth comparator Comp4 is the backfeed threshold voltage V _TH4 . The turn-on threshold voltage V _TH1 , the turn-off threshold voltage V _TH2 , the reset threshold voltage V _TH3 and the backflow threshold voltage V _TH4 can be set by adjusting the voltage source.

As shown in Figure 1, the logic control module includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a first counter Counter1, The second counter Counter2, the first inverter G1, the second inverter G2, the third inverter G5, the fourth inverter G7, the fifth inverter G9, the sixth inverter G13, the seventh inverter Phase device G14, first NOR gate G3, second NOR gate G4, third NOR gate G6, fourth NOR gate G8, fifth NOR gate G11, first NAND gate G10, second NAND gate Gate G12, the first AND gate G15, the first monostable flip-flop and the second monostable flip-flop, the input end of the second inverter G2 is connected to the first detection signal, and its output end is connected to the first NOR gate G3 The first input end of the first inverter G1; the input end of the first inverter G1 is connected to the enable signal ENA, and its output end is connected to the second input end of the first NOR gate G3; the clock end of the first D flip-flop D1 is connected to the second D The clock terminal of flip-flop D2, the first input terminal of the second NOR gate G4 and the output terminal of the first NOR gate G3, its reset terminal is connected to the output terminal of the seventh inverter G14, and its Q output terminal is connected to the second The second input terminal of the NOR gate G4, its Q non-output terminal is connected to the first input terminal of the third NOR gate G6; the reset terminal of the second D flip-flop D2 is connected to the enable signal ENA, and its Q non-output terminal is connected to the first input terminal of the third NOR gate G6; The second input end of the three NOR gate G6 and the third input end of the second NOR gate G4; the output end of the second NOR gate G4 is connected to the input end of the third inverter G5, the third D flip-flop D3, The reset terminal of the fourth D flip-flop D4 and the fifth D flip-flop D5; the enable terminal of the first counter Counter1 is connected to the output terminal of the third NOR gate G6, its clock terminal is connected to the clock signal, and its maximum bit output is connected to the seventh The input terminal of the inverter G14; the enabling terminal of the second counter Counter2 is connected to the output terminal of the fifth NOR gate G11, its clock terminal is connected to the clock signal, and its maximum bit output is connected to the input terminal of the fifth inverter G9; The input end of four inverters G7 is connected to the second detection signal, and its output end is connected to the first input end of the fourth NOR gate G8; the second input end of the fourth NOR gate G8 is connected to the output of the fifth inverter G9 end, its output end is connected to the clock end of the third D flip-flop D3; the input end of the first monostable flip-flop is connected to the third detection signal, and its output end is connected to the clock end of the fourth D flip-flop D4; the first NAND The first input end of the gate G10 is connected to the Q non-output end of the third D flip-flop D3, and its second input end is connected to the Q output end of the fourth D flip-flop D4; the first input end of the fifth NOR gate G11 is connected to the first The output end of the three inverter G5, its second input end is connected to the output end of the first NAND gate G10, and its output end is connected to the first input end of the second NAND gate G12 and the first input end of the first AND gate G15 end; the second input end of the second NAND gate G12 is connected to the Q non-output end of the fifth D flip-flop D5, and its output end is connected to the input end of the sixth inverter G13; the second input end of the first AND gate G15 Connect the fifth inverter G The output terminal of 9 is connected to the reset terminal of the fourth comparator Comp4 in the voltage detection module; the input terminal of the second monostable flip-flop is connected to the fourth detection signal, and its output terminal is connected to the clock of the fifth D flip-flop D5 terminal; the data input terminals of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4 and the fifth D flip-flop D5 are connected to the power supply voltage; the sixth inverter G13 The output terminal is connected to the input terminal of the drive module.

The drive module includes an output stage power driver B0, wherein the input terminal of the output stage power driver B0 is connected to the output terminal of the sixth inverter G13 as the input terminal of the drive module, and its output terminal is connected to the gate of the rectifier tube as the output terminal of the drive module , the output stage power driver B0 can be composed of an even number of cascaded inverters.

In some embodiments, the clock signal can be generated by the oscillator OSC, for example, the oscillator OSC is used to generate a square wave signal with an oscillation frequency of 320Khz as the clock signal.

The number of bits of the first counter Comp1 and the second counter Comp2 can be adjusted according to design requirements, and the counting time can also be set arbitrarily. The first counter Comp1 and the second counter Comp2 can be formed by cascading D flip-flops.

The first monostable flip-flop and the second monostable flip-flop can have the same structure, as shown in Figure 2, a circuit implementation form of the first monostable flip-flop is provided, including the eighth inverter G16 , the ninth inverter G17, the tenth inverter G18 and the sixth NOR gate G19, the input end of the eighth inverter G16 is connected to the first input end of the sixth NOR gate G19 and acts as the first monostable The input end of the flip-flop; the input end of the ninth inverter G17 is connected to the output end of the eighth inverter G16, and its output end is connected to the input end of the tenth inverter G18; the second input end of the sixth NOR gate G19 The terminal is connected to the output terminal of the tenth inverter G18, and its output terminal is used as the output terminal of the first monostable flip-flop.

The first comparator Comp1, the first D flip-flop D1, the second D flip-flop D2, the first counter Counter1, the second inverter G2, the third inverter G5, the seventh inverter G14, the second NOR The gate G4 and the third NOR gate G6 form a reset logic circuit. When the detected power MOSFET drain-source voltage difference is greater than the reset threshold voltage V _TH3 , the first counter Counter1 starts counting. During this period, all logic and comparators on the chip reset.

The second voltage comparator Comp2, the fourth inverter G7, the fifth inverter G9, the third NOR gate G8, the third D flip-flop D3 and the second counter Counter2 form a minimum on-time circuit, when the detected When the drain-source voltage difference of the power MOSFET is less than the turn-on threshold voltage V _TH1 , the power MOSFET is turned on, and the second counter Counter2 starts counting. When the highest bit output MSB of the second counter Counter2 becomes high, the second comparator Comp2 starts to detect whether the power MOSFET is reaches the turn-off threshold voltage V _TH2 .

The third comparator Comp3, the first monostable flip-flop, the fourth D flip-flop D4, the first NAND gate G10 and the fifth NOR gate G11 constitute a circuit for judging and turning on the power MOSFET, when the detected power MOSFET meets the turning-on condition , that is, when the detected drain-source voltage difference of the power MOSFET is less than the turn-on threshold voltage V _TH1 , the first monostable flip-flop generates a high pulse with a narrower width, the fourth D flip-flop D4 flips, and the output stage power drives B0 to turn on Power MOSFETs.

The fourth comparator Comp4, the second monostable flip-flop, the fifth D flip-flop D5 and the first AND gate G15 form an anti-current backflow circuit. Once the power MOSFET is turned on, the second counter Counter2 starts counting, and the power MOSFET is forced to turn on The second counter Counter2 counts the time during which the fourth comparator Comp4 detects the polarity of the current flowing through the open MOSFET.

Figure 3 is the working flow chart of the present invention, a kind of synchronous rectification control circuit provided by the present invention is integrated into the chip, when the enable signal EN is high (that is, the pin is enabled), the control circuit starts to work (that is, enters preparation mode), while detecting whether the chip power supply voltage (that is, the power supply voltage V _DD ) and the ambient temperature are normal; when the power supply voltage and the ambient temperature meet the conditions, the first comparator Comp1 waits for the reset signal (that is, the drain-source voltage difference of the power MOSFET is greater than the reset threshold voltage V _TH3 ), when the detected drain-source voltage difference of the power MOSFET is greater than the reset threshold voltage V _TH3 , all logics of the chip are reset and the first counter Counter1 is triggered to count, and all logics do not work during this period; after the first counter Counter1 After the counting time, the first comparator Comp1 and the logic circuit detect whether the drain-source voltage difference of the power MOSFET is between the turn-off threshold voltage V _TH2 and the reset threshold voltage V _TH3 . If the condition is met, the logic exits reset and starts to detect the drain-source voltage of the power MOSFET. Whether the difference meets the conduction condition (that is, the drain-source voltage difference of the power MOSFET is less than the turn-on threshold voltage V _TH1 ); when the third comparator Comp3 detects that the drain-source voltage difference of the power MOSFET is less than the turn-on threshold voltage V _TH1 , the power MOSFET is turned on, and the first 2. Counter2 starts counting, the power MOSFET is forced to turn on, shielding the second comparator Comp2 from detecting the power MOSFET drain-source voltage difference, the fourth comparator Comp4 starts to detect the polarity of the current flowing through the power MOSFET, and uses the fourth comparator Comp4 to detect the power Whether the drain-source voltage difference of the MOSFET reaches the backflow threshold voltage V _TH4 , if the backflow threshold voltage V _TH4 is not reached, it means that the current backflow does not occur at this time, then the second comparator Comp2 starts to detect the power MOSFET drain-source voltage after the second counter Counter2 is full If the difference is greater than the turn-off threshold voltage V _TH2 , if the power MOSFET drain-source voltage difference meets the conditions, the power MOSFET will be turned off; the fourth comparator Comp4 detects that the power MOSFET drain-source voltage difference reaches the back-feeding threshold voltage V _TH4 , which means that the current back-feeding phenomenon occurs at this time , then turn off the power MOSFET immediately; then start to wait for the reset signal Reset, and enter the above process again when the next reset signal Reset comes.

In summary, the present invention proposes a control circuit for controlling the rectification circuit of the motor to generate electricity, and detects whether the body diode of the power MOSFET is conducting by detecting the power MOSFET drain-source voltage difference, thereby controlling the power MOSFET to be turned on and off When the body diode is turned on, the drive output is high, the power MOSFET is turned on, and the channel of the power MOSFET flows through a large current. When the body diode is reverse-biased, the drive output is low, and the power MOSFET withstands voltage. The control circuit provided by the present invention can The power consumption of the synchronous rectification system is greatly reduced, the temperature of the rectification bridge is reduced, and the reliability of the system is improved.

In the present invention, the rectified power MOSFET tube works in the reverse resistance area. During the rectification process, the channel resistance of the power MOSFET mainly flows through a large current, which realizes lower conduction loss, improves the overall efficiency of the generator, and saves energy. , Clean and environmentally friendly; at the same time, when the power MOSFET is turned on, an anti-current backflow circuit is added to make the rectifier circuit safer and more reliable.

It is to be understood that the invention is not limited to the precise configuration and components shown above. Various modifications, changes and optimizations may be made to the step sequence, details and operations of the above methods and structures without departing from the scope of protection of the claims.

Claims (6)

1. A synchronous rectification control circuit preventing current backflow, characterized in that, it is used to control the rectifier tube in the synchronous rectification system, including a voltage detection module, a logic control module and a drive module, The voltage detection module is used to detect the drain-source voltage of the rectifier and generate a first detection signal, a second detection signal, a third detection signal and a fourth detection signal; The voltage detection module includes a fourth NDMOS transistor (M4), a fourth comparator (Comp4) and a fourth voltage source, the non-inverting input terminal of the fourth comparator (Comp4) is connected to the source of the fourth NDMOS transistor (M4), Its inverting input terminal is connected to the positive terminal of the fourth voltage source, and its output terminal outputs the fourth detection signal; the gate of the fourth NDMOS transistor (M4) is connected to the power supply voltage, and its drain is connected to the drain of the rectifier tube pole; the negative end of the fourth voltage source is connected to the source of the rectifier tube; The logic control module includes a first D flip-flop (D1), a second D flip-flop (D2), a third D flip-flop (D3), a fourth D flip-flop (D4), and a fifth D flip-flop (D5) , the first counter (Counter1), the second counter (Counter2), the first inverter (G1), the second inverter (G2), the third inverter (G5), the fourth inverter (G7) , the fifth inverter (G9), the sixth inverter (G13), the seventh inverter (G14), the first NOR gate (G3), the second NOR gate (G4), the third NOR gate Gate (G6), the fourth NOR gate (G8), the fifth NOR gate (G11), the first NAND gate (G10), the second NAND gate (G12), the first NAND gate (G15), the a monoflop and a second monoflop, The input end of the second inverter (G2) is connected to the first detection signal, and its output end is connected to the first input end of the first NOR gate (G3); The input end of the first inverter (G1) is connected to the enable signal (ENA), and its output end is connected to the second input end of the first NOR gate (G3); The clock end of the first D flip-flop (D1) is connected to the clock end of the second D flip-flop (D2), the first input end of the second NOR gate (G4) and the output end of the first NOR gate (G3), Its reset terminal is connected to the output terminal of the seventh inverter (G14), its Q output terminal is connected to the second input terminal of the second NOR gate (G4), and its Q non-output terminal is connected to the third NOR gate (G6) first input terminal; The reset terminal of the second D flip-flop (D2) is connected to the enabling signal (ENA), and its Q non-output terminal is connected to the second input terminal of the third NOR gate (G6) and the second input terminal of the second NOR gate (G4). The third input terminal; the output terminal of the second NOR gate (G4) is connected to the input terminal of the third inverter (G5), the third D flip-flop (D3), the fourth D flip-flop (D4) and the fifth D The reset terminal of the flip-flop (D5); The enabling end of the first counter (Counter1) is connected to the output end of the third NOR gate (G6), its clock end is connected to the clock signal, and its maximum bit output is connected to the input end of the seventh inverter (G14); The enabling terminal of the second counter (Counter2) is connected to the output terminal of the fifth NOR gate (G11), its clock terminal is connected to the clock signal, and its maximum bit output is connected to the input terminal of the fifth inverter (G9); The input terminal of the fourth inverter (G7) is connected to the second detection signal, and the output terminal thereof is connected to the first input terminal of the fourth NOR gate (G8); The second input terminal of the fourth NOR gate (G8) is connected to the output terminal of the fifth inverter (G9), and its output terminal is connected to the clock terminal of the third D flip-flop (D3); The input end of the first monostable flip-flop is connected to the third detection signal, and its output end is connected to the clock end of the fourth D flip-flop (D4); The first input end of the first NAND gate (G10) is connected to the Q non-output end of the third D flip-flop (D3), and its second input end is connected to the Q output end of the fourth D flip-flop (D4); The first input end of the fifth NOR gate (G11) is connected to the output end of the third inverter (G5), its second input end is connected to the output end of the first NAND gate (G10), and its output end is connected to the second The first input end of the NAND gate (G12) and the first input end of the first AND gate (G15); The second input end of the second NAND gate (G12) is connected to the Q non-output end of the fifth D flip-flop (D5), and its output end is connected to the input end of the sixth inverter (G13); The second input terminal of the first AND gate (G15) is connected to the output terminal of the fifth inverter (G9), and its output terminal is connected to the reset terminal of the fourth comparator (Comp4) in the voltage detection module; The input end of the second monostable flip-flop is connected to the fourth detection signal, and its output end is connected to the clock end of the fifth D flip-flop (D5); The data input terminals of the first D flip-flop (D1), the second D flip-flop (D2), the third D flip-flop (D3), the fourth D flip-flop (D4) and the fifth D flip-flop (D5) are connected to the power supply Voltage; The input terminal of the driving module is connected to the output terminal of the sixth inverter (G13), and the output terminal thereof is connected to the gate of the rectifier tube. 2. The synchronous rectification control circuit preventing current backfeeding according to claim 1, wherein the voltage detection module further comprises a first comparator (Comp1), a second comparator (Comp2), a third comparator ( Comp3), a first voltage source, a second voltage source, a third voltage source, a first NDMOS transistor (M1), a second NDMOS transistor (M2) and a third NDMOS transistor (M3), The drains of the first NDMOS transistor (M1), the second NDMOS transistor (M2) and the third NDMOS transistor (M3) are all connected to the drains of the rectifier transistors, and the gates thereof are connected to the power supply voltage; The noninverting input terminal of the first comparator (Comp1) is connected to the source of the first NDMOS transistor (M1), its inverting input terminal is connected to the positive terminal of the first voltage source, and its output terminal outputs the first detection signal; The noninverting input terminal of the second comparator (Comp2) is connected to the source of the second NDMOS transistor (M2), its inverting input terminal is connected to the positive terminal of the second voltage source, and its output terminal outputs the second detection signal; The noninverting input terminal of the third comparator (Comp3) is connected to the source of the third NDMOS transistor (M3), its inverting input terminal is connected to the positive terminal of the third voltage source, and its output terminal outputs the third detection signal; The reset terminal of the first comparator (Comp1), the second comparator (Comp2) and the third comparator (Comp3) is connected to the output terminal of the second NOR gate (G4) in the voltage detection module; Negative terminals of the first voltage source, the second voltage source and the third voltage source are connected to the source of the rectifier tube. 3. The synchronous rectification control circuit for preventing current backfeeding according to claim 1, wherein the clock signal is generated by an oscillator (OSC), and the oscillator (OSC) generates a square wave signal with an oscillation frequency of 320Khz as the clock signal. 4. The synchronous rectification control circuit for preventing current backfeeding according to claim 1, wherein the first monostable flip-flop and the second monostable flip-flop have the same structure, The first monostable flip-flop includes an eighth inverter (G16), a ninth inverter (G17), a tenth inverter (G18) and a sixth NOR gate (G19), The input end of the eighth inverter (G16) is connected to the first input end of the sixth NOR gate (G19) and serves as the input end of the first monostable flip-flop; The input end of the ninth inverter (G17) is connected to the output end of the eighth inverter (G16), and the output end thereof is connected to the input end of the tenth inverter (G18); The second input terminal of the sixth NOR gate (G19) is connected to the output terminal of the tenth inverter (G18), and its output terminal is used as the output terminal of the first monostable flip-flop. 5. The synchronous rectification control circuit for preventing current backfeeding according to claim 1, characterized in that, the first counter (Comp1) and the second counter (Comp2) are composed of D flip-flops cascaded. 6 . The synchronous rectification control circuit for preventing current backfeeding according to claim 1 , wherein the drive module comprises an even number of cascaded inverters.