CN108511511B

CN108511511B - Semiconductor device and method of manufacturing the same

Info

Publication number: CN108511511B
Application number: CN201710684537.8A
Authority: CN
Inventors: 荒井伸也
Original assignee: Toshiba Memory Corp
Current assignee: Japanese Businessman Panjaya Co ltd; Kioxia Corp
Priority date: 2017-02-28
Filing date: 2017-08-11
Publication date: 2021-06-29
Anticipated expiration: 2037-08-11
Also published as: JP2018142654A; CN113380814B; TWI663714B; CN113380814A; CN113380815B; CN113394225A; TW201834218A; CN113380815A; CN113394225B; CN108511511A

Abstract

A semiconductor device and a method of manufacturing the same. Embodiments of the present invention provide a semiconductor device capable of shortening a distance from a sidewall portion of a semiconductor body in contact with a source layer to a gate layer over the source layer, and a method of manufacturing the same. The gate layer (80) of the semiconductor device of the embodiment is provided between the Source Layer (SL) and the stacked body (100) and is thicker than the electrode layer (70) 1. The semiconductor body (20) has a side wall portion (20a) that extends in the stacking direction of the stack (100) within the stack (100), within the gate layer (80), and within the semiconductor layer (13) and that is in contact with the semiconductor layer (13). The semiconductor body (20) is not in contact with the electrode layer (70) and the gate layer (80).

Description

Semiconductor device and method for manufacturing the same

The present application has priority to application based on japanese patent application No. 2017-36973 (application date: 2017, 2 and 28). The present application incorporates the entire contents of the base application by reference thereto.

Technical Field

Embodiments relate to a semiconductor device and a method of manufacturing the same.

Background

A three-dimensional memory having a structure in which a side wall of a channel body (channel body) penetrating a stacked body including a plurality of electrode layers is in contact with a source layer provided below the stacked body has been proposed.

Disclosure of Invention

Embodiments provide a semiconductor device capable of shortening a distance from a sidewall portion in contact with a source layer to a gate layer over the source layer in a semiconductor body and a method of manufacturing the same.

The semiconductor device of an embodiment includes an active layer, a stacked body, a gate layer, a semiconductor body, and a charge accumulation unit. The source layer has a semiconductor layer containing an impurity. The laminate is provided on the source layer, and has a plurality of electrode layers laminated with an insulator interposed therebetween. The gate layer is provided between the source layer and the stacked body, and is thicker than the thickness of the electrode layer 1 layer. The semiconductor body extends in the stacking direction of the stacked body in the stacked body, in the gate layer, and in the semiconductor layer, and has a side wall portion in contact with the semiconductor layer. The semiconductor body is not in contact with the electrode layer and the gate layer. The charge accumulation portion is provided between the semiconductor body and the electrode layer.

Drawings

Fig. 1 is a schematic perspective view of a semiconductor device according to an embodiment.

Fig. 2 is a schematic cross-sectional view of a semiconductor device of an embodiment.

Fig. 3 is an enlarged sectional view of a portion a in fig. 2.

Fig. 4 to 17 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment.

Fig. 18 is a schematic cross-sectional view of a semiconductor device of an embodiment.

Description of reference numerals

1 … memory cell array; 10 … a substrate; 11 … a layer comprising a metal; 12-14 … silicon layer; 20 … a semiconductor body; 20a … side wall portion; 30 … memory film; 70 … an electrode layer; 72 … an insulating layer; 80 … a gate layer; 100 … a laminate; SL … source layer

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals.

In the embodiment, a semiconductor memory device having a three-dimensional memory cell array, for example, will be described as a semiconductor device.

Fig. 1 is a schematic perspective view of a memory cell array 1 of the embodiment.

Fig. 2 is a schematic cross-sectional view of the memory cell array 1.

In fig. 1, two directions parallel to and orthogonal to the main surface of the substrate 10 are referred to as an X direction and a Y direction, and a direction orthogonal to both the X direction and the Y direction is referred to as a Z direction (stacking direction). The Y direction and the Z direction in fig. 2 correspond to the Y direction and the Z direction in fig. 1, respectively.

The memory cell array 1 has: the liquid crystal display device includes a source layer SL, a stacked body 100 disposed on the source layer SL, a gate layer 80 disposed between the source layer SL and the stacked body 100, a plurality of column portions CL, a plurality of separation portions 160, and a plurality of bit lines BL disposed above the stacked body 100. The source layer SL is provided on the substrate 10 with the insulating layer 41 therebetween. The substrate 10 is, for example, a silicon substrate.

The columnar portion CL is formed in a substantially columnar shape extending in the lamination direction (Z direction) of the laminate 100. The columnar portion CL further penetrates the gate layer 80 below the stacked body 100 and reaches the source layer SL. The plurality of columnar portions CL are arranged, for example, in a staggered manner. Alternatively, the plurality of columnar portions CL may be arranged in a square grid along the X direction and the Y direction.

The separating section 160 separates the stacked body 100 and the gate layer 80 into a plurality of blocks (or finger portions) in the Y direction. The isolation portion 160 has a structure in which an insulating film 163 is embedded in a slit ST shown in fig. 17 described later.

The plurality of bit lines BL are, for example, metal films extending in the Y direction. The plurality of bit lines BL are separated from each other in the X direction.

An upper end portion of the semiconductor body 20 described later of the columnar portion CL is connected to the bit line BL via a contact portion Cb and a contact portion V1 shown in fig. 1.

As shown in fig. 2, the source layer SL has: a layer 11 containing a metal and semiconductor layers 12 to 14.

The metal-containing layer 11 is provided on the insulating layer 41. The metal-containing layer 11 is, for example, a tungsten layer or a tungsten silicide (tungsten silicide) layer.

A semiconductor layer 12 is provided on the metal-containing layer 11, a semiconductor layer 13 is provided on the semiconductor layer 12, and a semiconductor layer 14 is provided on the semiconductor layer 13.

The semiconductor layers 12 to 14 are conductive polysilicon layers containing impurities. The semiconductor layers 12 to 14 are, for example, n-type polysilicon layers doped with phosphorus. Semiconductor layer 14 may also be an undoped polysilicon layer that is not intentionally doped with impurities.

The thickness of the semiconductor layer 14 is thinner than the thickness of the semiconductor layer 12 and the thickness of the semiconductor layer 13.

An insulating layer 44 is provided on the semiconductor layer 14, and a gate layer 80 is provided on the insulating layer 44. The gate layer 80 is a polycrystalline silicon layer containing impurities and having conductivity. The gate layer 80 is, for example, an n-type polysilicon layer doped with phosphorus. The thickness of the gate layer 80 is thicker than the thickness of the semiconductor layer 14.

The stacked body 100 is provided on the gate layer 80. The laminate 100 includes a plurality of electrode layers 70 stacked in a direction (Z direction) perpendicular to the main surface of the substrate 10. An insulating layer (insulator) 72 is provided between the upper and lower adjacent electrode layers 70. An insulating layer 72 is provided between the lowermost electrode layer 70 and the gate layer 80. An insulating layer 45 is provided on the uppermost electrode layer 70.

The electrode layer 70 is a metal layer. The electrode layer 70 is, for example, a tungsten layer containing tungsten as a main component or a molybdenum layer containing molybdenum as a main component. The insulating layer 72 is a silicon oxide layer containing silicon oxide as a main component.

At least the uppermost electrode layer 70 among the plurality of electrode layers 70 is a drain side select gate SGD of a drain side select transistor STD (fig. 1), and at least the lowermost electrode layer 70 is a source side select gate SGS of a source side select transistor STS (fig. 1). For example, a lower-layer-side multilayer (e.g., 3-layer) electrode layer 70 including the lowermost electrode layer 70 serves as the source-side select gate SGS. A plurality of layers of drain side select gates SGD may also be provided.

Between the drain-side select gate SGD and the source-side select gate SGS, a multilayer electrode layer 70 is provided as a cell gate CG.

The gate layer 80 is thicker than both the thickness of 1 layer of the electrode layer 70 and the thickness of 1 layer of the insulating layer 72. Therefore, the gate layer 80 is thicker than the thickness of the 1 layer of the drain side select gate SGD, the thickness of the 1 layer of the source side select gate SGS, and the thickness of the 1 layer of the cell gate CG.

The plurality of columnar portions CL extend in the stacked direction in the stacked body 100, further penetrate the gate layer 80, the insulating layer 44, the semiconductor layer 14, and the semiconductor layer 13, and reach the semiconductor layer 12.

Fig. 3 is an enlarged sectional view of a portion a in fig. 2.

The columnar section CL includes: a memory film 30, a semiconductor body 20, and an insulating core film (core film) 50. The memory film 30 is a laminated film of insulating films including a tunnel insulating film 31, a charge accumulating film (charge accumulating part) 32, and a block insulating film 33.

As shown in fig. 2, the semiconductor body 20 is formed in a tubular shape continuously extending in the Z direction in the stacked body 100 and in the gate layer 80 to reach the source layer SL. The core film 50 is provided inside the tubular semiconductor body 20.

The upper end of the semiconductor body 20 is connected to the bit line BL via a contact Cb and a contact V1 shown in fig. 1. The sidewall portion 20a on the lower end side of the semiconductor body 20 is in contact with the semiconductor layer 13 of the source layer SL.

The memory film 30 is provided between the stacked body 100 and the semiconductor body 20 and between the gate layer 80 and the semiconductor body 20, and surrounds the semiconductor body 20 from the outer peripheral side.

The memory film 30 extends continuously in the Z direction in the stacked body 100 and in the gate layer 80. The memory film 30 is not provided on the side wall portion (source contact portion) 20a of the semiconductor body 20 which is in contact with the semiconductor layer 13. The sidewall portion 20a is not covered with the memory film 30. Further, the memory film 30 may be disposed between the semiconductor body 20 and the semiconductor layer 13, on a part of the outer periphery of the semiconductor body 20.

The lower end of the semiconductor body 20 is continuous with the side wall portion 20a, is located below the side wall portion 20a, and is located in the semiconductor layer 12. A memory film 30 is provided between the lower end of the semiconductor body 20 and the semiconductor layer 12. Therefore, the memory film 30 is cut in the Z direction at the position of the side wall portion 20a of the semiconductor body 20, and is disposed below the position surrounding the outer periphery of the lower end portion of the semiconductor body 20 and below the bottom surface of the semiconductor body 20.

As shown in fig. 3, the tunnel insulating film 31 is provided between the semiconductor body 20 and the charge trapping film 32, and is in contact with the semiconductor body 20. The charge trapping film 32 is provided between the tunnel insulating film 31 and the block insulating film 33. The block insulating film 33 is provided between the charge trapping film 32 and the electrode layer 70.

Semiconductor body 20, memory film 30, and electrode layer 70 (cell gate CG) constitute a memory cell MC. The memory cell MC has a vertical transistor structure in which the electrode layer 70 (cell gate CG) surrounds the periphery of the semiconductor body 20 via the memory film 30.

In the memory cell MC having the vertical transistor structure, the semiconductor body 20 is, for example, a channel body of silicon, and the electrode layer 70 (cell gate CG) functions as a control gate. The charge trapping film 32 functions as a data storage layer for trapping charges injected from the semiconductor body 20.

The semiconductor memory device according to the embodiment is a nonvolatile semiconductor memory device capable of electrically erasing and writing data and holding memory contents even when power is turned off.

The memory cell MC is, for example, a Charge Trap (Charge Trap) type memory cell. The charge trapping film 32 has a plurality of charge trapping sites in an insulating film, and includes, for example, a silicon nitride film. Alternatively, the charge trapping film 32 may be a conductive Floating Gate (Floating Gate) whose periphery is surrounded by an insulator.

The tunnel insulating film 31 serves as a potential barrier when injecting charges from the semiconductor body 20 into the charge trapping film 32 or when discharging charges trapped in the charge trapping film 32 to the semiconductor body 20. The tunnel insulating film 31 includes, for example, a silicon oxide film.

The block insulating film 33 prevents the electric charges accumulated in the electric charge accumulating film 32 from being discharged to the electrode layer 70. In addition, the block insulating film 33 prevents backward tunneling (back tunneling) of charges from the electrode layer 70 to the column portion CL.

The block insulating film 33 includes, for example, a silicon oxide film. Alternatively, the block insulating film 33 may have a stacked structure of a silicon oxide film and a metal oxide film. In this case, a silicon oxide film can be provided between the charge trapping film 32 and the metal oxide film, and a metal oxide film can be provided between the silicon oxide film and the electrode layer 70. The metal oxide film is, for example, an aluminum oxide film.

As shown in fig. 1, a drain side selection transistor STD is provided in an upper layer portion of the stacked body 100. A source side selection transistor STS is provided in a lower layer portion of the stack 100.

The drain side select transistor STD is a vertical transistor having the drain side select gate SGD (fig. 2) as a control gate, and the source side select transistor STS is a vertical transistor having the source side select gate SGS (fig. 2) as a control gate.

A portion of the semiconductor body 20 facing the drain-side select gate SGD functions as a channel, and the memory film 30 between the channel and the drain-side select gate SGD functions as a gate insulating film of the drain-side select transistor STD.

A portion of the semiconductor body 20 facing the source side select gate SGS functions as a channel, and the memory film 30 between the channel and the source side select gate SGS functions as a gate insulating film of the source side select transistor STS.

A plurality of drain side selection transistors STD connected in series through the semiconductor body 20 may be provided, or a plurality of source side selection transistors STS connected in series through the semiconductor body 20 may be provided. The same gate potential is applied to the plurality of drain side select gates SGD of the plurality of drain side select transistors STD, and the same gate potential is applied to the plurality of source side select gates SGS of the plurality of source side select transistors STS.

Between the drain side selection transistor STD and the source side selection transistor STS, a plurality of memory cells MC are provided. The plurality of memory cells MC, the drain side selection transistor STD, and the source side selection transistor STS are connected in series by the semiconductor bodies 20 of the pillar portions CL to constitute 1 memory string (memory string). The memory strings are arranged, for example, in a staggered manner in a plane direction parallel to the XY plane, and the plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

The sidewall 20a of the semiconductor body 20 is in contact with the semiconductor layer 13 doped with an impurity (e.g., phosphorus), and the sidewall 20a also contains the impurity (e.g., phosphorus). The side wall portion 20a has an impurity concentration higher than that of a portion of the semiconductor body 20 facing the stacked body 100. The impurity concentration of the sidewall portion 20a is higher than the impurity concentration of the channel of the memory cell MC, the impurity concentration of the channel of the source side selection transistor STS, and the impurity concentration of the drain side selection gate STD.

Further, by a heat treatment described later, an impurity (e.g., phosphorus) diffuses from the side wall portion 20a to a portion 20b of the semiconductor body 20 opposed to the gate layer 80. The portion between the sidewall portion 20a and the portion 20b (the portion corresponding to the insulating layer 44) in the semiconductor body 20 also contains an impurity (e.g., phosphorus).

The impurity does not diffuse to the entire region of the portion 20b of the semiconductor body 20, and the region on the stacked body 100 side in the portion 20b has an impurity concentration lower than that of the region on the side wall portion 20a side in the portion 20 b. The portion 20b has a gradient in which the impurity concentration decreases from the side wall portion 20a side to the stacked body 100 side. The region of the portion 20b on the side of the sidewall portion 20a has a higher impurity concentration than the portion of the semiconductor body 20 facing the stacked body 100.

In the read operation, electrons are supplied from the source layer SL to the channel of the memory cell MC through the sidewall portion 20a of the semiconductor body 20. At this time, by applying an appropriate potential to the gate layer 80, a channel (n-type channel) can be induced in the entire region of the portion 20b of the semiconductor body 20. The memory film 30 between the portion 20b of the semiconductor body 20 and the gate layer 80 functions as a gate insulating film.

Since the portion 20b of the semiconductor body 20 contains impurities as described above, it may be difficult to turn on the portion 20b by potential control of the gate layer 80, and the function of turning off the portion may be assumed by the source side selection transistor STS. The impurities do not diffuse into the channel of the source side select transistor STS.

The distance between the sidewall portion 20a and the portion 20b of the semiconductor body 20 is smaller than the thickness of the gate layer 80. The distance between the sidewall 20a and the portion 20b of the semiconductor body 20 substantially corresponds to the total thickness of the semiconductor layer 14 and the thickness of the insulating layer 44.

As described below, the thick gate layer 80 is used as an etching stopper layer when the slit ST is formed. Therefore, the semiconductor layer 14 can be thinned. The thickness of the gate layer 80 is, for example, about 200nm, and the thickness of the semiconductor layer 14 is, for example, about 30 nm. Therefore, the distance for diffusing the impurity from the sidewall 20a to the portion of the semiconductor body 20 facing the insulating layer 44 can be shortened, and the diffusion of the impurity to the region of the gate layer 80 where channel induction is difficult can be easily controlled.

In addition, since the portion 20b of the semiconductor body 20 facing the gate layer 80 contains impurities, the gate layer 80 can be made to function as a GIDL (gate induced drain leakage) generator (generator) during an erase operation.

An erase potential (e.g., several volts) is applied to the gate layer 80, and holes generated by applying a high electric field to the portion 20b of the semiconductor body 20 are supplied to the channel of the memory cell MC, thereby raising the channel potential. Then, by setting the potential of the cell gate CG to, for example, the ground potential (0V), holes are injected into the charge accumulation film 32 by the potential difference between the semiconductor body 20 and the cell gate CG, thereby performing the data erasing operation.

Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to fig. 4 to 17. The cross sections of fig. 4 to 17 correspond to the cross section of fig. 2.

As shown in fig. 4, an insulating layer 41 is formed on the substrate 10. A layer 11 containing a metal is formed on the insulating layer 41. The metal-containing layer 11 is, for example, a tungsten layer or a tungsten silicide layer.

A semiconductor layer (1 st semiconductor layer) 12 is formed on the metal-containing layer 11. The semiconductor layer 12 is, for example, a polysilicon layer doped with phosphorus. The thickness of the semiconductor layer 12 is, for example, about 200 nm.

A protective film 42 is formed on the semiconductor layer 12. The protective film 42 is, for example, a silicon oxide film.

A sacrificial layer 91 is formed on the protective film 42. The sacrificial layer 91 is, for example, an undoped polysilicon layer. The thickness of the sacrificial layer 91 is, for example, about 30 nm.

The protective film 43 is formed on the sacrificial layer 91. The protective film 43 is, for example, a silicon oxide film.

A semiconductor layer (2 nd semiconductor layer) 14 is formed on the protective film 43. Semiconductor layer 14 is, for example, a polysilicon layer that is undoped or doped with phosphorus. The thickness of the semiconductor layer 14 is, for example, about 30 nm.

An insulating layer 44 is formed on the semiconductor layer 14. The insulating layer 44 is, for example, a silicon oxide layer.

A gate layer 80 is formed on the insulating layer 44. The gate layer 80 is, for example, a polysilicon layer doped with phosphorus. The thickness of the gate layer 80 is larger than both the thickness of the semiconductor layer 14 and the thickness of the insulating layer 44, and is, for example, about 200 nm.

As shown in fig. 5, a stacked body 100 is formed on the gate layer 80. On the gate layer 80, an insulating layer (2 nd layer) 72 and a sacrificial layer (1 st layer) 71 are alternately stacked. The step of alternately stacking the insulating layers 72 and the sacrificial layers 71 is repeated, and a plurality of sacrificial layers 71 and a plurality of insulating layers 72 are formed on the gate layer 80. An insulating layer 45 is formed on the uppermost sacrificial layer 71. For example, the sacrificial layer 71 is a silicon nitride layer, and the insulating layer 72 is a silicon oxide layer.

The thickness of the gate layer 80 is thicker than both the thickness of 1 layer of the sacrificial layer 71 and the thickness of 1 layer of the insulating layer 72.

As shown in fig. 6, a plurality of Memory cavities (MH) are formed in a layer above the semiconductor layer 12. The memory cavity MH is formed by Reactive Ion Etching (RIE) using a mask layer not shown. The memory cavity MH penetrates the stacked body 100, the gate layer 80, the insulating layer 44, the semiconductor layer 14, the protective film 43, the sacrificial layer 91, and the protective film 42, and reaches the semiconductor layer 12. The bottom of the memory cavity MH is located in the semiconductor layer 12.

The sacrificial layers (silicon nitride layers) 71 and the insulating layers (silicon oxide layers) 72 are continuously etched using the same gas (for example, a CF-based gas) without switching the gas type. At this time, the gate layer (polysilicon layer) 80 functions as an etching stopper layer, and temporarily stops etching at the position of the gate layer 80. The variation of the etching rate among the plurality of memory cavities MH is absorbed by the thicker gate layer 80, and the variation of the bottom positions among the plurality of memory cavities MH is reduced.

Then, the gas species are switched to perform stepwise etching of each layer. That is, the insulating layer 44 is used as a barrier layer, the remaining portion of the gate layer 80 is etched, the semiconductor layer 14 is used as a barrier layer, the insulating layer 44 is etched, the protective film 43 is used as a barrier layer, the semiconductor layer 14 is etched, the sacrificial layer 91 is used as a barrier layer, the protective film 43 is etched, the protective film 42 is used as a barrier layer, the sacrificial layer 91 is etched, the semiconductor layer 12 is used as a barrier layer, and the protective film 42 is etched. Further, etching is blocked in the middle of the thick semiconductor layer 12.

The thick gate layer 80 can easily control the etching stop position for the hole processing of the stacked body 100 having a high aspect ratio.

In the memory cavity MH, a columnar portion CL is formed as shown in fig. 7. The memory film 30 is formed to be conformal (conformal) along the sides and the bottom of the memory cavity MH, the semiconductor body 20 is formed to be conformal along the memory film 30 at the inner side of the memory film 30, and the core film 50 is formed at the inner side of the semiconductor body 20.

Then, as shown in fig. 8, a plurality of slits ST are formed in the laminate 100. The slit ST is formed by RIE using a mask layer not shown. The slit ST penetrates the stacked body 100 and reaches the gate layer 80.

As in the formation of the memory cavity MH, the plurality of sacrificial layers 71 and the plurality of insulating layers 72 are continuously etched using the same gas (for example, CF-based gas) without switching the gas type. At this time, the gate layer 80 functions as an etching stopper, and temporarily stops etching by the slit processing at the position of the gate layer 80. The thick gate layer 80 absorbs the variation in etching rate among the plurality of slits ST, thereby reducing the variation in bottom position among the plurality of slits ST.

Then, the gas species are switched to perform stepwise etching of each layer. That is, the remaining portion of the gate layer 80 is etched using the insulating layer 44 as a barrier layer. As shown in fig. 9, the insulating layer 44 is exposed at the bottom of the slit ST.

Thereafter, the semiconductor layer 14 is used as a barrier layer, the insulating layer 44 is etched, and the protective film 43 is used as a barrier layer, and the semiconductor layer 14 is etched. As shown in fig. 10, the sacrifice layer 91 is exposed at the bottom of the slit ST.

The thick gate layer 80 can easily control the etching stop position of the slit processing with respect to the stacked body 100 having a high aspect ratio. Further, in the subsequent stepwise etching, the bottom position of the slit ST can be controlled with high accuracy and ease. The slit ST does not penetrate the sacrificial layer 91, and the bottom of the slit ST ends within the sacrificial layer 91.

On the side and bottom of the slit ST, as shown in fig. 11, the liner film 161 is formed to be conformal along the side and bottom of the slit ST. The liner film 161 is, for example, a silicon nitride film.

The liner film 161 formed at the bottom of the slit ST is removed by, for example, RIE. As shown in fig. 12, the sacrifice layer 91 is exposed at the bottom of the slit ST.

Then, the sacrificial layer 91 is removed by etching through the slit ST. For example, the sacrificial layer 91 as a polysilicon layer is removed by supplying heat TMY (trimethylhydroxyethylammonium hydroxide) through the slit ST.

The sacrifice layer 91 is removed, and as shown in fig. 13, a cavity 90 is formed between the semiconductor layer 12 and the semiconductor layer 14. The

protective films

42 and 43, which are, for example, silicon oxide films, protect the

semiconductors

12 and 14 from etching by the hot TMY. The liner film (e.g., silicon nitride film) 161 formed on the side surface of the slit ST prevents side etching of the gate layer 80 and the semiconductor layer 14 from the slit ST side.

A part of the side wall of the columnar portion CL is exposed in the cavity 90. That is, a part of the memory film 30 is exposed.

A part of the memory film 30 exposed in the cavity 90 is removed by etching through the slit ST. The memory film 30 is etched by, for example, a CDE (chemical dry etching) method.

At this time, the

protective films

42 and 43 of the same type as those included in the memory film 30 are also removed. The liner film 161 formed on the side surface of the slit ST is a silicon nitride film of the same kind as the charge trapping film 32 included in the memory film 30, but the thickness of the liner film 161 is thicker than the thickness of the charge trapping film 32, and the liner film 161 remains on the side surface of the slit ST.

The liner film 161 prevents side etching from the slit ST side of the sacrificial layer 71, the insulating layer 72, and the insulating layer 44 when a part of the memory film 30 exposed in the cavity 90 is removed. Since the lower surface of the insulating layer 44 is covered with the semiconductor layer 14, etching from the lower surface side of the insulating layer 44 is also prevented.

By removing a part of the memory film 30, the memory film 30 is cut vertically at the sidewall 20a as shown in fig. 14. By the control of the etching time, the memory film (gate insulating film) 30 between the gate layer 80 and the semiconductor body 20 is not etched.

In addition, by the control of the etching time, the memory film 30 is also left between the semiconductor layer 12 and the semiconductor body 20 below the sidewall portion 20 a. The lower end portion of the semiconductor body 20 below the sidewall portion 20a is held in a state of being supported by the semiconductor layer 12 via the memory film 30.

A part of the memory film 30 is removed, and as shown in fig. 14, a part of the semiconductor body 20 (sidewall 20a) is exposed in the cavity 90.

In the cavity 90, as shown in fig. 15, a semiconductor layer (3 rd semiconductor layer) 13 is formed. The semiconductor layer 13 is, for example, a polysilicon layer doped with phosphorus.

A gas containing silicon is supplied to the cavity 90 through the gap ST, and the semiconductor layer 13 starts epitaxial growth from the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the sidewall portion 20a of the semiconductor body 20 exposed to the cavity 90, and the cavity 90 is buried by the semiconductor layer 13.

Since the semiconductor layer 14 is also formed as a polycrystalline silicon layer on the upper surface of the cavity 90, the semiconductor layer 13 can be epitaxially grown from the upper surface side of the cavity 90, and the time required for forming the semiconductor layer 13 can be shortened.

The sidewall portion 20a of the semiconductor body 20 is in contact with the semiconductor layer 13. At the stage where the columnar portion CL is formed, the semiconductor body 20 contains substantially no impurities from the upper end to the lower end. The semiconductor layer 13 is epitaxially grown under high temperature heat treatment, at which time impurities (e.g., phosphorus) are also doped in the sidewall portions 20a of the semiconductor body 20.

Further, impurities (phosphorus) are thermally diffused from the side wall portion 20a in the extending direction of the semiconductor body 20 by heat treatment at the time of epitaxial growth of the semiconductor layer 13 or heat treatment in a later step. The impurities are diffused into at least the portion of the semiconductor body 20 that is opposite the insulating layer 44. That is, the impurity is diffused into a region where channel induction of the gate layer 80 is difficult to occur.

The gate layer 80 plays a role as an absorption layer of poor etching rate when forming the memory cavity MH and/or the slit ST, as described above. Therefore, the semiconductor layer 14 does not need to be provided thick. Therefore, the distance over which the impurity is diffused from the side wall portion 20a of the semiconductor body 20 to the portion facing the insulating layer 44 can be shortened. For example, the diffusion distance is about 50nm, and the impurity can be easily and reliably diffused into the portion of the semiconductor body 20 facing the insulating layer 44.

Further, if the impurity is diffused into the portion 20b of the semiconductor body 20 facing the gate layer 80, holes formed by GIDL can be generated in the portion 20b as described above, and an erasing operation using the holes can be performed.

Next, after the liner film 161 is removed or in the same step as the removal of the liner film 161, the sacrificial layer 71 is removed by an etching solution or an etching gas supplied through the slit ST. For example, the sacrificial layer 71, which is a silicon nitride layer, is removed using an etching solution containing phosphoric acid.

The sacrifice layer 71 is removed, and as shown in fig. 16, a gap 75 is formed between the insulating layers 72 adjacent to each other in the upper and lower stages. A gap 75 is also formed between the uppermost insulating layer 72 and the insulating layer 45.

The insulating layers 72 are in contact with the side surfaces of the columnar portions CL so as to surround the side surfaces of the columnar portions CL. The plurality of insulating layers 72 are supported by physical coupling with the plurality of columnar portions CL, and a gap 75 between the insulating layers 72 is ensured.

As shown in fig. 17, an electrode layer 70 is formed in the gap 75. The electrode layer 70 is formed by, for example, a CVD (chemical vapor deposition) method. The source gas is supplied to the gap 75 through the slit ST. The electrode layer 70 formed on the side surface of the slit ST is removed.

Then, as shown in fig. 2, the insulating film 163 is embedded in the slit ST.

The sacrificial layer 91 is not limited to a polysilicon layer, and may be, for example, a silicon nitride layer. In the case of a combination of the semiconductor layers 12 and 14 as the polysilicon layers and the sacrificial layer 91 as the silicon nitride layer, the

protective films

42 and 43 may not be provided.

Fig. 18 is a schematic cross-sectional view showing another example of the memory cell array of the embodiment.

The semiconductor layer 13 is provided along the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the sidewall portion 20a of the semiconductor body 20, and the cavity 90 remains between the semiconductor layer 13 provided on the upper surface of the semiconductor layer 12 and the semiconductor layer 13 provided on the lower surface of the semiconductor layer 14.

If the semiconductor layer 13 is insufficiently buried in the cavity 90 and a void is generated in the semiconductor layer 13, the void may move in the subsequent high-temperature heat treatment step and break the sidewall 20a of the semiconductor body 20.

As shown in fig. 18, if the semiconductor layer 13 is formed as a thin film along the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the side wall portion 20a of the semiconductor body 20, and the cavity 90 remains inside the semiconductor layer 13, there is no gap that moves.

In the above embodiment, the silicon nitride layer is exemplified as the 1 st layer 71, but a metal layer or a silicon layer doped with an impurity may be used as the 1 st layer 71. In this case, since the 1 st layer 71 is the electrode layer 70 as it is, a process of replacing the 1 st layer 71 with an electrode layer is not necessary.

The 2 nd layer 72 may be removed by etching through the slit ST to form a gap between the upper and lower adjacent electrode layers 70.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and/or modifications thereof are included in the scope and/or gist of the invention, and are included in the scope equivalent to the invention described in the claims.

Claims

1. A semiconductor device comprising:

a source layer having a semiconductor layer containing impurities;

a laminated body provided on the source layer and having a plurality of electrode layers laminated with an insulator interposed therebetween;

a gate layer, which is arranged between the source layer and the stacked body, and is thicker than the thickness of the electrode layer 1;

A semiconductor body extending in the stacking direction of the stack, within the gate layer, and within the semiconductor layer, having sidewall portions in contact with the semiconductor layer, and not being connected to the electrode layer is in contact with the gate layer; and

a charge accumulation portion provided between the semiconductor body and the electrode layer,

A distance between a portion of the semiconductor body facing the gate layer and the sidewall portion is smaller than a thickness of the gate layer.

2. The semiconductor device according to claim 1,

The impurity concentration of the side wall portion of the semiconductor body is higher than the impurity concentration of the portion of the semiconductor body facing the stacked body.

3. The semiconductor device according to claim 1,

The impurity concentration of the portion of the semiconductor body facing the gate layer is higher than the impurity concentration of the portion of the semiconductor body facing the stacked body.

4. The semiconductor device according to claim 1,

The electrode layer has:

at least one layer of drain side select gate thinner than the gate layer;

at least one layer of source side select gate disposed between the drain side select gate and the gate layer and thinner than the gate layer; and

A plurality of cell gates are provided between the drain-side selection gate and the source-side selection gate so as to face the charge accumulating portion, and each cell gate of the plurality of cell gates is thinner than the gate layer.

5. A semiconductor device comprising:

a source layer having a semiconductor layer containing impurities;

6. The semiconductor device according to claim 5,

7. The semiconductor device according to claim 5,

The electrode layer has:

at least one layer of drain side select gate thinner than the gate layer;

8. A semiconductor device comprising:

a source layer having a semiconductor layer containing impurities;

9. The semiconductor device according to claim 8,

The electrode layer has:

at least one layer of drain side select gate thinner than the gate layer;

10. A semiconductor device comprising:

a source layer having a semiconductor layer containing impurities;

The electrode layer has:

at least one layer of drain side select gate thinner than the gate layer;

11. The semiconductor device of claim 1, 5, 8 or 10,

The gate layer is a silicon layer containing phosphorus.

12. The semiconductor device of claim 1, 5, 8 or 10,

The semiconductor layer is a silicon layer containing phosphorus.

13. The semiconductor device of claim 1, 5, 8 or 10,

The source layer also has a metal-containing layer,

The semiconductor layer is disposed between the metal-containing layer and the gate layer.

14. The semiconductor device of claim 1, 5, 8 or 10,

The charge accumulating portion is continuous in the stacking direction between the stack and the semiconductor body.

15. The semiconductor device of claim 14,

A film constituting the charge storage portion is provided between the gate layer and the semiconductor body.

16. The semiconductor device of claim 14,

Under the bottom surface of the semiconductor body, a film constituting the charge accumulating portion is provided.

17. The semiconductor device of claim 1, 5, 8 or 10,

At the time of the erasing operation, a potential for causing gate induced leakage, ie, GIDL, to occur in a portion of the semiconductor body opposed to the gate layer is applied to the gate layer.

18. The semiconductor device of claim 1, 5, 8 or 10,

The semiconductor layer has:

the first semiconductor layer;

a second semiconductor layer disposed between the first semiconductor layer and the gate layer; and

a third semiconductor layer provided along the upper surface of the first semiconductor layer, the lower surface of the second semiconductor layer, and the sidewall portion of the semiconductor body,

A cavity is formed between the third semiconductor layer provided on the upper surface of the first semiconductor layer and the third semiconductor layer provided on the lower surface of the second semiconductor layer.

19. A method of manufacturing a semiconductor device, comprising:

the process of forming a sacrificial layer on the first semiconductor layer;

a process of forming a second semiconductor layer on the sacrificial layer;

a step of forming an insulating layer on the second semiconductor layer;

a step of forming a gate layer thicker than the second semiconductor layer on the insulating layer;

a step of forming a laminate having a plurality of first layers and a plurality of second layers including alternately stacked first layers and second layers on the gate layer;

a step of forming a semiconductor body in a hole penetrating the stacked body, the gate layer, the insulating layer, the second semiconductor layer and the sacrificial layer;

after forming the semiconductor body, forming a gap penetrating the stacked body, the gate layer, the insulating layer, and the second semiconductor layer to reach the sacrificial layer;

The process of removing the sacrificial layer through the gap to form a cavity between the first semiconductor layer and the second semiconductor layer;

exposing a portion of the semiconductor body in the cavity; and

A step of forming a third semiconductor layer containing impurities and in contact with the part of the semiconductor body in the cavity.

20. The method of manufacturing a semiconductor device according to claim 19,

The first semiconductor layer, the second semiconductor layer, the sacrificial layer and the gate layer are silicon layers,

Between the first semiconductor layer and the sacrificial layer and between the sacrificial layer and the second semiconductor layer, a protective film of a material different from that of the silicon layer is formed,

The sacrificial layer is removed in a state where the side surfaces of the slits are covered with a liner film having a material different from that of the silicon layer.

21. The method of manufacturing a semiconductor device according to claim 19,

The first semiconductor layer, the second semiconductor layer and the gate layer are silicon layers,

The sacrificial layer is a silicon nitride layer.

22. The method of manufacturing a semiconductor device according to claim 19,

Before forming the semiconductor body, an insulating film is formed on the sides of the hole,

After removing the sacrificial layer, a part of the insulating film exposed in the cavity is removed to expose the part of the semiconductor body in the cavity.

23. The method of manufacturing a semiconductor device according to claim 19,

The impurity is thermally diffused to the part of the semiconductor body and the part of the semiconductor body facing the insulating layer during or after the formation of the third semiconductor layer .

24. The method of manufacturing a semiconductor device according to claim 23,

The impurity also diffuses to a portion of the semiconductor body opposite the gate layer.

25. The method of manufacturing a semiconductor device according to claim 19,

The step of replacing the first layer with an electrode layer through the gap is also included.