CN108551622B - A kind of buffer circuits of low noise MEMS microphone - Google Patents

Abstract

The invention discloses a buffer circuit of a low-noise MEMS microphone, which comprises three parts: a bias module, a negative feedback module and a signal reading module. The output end of the bias module is connected with the input end of the negative feedback module, the output end of the negative feedback module is connected with the input end of the bias module, the output end of the negative feedback module is connected with the input end of the signal reading module, and the signal reading module The output is connected to the input of the negative feedback module. The invention can simplify the circuit structure, stably read the static current of the signal module, and reduce circuit noise, so that the buffer circuit of the MEMS microphone can accurately read the voltage signal under the action of sound pressure within the sound bandwidth frequency, and is suitable for the MEMS microphone. The input stage of the sensor readout interface circuit.

Description

A buffer circuit of a low noise MEMS microphone

technical field

The invention belongs to the technical field of electronics, and further relates to a buffer circuit of a low-noise MEMS (Micro-Electro-Mechanical System) microphone in the technical field of analog integrated circuits. The invention can be used as the input stage of the readout interface circuit of the MEMS microphone sensor, and can accurately read the voltage signal under the action of sound pressure.

Background technique

MEMS microphones are widely used. In the design of the MEMS microphone readout interface circuit, the buffer circuit is a key module. This module needs to accurately read the voltage signal under the action of sound pressure. The traditional buffer circuit is usually implemented with an operational amplifier, but the operational amplifier has a complex structure, high power consumption and noise, high cost to deal with the noise, and a large chip area. In order to meet the requirement that the buffer circuit can accurately read the signal, the buffer circuit must have low noise performance.

Zhou Feng disclosed a unit of MEMS microphone in his paper "Research and Design of Conditioning Circuit of Condenser MEMS Microphone" (Master's thesis of Microelectronics and Solid State Electronics, Yizhou University, May 2012) gain buffer circuit. The circuit structure of the unity gain buffer is that the output of the op amp is connected to the input of one end, and its gain is unity. structure. Although the circuit is easy to implement, the disadvantages of the circuit are that the power consumption is large, the noise is high, the noise processing cost is high, and the chip area is large.

Electronics and Telecommunications Research Institute, Daejeon (KR), in its patent document "READ-OUT CIRCUIT WITH HIGH INPUT IMPEDANCE" (Application No. 15/511, 361 Publication No. US8,300,850B2), discloses an application to a microphone the high input impedance of the readout circuit. The circuit mainly includes: a feedback resistor and an operational amplifier connected into a buffer structure, one end of the feedback resistor is connected to the input of the operational amplifier, and the other end is connected to the output of the operational amplifier. The circuit structure has the advantages of high input impedance and can read signals well. However, the readout circuit still has the disadvantage that since the circuit uses resistors and op amps to achieve high input impedance, this method is more It is complex, and the resistance occupies a large area of the chip.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a buffer circuit for a low-noise MEMS microphone in view of the above-mentioned deficiencies in the prior art.

In order to achieve the above purpose, the buffer circuit of the present invention includes a bias module, a negative feedback module, and a signal reading module. The bias module includes a PMOS tube 3 and two NMOS tubes 4 and 5; the negative feedback module It includes two PMOS transistors 6 and 7, three NMOS transistors 8, 9, and 10, two NPN bipolar transistors Q1 and Q2, a resistor R, and a capacitor C; the signal reading module includes three PMOS transistors 2 , 1, 11; the output end of the bias module is connected with the input end of the negative feedback module, the output end of the negative feedback module is connected with the input end of the bias module, and the output end of the negative feedback module is connected with the input end of the signal reading module The output terminal of the signal reading module is connected to the input terminal of the negative feedback module.

Compared with the prior art, the present invention has the following advantages:

First, the present invention utilizes two NPN bipolar transistors Q1 and Q2 and resistors in the negative feedback module to provide quiescent current for the signal reading module, and uses NPN bipolar transistors to overcome the problem of high noise in the prior art , so that the present invention has the advantage of reducing noise.

Second, in the present invention, the currents flowing through the two NPN bipolar transistors are different due to the different voltages between the collectors and the emitters of the two NPN bipolar transistors. system imbalance, so that the present invention has the advantage of reducing system imbalance.

Third, the present invention utilizes the negative feedback loop in the negative feedback module to feedback the quiescent current, which overcomes the disadvantages of high power consumption and high noise of the circuit in the prior art, so that the present invention not only stabilizes the signal reading module In addition, the quiescent current in the NPN bipolar transistor and the second PMOS transistor 1 in the signal reading module are suppressed, and the 1/f noise of all other tubes is suppressed.

Fourth, the present invention uses the PMOS transistor 11 in the signal reading module to provide a DC bias for the signal input terminal, and at the same time, the PMOS transistor 11 ensures high input impedance, and the PMOS transistor 11 is a diode connection with a gate and a drain connected together. The method works in the deep sub-threshold region, which overcomes the disadvantage that the method of realizing high input impedance in the prior art is relatively complicated, so that the occupied area of the chip in the present invention is reduced.

Description of drawings

1 is an electrical schematic diagram of the present invention;

FIG. 2 is a simulation result diagram of equivalent input noise of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

Referring to FIG. 1 , the specific circuit of the present invention will be further described.

The electrical schematic diagram of the present invention is divided into three parts: a bias module, a negative feedback module, and a signal reading module by the dotted line in FIG. 1 .

The electrical schematic diagram of the present invention The bias module described by the dotted line in FIG. 1 includes a PMOS transistor 3 and two NMOS transistors 4 and 5. The output end of the bias module is connected to the input end of the negative feedback module. The bias module The input end is connected with the output end of the negative feedback module.

The gate of the PMOS tube 3 in the bias module is respectively connected with the drain of the second PMOS tube 7 in the negative feedback module, the drain of the third NMOS tube 10 in the negative feedback module, and the capacitor C in the negative feedback module. The gate of the first PMOS tube 2 in the signal reading module is connected, the source of the PMOS tube 3 is connected to the power supply voltage VCC, and the drain of the PMOS tube 3 is respectively connected to the first NMOS tube 4 in the bias module. The drain of , the gate of the first NMOS transistor 4 in the bias module, and the gate of the first NMOS transistor 8 in the negative feedback module are connected. The source of the first NMOS transistor 4 in the bias module is respectively connected to the drain of the second NMOS transistor 5 in the bias module and the gate of the second NMOS transistor 5 in the bias module. The source of the second NMOS transistor 5 in the bias module is connected to the common ground terminal GND.

The negative feedback module described by the dotted line in the electrical schematic diagram of the present invention includes two PMOS transistors 6 and 7, three NMOS transistors 8, 9, 10, two NPN bipolar transistors Q ₁ and Q ₂ , A resistor R, a capacitor C, the output terminal of the negative feedback module is connected to the input terminal of the bias module, the output terminal of the negative feedback module is connected to the input terminal of the signal reading module, and the input terminal of the negative feedback module is connected to the input terminal of the bias module. output connection.

The gate of the first PMOS tube 6 in the negative feedback module is connected to its drain, the drain of the first NMOS tube 8 in the negative feedback module, and the gate of the second PMOS tube 7 in the negative feedback module, respectively. The source of the first PMOS transistor 6 in the feedback module is connected to the power supply voltage VCC. The source of the second PMOS tube 7 in the negative feedback module is connected to the power supply voltage VCC, and the drain of the second PMOS tube 7 in the negative feedback module is respectively connected to the drain of the third NMOS tube 10 in the negative feedback module. , The capacitor C in the negative feedback module, the gate of the PMOS tube 3 in the bias module, and the gate of the first PMOS tube 2 in the signal reading module are connected. The gate of the first NMOS tube 8 in the negative feedback module is respectively connected with the drain of the PMOS tube 3 in the bias module, the drain of the first NMOS tube 4 in the bias module, and the first NMOS tube 4 in the bias module. The gates of the first NMOS transistors 4 are connected, and the source of the first NMOS transistor 8 is connected to the collector of the _first NPN bipolar transistor Q1 in the negative feedback module. The base of the _first NPN bipolar transistor Q1 in the negative feedback module is respectively connected with the base of the second NPN bipolar transistor _Q2 in the negative feedback module, the resistor R in the negative feedback module, the negative feedback module The capacitor C in the signal reading module is connected to the drain of the second PMOS transistor ₁ , and the emitter of the first NPN bipolar transistor Q1 is connected to the common ground terminal GND. The collector of the second NPN bipolar transistor _Q2 in the negative feedback module is respectively connected with the drain of the second NMOS transistor 9 in the negative feedback module, the gate of the second NMOS transistor 9 in the negative feedback module, The gate of the third NMOS tube 10 in the negative feedback module is connected to the current source I _REF , and the emitter of the second NPN bipolar transistor _Q2 is connected to the common ground terminal GND; the second NMOS in the negative feedback module The source of the tube 9 is connected to the common ground terminal GND. The source of the third NMOS transistor 10 in the negative feedback module is connected to the common ground terminal GND. The capacitor C in the negative feedback module is connected in series with the resistor R in the negative feedback module, and is respectively connected to the drain of the second PMOS transistor 7 in the negative feedback module and the common ground terminal GND.

The electrical schematic diagram of the present invention The signal reading module described by the dotted line in FIG. 1 includes three PMOS transistors 2, 1 and 11. The output end of the signal reading module is connected to the input end of the negative feedback module. The signal reading module The input end is connected with the output end of the negative feedback module.

The gate of the first PMOS tube 2 in the signal reading module is respectively connected with the gate of the PMOS tube 3 in the bias module, the drain of the second PMOS tube 7 in the negative feedback module, and the third in the negative feedback module. The drain of each NMOS transistor 10 is connected to the capacitor C in the negative feedback module, the source of the first PMOS transistor 2 is connected to the power supply voltage VCC, and the drain of the first PMOS transistor 2 is connected to the second in the signal reading module. The source of each PMOS transistor 1 is connected. The gate of the second PMOS tube 1 in the signal reading module is connected to the source of the third PMOS tube 11 in the signal reading module, and the drain of the second PMOS tube 1 is respectively connected with the third PMOS tube 1 in the negative feedback module. The base of _one NPN bipolar transistor Q1, the base of the second NPN bipolar transistor _Q2 in the negative feedback module, the resistor R in the negative feedback module, and the capacitor C in the negative feedback module are connected. The gate of the third PMOS transistor 11 in the signal reading module is connected to its drain and the common ground terminal GND respectively.

The effects of the present invention will be further described below in conjunction with simulation experiments.

1. Simulation conditions:

The simulation experiment of the present invention is realized based on the 0.18 μm BCD process and using the Spectre simulation tool of the Cadence software. The power supply voltage is set to 3V, the simulation temperature is set to normal temperature (25°C), and the scanning frequency range is 1Hz to 10MHz.

2. Simulation content:

Under the software LINUX operating system, based on the 0.18 μm BCD process, the equivalent input noise simulation of the buffer circuit of the present invention is performed by using the Spectre simulation tool of the Cadence software. The power supply voltage is set to 3V, the simulation temperature is set to normal temperature (25°C), and the scanning frequency range is 1Hz to 10MHz. The device parameters are set reasonably so that the buffer circuit can meet the requirements of low noise within the audio bandwidth range.

3. Analysis of simulation results:

FIG. 2 of the present invention is a simulation result diagram of the equivalent input noise of the present invention. The abscissa axis in Fig. 2 represents the frequency, and the ordinate axis represents the equivalent input noise. The point M0 marked with a triangle represents the equivalent input noise value at a frequency of 20.0Hz, the point M1 marked with a circle represents the equivalent input noise value at a frequency of 20KHz, and the point M2 marked with a square represents the equivalent input noise at a frequency of 1KHz value. It can be seen from the simulation Fig. 2 of the present invention that the abscissa of point M0 is 20.0Hz, the ordinate of point M0 is 119.6nV/sqrt(Hz), the abscissa of point M1 is 20KHz, and the ordinate of point M1 is 8.433nV/sqrt(Hz). The rms value of the equivalent input noise over the bandwidth is in the nV level. The ordinate of point M2 is 18.66nV/sqrt(Hz), and the marking line is at the position of 1KHz on the abscissa, indicating that the equivalent input noise when the frequency is 1KHz is only 18.66nV/sqrt(Hz). To sum up, the buffer circuit of the present invention meets the requirement of low noise.

Claims (1)

1. a kind of buffer circuits of low noise MEMS microphone, including biasing module, negative feedback module, signal reading module, It is characterized in that, the biasing module includes a PMOS tube (3), two NMOS tubes (4,5)；In the biasing module The grid of one PMOS tube (3), respectively and in the drain electrode of second PMOS tube (7) in negative feedback module, negative feedback module The drain electrode of third NMOS tube (10), the capacitor C in negative feedback module, first PMOS tube (2) in signal reading module Grid connection；The source electrode of first PMOS tube (3) in biasing module is connect with supply voltage VCC；First in biasing module A PMOS tube (3) drain electrode respectively with first in the drain electrode of first NMOS tube (4) in biasing module, biasing module The grid connection of the grid of NMOS tube (4), first NMOS tube (8) in negative feedback module；First in the biasing module The source electrode of a NMOS tube (4) respectively with second in the drain electrode of second NMOS tube (5) in biasing module, biasing module The grid of NMOS tube (5) connects；The source electrode of second NMOS tube (5) in the biasing module is connect with common GND；

The negative feedback module includes two PMOS tube (6,7), three NMOS tubes (8,9,10), two NPN bipolar transistor Q₁ And Q₂, a resistance R, a capacitor C；The grid of first PMOS tube (6) in the negative feedback module is leaked with it respectively The drain electrode of first NMOS tube (8) in pole, negative feedback module, second PMOS tube (7) in negative feedback module grid connect It connects；The source electrode of first PMOS tube (6) in negative feedback module is connect with supply voltage VCC；In the negative feedback module The source electrode of two PMOS tube (7) is connect with supply voltage VCC, the drain electrode difference of second in negative feedback module PMOS tube (7) The capacitor C in drain electrode, negative feedback module with the third NMOS tube (10) in negative feedback module, the PMOS tube in biasing module (3) the grid connection of grid, first PMOS tube (2) in signal reading module；First in the negative feedback module The grid of NMOS tube (8) respectively with first NMOS tube (4) in the drain electrode of the PMOS tube (3) in biasing module, biasing module Drain electrode, first NMOS tube (4) in biasing module grid connection, first NMOS tube (8) in negative feedback module First NPN bipolar transistor Q in source electrode and negative feedback module₁Collector connection；In the negative feedback module One NPN bipolar transistor Q₁Base stage respectively with second NPN bipolar transistor Q in negative feedback module₂Base stage, The drain electrode of the capacitor C in resistance R, negative feedback module, second PMOS tube (1) in signal reading module in negative feedback module Connection；First NPN bipolar transistor Q in negative feedback module₁Emitter connect with common GND；It is described negative anti- Present second NPN bipolar transistor Q in module₂Collector respectively with second NMOS tube (9) in negative feedback module Drain electrode, the grid of second NMOS tube (9) in negative feedback module, third NMOS tube (10) in negative feedback module grid Pole, current source I_REFConnection；Second NPN bipolar transistor Q in negative feedback module₂Emitter and common GND connect It connects；The source electrode of second NMOS tube (9) in the negative feedback module is connect with common GND；In the negative feedback module The source electrode of third NMOS tube (10) connect with common GND；Capacitor C and negative feedback module in the negative feedback module In resistance R series connection after the drain electrode with second PMOS tube (7) in negative feedback module respectively again, common GND connection；

The signal reading module includes three PMOS tube (2,1,11)；First PMOS tube in the signal reading module (2) grid respectively with second PMOS tube in the grid of first PMOS tube (3) in biasing module, negative feedback module (7) drain electrode, the drain electrode of the third NMOS tube (10) in negative feedback module, the capacitor C connection in negative feedback module, signal are read The source electrode of first PMOS tube (2) in modulus block is connect with supply voltage VCC；First PMOS tube in signal reading module (2) source electrode of second PMOS tube (1) in drain electrode and signal reading module connects；Second in the signal reading module The source electrode of third PMOS tube (11) in the grid and signal reading module of a PMOS tube (1) connects, in signal reading module Second PMOS tube (1) drain electrode respectively with first NPN bipolar transistor Q in negative feedback module₁Base stage, negative anti- Present second NPN bipolar transistor Q in module₂Base stage, the resistance R in negative feedback module, the electricity in negative feedback module Hold C connection；The grid of third PMOS tube (11) in the signal reading module drains with it respectively, common GND connects It connects；

The output end of the biasing module and the input terminal of negative feedback module connect, the output end and biasing module of negative feedback module Input terminal connection, the input terminal of the output end of negative feedback module and signal reading module connects, the output of signal reading module End is connected to the input terminal of negative feedback module.