CN108563144A - A kind of missile-borne radar signal processing semi-hardware type simulation test system - Google Patents

Abstract

The invention belongs to the field of radar signal simulation processing, and discloses a semi-physical simulation test system for missile-borne radar signal processing, including a radar seeker comprehensive test device, an analog-to-digital conversion module, an FPGA preprocessing module, a DSP imaging processing module, and a host computer Display terminal; the signal source outputs two reference clocks, one for the radar seeker comprehensive test device as a reference clock, one for the signal processor as a sampling clock, and the radar seeker comprehensive test device outputs simulated radar echo signals and frames Synchronization and pulse synchronization signal, the analog-to-digital conversion module completes the A/D sampling of the simulated radar echo, FPGA is used as the preprocessing module to complete the data preprocessing and data ping-pong transmission, and the two DSP chips in the DSP imaging processing module complete the imaging processing , another DSP chip completes the transmission of the imaging results to the host computer, and displays the imaging processing results in real time on the display terminal of the host computer.

Description

A hardware-in-the-loop simulation test system for missile-borne radar signal processing

technical field

The invention belongs to the technical field of radar signal simulation processing, and in particular relates to a hardware-in-the-loop simulation test system for missile-borne radar signal processing, which is used in the fields of high-speed aircraft imaging tracking guidance and the like.

Background technique

In order to adapt to the increasingly complex battlefield environment, the rapid development of radar technology also puts forward higher requirements for modern real-time signal processing algorithms. Synthetic aperture radar signal processing technology has also become a hot spot for exploration and development in various countries. However, the performance of signal processing algorithms cannot be limited to theoretical simulation, and needs to be further verified in practical applications.

In the previous test and verification process of synthetic aperture radar signal processors, there are the following defects: First, the actual performance of signal processors often needs to be verified by field experiments. and other external conditions; second, the actual missile-borne signal processing board is one bomb and one board, and there is no unified hardware platform, which brings great difficulties to the verification of the new algorithm; the third is the full physical seeker There are many peripherals in the system and the cost is high, and the test and verification of the signal processing algorithm will bring additional overhead. Therefore, the construction of hardware-in-the-loop simulation test system for radar signal processing is very necessary for the simulation test of signal processor in the laboratory stage.

Contents of the invention

In view of the above problems, the object of the present invention is to provide a hardware-in-the-loop simulation test system for missile-borne radar signal processing, which makes the laboratory stage test verification closer to the field experiment, and is used to solve the problem that the field experiment is easily affected by the environment, the development cycle is long, and the cost is high. series of questions.

The radar signal processing hardware-in-the-loop simulation test system uses the radar seeker comprehensive test device to simulate the actual radar front-end output simulated radar echo, and completes a series of signal processing algorithms in the signal processor, thereby verifying the performance of the signal processing algorithm and the work of the signal processing system Is it normal.

In order to achieve the above object, the present invention adopts the following technical solutions to achieve.

A hardware-in-the-loop simulation test system for missile-borne radar signal processing, the system includes: a clock signal source, a radar seeker comprehensive test device, a signal processor, and an upper computer display terminal; the signal processor includes: an analog-to-digital conversion module , FPGA signal preprocessing module, DSP imaging processing module;

The reference clock output terminal provided on the clock signal source is connected with the reference clock input terminal provided on the radar seeker comprehensive testing device;

The sampling clock output terminal set on the clock signal source is connected to the sampling clock input terminal set on the analog-to-digital conversion module;

The analog signal output terminal provided on the radar seeker comprehensive test device is connected with the analog signal input terminal provided on the analog-to-digital conversion module;

The synchronous signal output terminal that is provided with on the radar seeker comprehensive testing device is connected with the synchronous signal input terminal of the FPGA signal preprocessing module;

The digital signal output end of described analog-to-digital conversion module is connected with the digital signal input end of described FPGA signal preprocessing module;

The digital signal output end of described FPGA signal preprocessing module is connected with the digital signal input end of described DSP imaging processing module;

The digital signal output end of the DSP imaging processing module is connected with the digital signal input end of the host computer display terminal through Ethernet.

Features and further improvements of the technical solution of the present invention are:

(1) The radar seeker comprehensive test device is used to obtain the simulated radar echo signal from the simulation software, complete the conversion of the simulated radar echo signal to the simulated radar echo signal, and convert the simulated radar echo signal The signal is sent to the four-way analog signal input terminal of the analog-to-digital conversion module through the four-way SMA interface;

The radar seeker comprehensive test device is also used to set the radar echo frame synchronization signal and the pulse synchronization signal, and send the radar echo frame synchronization signal and the pulse synchronization signal to the FPGA signal preprocessing through the BNC interface module;

The analog-to-digital conversion module is used to sequentially amplify the analog radar echo signal, perform single-ended to differential operation and A/D sampling, and send the digital radar signal obtained after sampling to the FPGA signal through a 12-bit LVDS interface preprocessing module;

The FPGA signal preprocessing module is used to sequentially perform digital down-conversion and pulse compression preprocessing operations on the digital radar signal according to the radar echo frame synchronization signal and pulse synchronization signal, to obtain the preprocessed digital radar signal , and sending the preprocessed digital radar signal to the DSP imaging processing module through the SRIO interface ping-pong;

The DSP imaging processing module is used to image the preprocessed digital radar signal, and send the radar signal imaging result to the upper computer display terminal through Gigabit Ethernet;

The display terminal of the host computer is used to display the radar signal imaging results in real time.

(2) The analog-to-digital conversion module includes: four amplifiers and four A/D converters, and the four amplifiers are correspondingly connected to the four A/D converters;

The amplifier is used to amplify the input analog radar echo signal, and convert the single-ended signal into a differential signal; the gain of the amplifier amplifying the analog radar echo signal is performed by the FPGA signal preprocessing module through the SPI interface control;

The A/D converter is used to perform A/D sampling on the amplified differential signal to obtain a digital radar signal, and send the digital radar signal to an FPGA signal preprocessing module.

(3) said FPGA signal preprocessing module comprises: data collation submodule, digital down-conversion submodule, pulse compression submodule, data buffer submodule and SRIO transmission submodule;

The data sorting sub-module is used to sort out the digital radar signal, change the unsigned number into a signed number, expand the data bit width from 12 bits to 16 bits, and convert the The number of data points is intercepted to 4096 points, and the data is converted to the clock domain and transmitted to the digital down-conversion module;

The digital down-conversion sub-module is used to receive the data processed by the data sorting sub-module, mix and filter the data according to the radar echo frame synchronization signal and pulse synchronization signal, and generate the radar echo frame synchronization signal and pulse synchronization signal The signal is sent to the pulse compression sub-module;

The pulse compression sub-module is used to receive the data processed by the digital down-conversion sub-module, and perform 4096-point FFT operations, matched filtering and 4096-point IFFT operations on the data according to the radar echo frame synchronization signal and the pulse synchronization signal, and generate The radar echo frame synchronization signal and pulse synchronization signal are sent to the data buffer sub-module;

The data buffering submodule is used to perform clock domain conversion on data, and provides a pulse start transmission flag for the SRIO transmission submodule;

The SRIO transmission sub-module is used to receive data from the data buffer sub-module, detect the frame start flag, complete the SRIO stream writing protocol, and ping-pong transmit the data to the DSP imaging processing module.

(4) described DSP image processing module comprises three DSP chips, is respectively marked as DSP1, DSP2, DSP3; Described DSP1 is connected with DSP2 by Hyperlink interface, and described DSP3 is connected with DSP2 by PCI-Express interface;

The FPGA signal preprocessing module is used to send 4096 pulse data to DSP1, and then send data with the same amount of data to DSP3, alternate between DSP1 and DSP3 in turn, and ping-pong the preprocessed digital radar signal through the SRIO interface Send to the DSP imaging processing module;

The DSP1 and the DSP3 are used to ping-pong receive the preprocessed digital radar signal sent by the FPGA signal preprocessing module; and perform Doppler center estimation and distance walking correction to the received preprocessed digital radar signal respectively , the imaging process of range bending correction, secondary range pulse pressure, motion error estimation and compensation, azimuth compression and geometric correction to obtain the radar signal imaging result, and send the radar signal imaging result to DSP2;

The DSP2 sends the imaging result of the radar signal to the display terminal of the host computer through Gigabit Ethernet.

(5) The DSP2 is connected to the Gigabit Ethernet conversion chip through the SGMII interface, and the Gigabit Ethernet conversion chip is connected to the host computer display terminal through the RJ45 network port.

The present invention has the following advantages: the first, the present invention is owing to adopt radar seeker comprehensive testing device, and this device has the solid-state hard disk of 8192GB, and storage capacity is large, can play back the radar echo signal of the arbitrary data amount that MATALB produces; Two, the radar seeker comprehensive test device of the present invention has the DA chip of four roads up to 500MHz, can play back the radar intermediate frequency echo signals of up to four roads that meet the hardware parameters that MATLAB produces, and the four road signals can be the same or different, The multi-channel verification of the signal processing board can be completed at the same time; the 3rd, the present invention has one reference clock input interface, one frame synchronization and one pulse synchronization output interface, and the echo data is according to the above-mentioned Three kinds of signals are played back, and simulate actual radar front-end work situation; The 4th, the FPGA chip involved in the present invention selects the Virtex-6 series chip that logic resource, memory resource, DSP resource are richer, and DSP chip also selects the TMS320C6678 chip of the highest performance in the industry , each piece of DSP all plug-in capacity is the DDR SDRAM chip of 2GByte, to satisfy this system to the requirement of processing large amount of data and operation complex algorithm; SRIO completes the data transmission with the DSP1 and DSP3 chips, and another DSP2 chip communicates with the host computer through the Gigabit Ethernet chip, which overcomes the shortcoming of the slow transmission rate of the prior art, improves the real-time performance of the present invention, and satisfies the requirements of the missile-borne radar signal. The processor system requires high real-time performance and rapidity; sixth, the implementation process of the present invention is simple, and the function of the signal processing board can be tested and verified in the laboratory, which is not affected by external conditions, saves manpower and material resources, and saves The time period and development cost of field experiments; Seventh, the system equipment of the present invention is less, convenient to connect, and the cost is lower; Eighth, the present invention can replace the signal processing board or signal processing algorithm, and complete Verification, strong versatility.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the realization structural block diagram of missile-borne radar signal processing hardware-in-the-loop simulation test system of the present invention;

Fig. 2 is a schematic diagram of the connection between the radar seeker comprehensive testing device of the present invention and the signal processor;

Fig. 3 is the schematic diagram of connection between the analog-to-digital conversion module of the present invention and the FPGA preprocessing module;

Fig. 4 is the connection schematic diagram between DSP imaging processing module of the present invention and FPGA preprocessing module;

Fig. 5 is a schematic diagram of the connection between the host computer display terminal and the signal processor of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The present invention will be further described below in conjunction with the accompanying drawings.

According to accompanying drawing 1, the present invention comprises following several modules altogether: radar seeker comprehensive testing device, signal processor and host computer display terminal. in:

The radar seeker comprehensive test device is mainly used to generate multiple synchronous simulated radar echo signals. There are 4 SMA D/A output interfaces on the rear panel of the radar seeker comprehensive test device. The maximum conversion rate of the DA chip is 500MHz, the resolution is 16bit, one external reference clock input interface, one frame synchronization output interface and one pulse Synchronous output interface.

The radar seeker comprehensive test device mainly has the following functions: used for format conversion from MATLAB simulation echo data to radar seeker comprehensive test device echo data; used for echo data to radar seeker comprehensive test device SSD Import and browse; used to set the playback parameters of the radar seeker comprehensive test device; used to output multiple analog radar echo signals to the signal processor; used to output radar echo frame synchronization and pulse synchronization signals to the signal processor.

Signal processor, including analog-to-digital conversion module, FPGA preprocessing module and DSP imaging processing module.

The analog-to-digital conversion module adopts four pieces of analog-to-digital conversion chip ADS5463, but is not limited to this chip, the maximum sampling rate of the chip is 500MSPS (how many megabytes of samples per second), 12-bit LVDS output, one-way with the radar seeker comprehensive test device Connection, two-way connection with the FPGA preprocessing module, used to receive and sample the simulated radar echo output by the radar seeker comprehensive test device, because the radar seeker comprehensive test device gives a single-ended signal, and its peak-to-peak value It is 1.2Vpp, so first use the amplifier AD8370 of ADI company to convert the collected analog signal into a differential signal and amplify it. The gain of the output signal of the AD8370 chip can be modified by the FPGA chip through the SPI interface. Control, and then output the differential signal output by AD8370 to ADS5463 to complete the analog-to-digital conversion, and finally send the sampled data to the FPGA preprocessing module.

The FPGA preprocessing module selects a Virtex-6 series high-performance XC6VLX240T-FF1156 chip from XILINX Company, but it is not limited to this chip. The number of logic units of this chip reaches 241,152, the number of DSP48E1 slices reaches 768, and the speed is as high as 600MHz. There are 600 single-ended pins and 20 high-speed serial transceivers, which can realize various high-speed serial bus protocols. The FPGA preprocessing module is bidirectionally connected with the analog-to-digital conversion module and bidirectionally connected with the DSP imaging processing module.

The FPGA preprocessing module includes a data sorting submodule, a digital down-conversion submodule, a pulse compression submodule, a data buffering submodule, and an SRIO transmission submodule. The echo data is sorted, the unsigned number is changed into a signed number, and the data bit width is expanded from 12 bits to 16 bits, and the number of data points in each pulse repetition cycle is intercepted to 4096 points, and the data is clock domain Convert and transmit to the digital down-conversion module; the digital down-conversion sub-module is used to receive the data processed by the data sorting sub-module, mix and filter the data according to the synchronization signal, and generate frame synchronization and pulse synchronization signals , sent to the pulse compression sub-module; the pulse compression sub-module is used to receive the data processed by the digital down-conversion sub-module, and perform 4096-point FFT operations, matched filtering and 4096-point IFFT operations on the data according to the pulse synchronization signal, And generate frame synchronization and pulse synchronization signals, sent to the data buffer sub-module; the data buffer sub-module, the data clock domain conversion, and for the SRIO transmission sub-module to provide a pulse start transmission flag; the SRIO transmission sub-module Module, used to receive the data of the data buffer sub-module, used to detect the frame start flag, used to complete the SRIO stream writing protocol, and transmit the ping-pong data to the DSP1 and DSP3 chips, after it sends 4096 pulse data to a DSP chip , and then send the same amount of data to another DSP chip, and rotate between the two DSP chips in turn to complete the doorbell interrupt transmission.

The DSP imaging processing module uses three TI DSP chips of the type TMS320C6678, but is not limited to this chip. The chip has 8 high-performance fixed-point/floating-point CPU cores with a rate of up to 1.25GHz, and there are 4096KB multi-core in the chip. Shared memory, the maximum 8GB DDR3 memory can be expanded outside the chip, the maximum running speed of the off-chip DDR3 is 1600MHz, it has 4 SRIO channels, compatible with 1.25, 2.5, 3.125 and 5Gbps working speed, and each DSP chip has an external DDR with a capacity of 2GByte The SDRAM chip is used to store the data and imaging results sent by the FPGA pre-processing module. DSP1 and DSP3 are used to ping-pong receive the pre-processed data sent by the FPGA pre-processing module; DSP1 and DSP3 are used for Doppler center estimation, distance Walking correction, distance bending correction, secondary distance pulse pressure, motion error estimation and compensation, azimuth compression and geometric correction algorithm, complete imaging processing, and send imaging results to DSP2 chip through Hyperlink interface and PCI-Express interface; DSP2 chip uses It is used to send the imaging results sent by DSP1 and DSP3 to the display terminal of the host computer through Gigabit Ethernet.

The display terminal of the upper computer is bidirectionally connected with the signal processor through a network cable. During the system implementation, the DSP2 chip sends the SAR image obtained by DSP1 and DSP3 in the DSP imaging processing module to the upper computer through Gigabit Ethernet, and displays it on the upper computer. The imaging results are displayed in real time on the terminal.

With reference to accompanying drawing 2, the connection between the radar seeker comprehensive test device and the signal processor is described further.

The radar seeker comprehensive test device has four SMA form D/A output interfaces: SMA1, SMA2, SMA3, SMA4, which can output up to four channels of coherent signals at the same time, and the DA output interface is connected to the analog-to-digital conversion module through the coaxial cable. The four-way A/D input interface AD1, AD2, AD3, AD4 is connected, the reference clock input interface CLK_IN of the radar seeker comprehensive test device is connected with one output of the signal source, and the signal processor AD sampling clock input interface ADC_CLK is connected with the signal source The other output is connected, the frame synchronization signal IPPS_OUT and the pulse synchronization signal TRIG_OUT of the radar seeker comprehensive test device are output through the BNC interface, and then connected to the frame synchronization input sync_frame and the pulse synchronization input sync_pulse of the signal processor through the coaxial cable, Provide reference for FPGA data preprocessing.

Referring to accompanying drawing 3, the connection between the analog-to-digital conversion module and the FPGA preprocessing module is further described.

The analog-to-digital conversion module uses four A/D conversion chips, and the chip uses TI's ADS5463 for the acquisition of analog radar intermediate frequency echo signals. First, we choose ADI's amplifier AD8370 to convert the collected analog signals into single-ended signals. The differential signal is amplified, and the FPGA chip modifies the AD8370 on-chip register value through the SPI interface to control the gain of the output signal. The specific control signals are DATA, CLK, and LATCH. After that, the AD8370 chip transmits the differential signal to the ADS5463. Perform A/D sampling and send the data to the FPGA preprocessing module. The main signal lines connecting the analog-to-digital conversion chip ADS5463 and the FPGA chip are as follows: ADC_P[11:0], ADC_N[11:0], which are low-voltage differential signals, used to transmit A/D sampling data, and the data output mode is DDR Mode; OVR_P, OVR_N are data overflow signal lines, used to indicate whether the input signal value overflows; DRY_P, DRY_N are data ready signal lines, used to indicate that the sampling has been completed.

With reference to accompanying drawing 4, the connection between the DSP imaging processing module and the FPGA preprocessing module is described further.

The DSP imaging processing module uses three DSP chips of the model TMS320C6678, and the three DSP chips are connected to the FPGA preprocessing module through the Serial Rapid IO (SRIO) interface. In the FPGA, there are five MGT high-speed transceiver modules of BANK112-BANK116. Among the present invention, BANK112 links to each other with DSP3; BANK113 links to each other with DSP1, and BANK116 links to each other with DSP2, and these three SRIO interfaces are set to 4 channels, and the rate of each channel is 3.125GHz, and terminal device is the source or the destination of data packet, different Terminal devices are distinguished by device ID. The ID numbers of FPGA are 0xFF, 0x AA, and 0x 55, the ID number of DSP1 is D1, the ID number of DSP2 is D2, and the ID number of DSP3 is D3.本发明中高速串行通信接口SRIO时钟频率为125MHz，串行通信接口采用以下信号线：srio_txp0、srio_txn0、srio_txpl、srio_txn1、srio_txp2、srio_txn2、srio_txp3、srio_txn3；srio_rxp0、srio_rxn0、srio_rxp1、srio_rxn1、srio_rxp2、srio_rxn2 , srio_rxp3, and srio_rxn3 are serial differential forms. After DSP1 and DSP3 complete the imaging algorithm, the imaging result should be sent to DSP2 through the Hyperlink interface and PCI-Express interface, and DSP2 will transmit the data from the signal processing board to the display terminal of the upper computer for real-time display of the result.

Referring to Fig. 5, the connection between the host computer display terminal and the signal processor will be further described.

The SGMII interface of the DSP2 chip is connected to the Gigabit Ethernet conversion chip. The Gigabit Ethernet conversion chip uses the 88EE1111 chip. The specific connection uses the following signal lines: DSP2_SGMII1_RXP, DSP2_SGMII1_RXN, DSP2_SGMII1_TXP, DSP2_SGMII1_TXN. The signal lines are differential data transmission lines; DSP2_MDIO is the bidirectional IO control line of the Ethernet conversion chip, and DSP2_MDC is the clock line of the Ethernet conversion chip. The conversion chip is connected to an RJ45 network port, communicates with the host computer through the RJ45 connection network cable, and transmits the imaging processing results in real time.

Working principle in the implementation process of the present invention is described as follows:

Echo simulation. Customize the echo parameters according to the test needs, simulate the echo data in MATLAB, write the data into a file with the suffix .dat, complete the data conversion in the data conversion software, and add 32 words before each pulse data Section header information, this header is mainly used for the analysis of the echo simulation data by the internal hardware of the system. After the data conversion is completed, the data to be played back needs to be stored in the SSD (solid state drive) through the embedded computer. After the data is imported, it needs to be Browse the data on the software interface. After confirming that the imported data is correct, configure the system parameters, including clock source, reference clock, pulse repetition frequency, frame pulse number and pulse width. After the setting is completed, enter the playback interface, select the playback mode, and wait for the signal processing board Power-on.

system connection. Connect the reference clock input interface of the radar seeker comprehensive test device with the signal source output interface through a coaxial cable, and connect the AD sampling clock input interface of the signal processor with the other output interface of the signal source through a coaxial cable. The DA output interface of the radar seeker comprehensive test device is connected with the AD input interface of the signal processor through a coaxial cable, and the frame synchronization and pulse synchronization output interface of the radar seeker comprehensive test device are connected with the frame synchronization and pulse synchronization of the signal processor The input interface is connected through a coaxial cable, and the Ethernet interface of the signal processor is connected with the host computer through a network cable.

The signal processing board is powered on. Click the start playback button on the software interface of the radar seeker comprehensive test device, and output the simulated radar echo signal, frame synchronization and pulse synchronization signals under the action of the external reference clock, and the FPGA chip modifies the AD8370 on-chip register value through the SPI interface to control the output signal Gain, the analog-to-digital conversion module in the signal processor performs A/D conversion on the input analog radar echo signal when the sampling clock arrives, and the FPGA pre-processing module converts the analog-to-digital conversion module The transmitted data is preprocessed to realize digital down-conversion, fast Fourier transform, and range-to-pulse compression operations, and then the FPGA preprocessing module sends the preprocessed data to the DSP imaging processing module in ping-pong mode through the SerialRapid IO (SRIO) interface In DSP1 and DSP3, the FPGA preprocessing module will send a doorbell interrupt when sending data of 4096 pulse repetition periods. After receiving the interrupt, DSP1 and DSP3 will perform Doppler center estimation, distance walking correction, and Range bending correction, secondary range pulse pressure, motion error estimation and compensation, azimuth compression, and geometric correction algorithms complete the imaging processing, and then DSP1 and DSP3 send the processed results to DSP2 through Hyperlink interface and PCI-Express interface, and DSP2 The imaging processing results are transmitted to the display terminal of the host computer through Gigabit Ethernet, and real-time imaging is performed on the display terminal interface of the host computer.

The application of the present invention is not limited by external conditions, and can simulate the actual radar front-end work. In addition, the system also has the advantages of stability and reliability, large storage capacity, and high transmission rate. It is mainly suitable for laboratory stage in the field of imaging tracking guidance of high-speed aircraft Test verification.

Those of ordinary skill in the art can understand that all or part of the steps to realize the above method embodiments can be completed by hardware related to program instructions, and the aforementioned programs can be stored in computer-readable storage media. When the program is executed, the execution includes The steps of the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (6)

1. a kind of missile-borne radar signal processing semi-hardware type simulation test system, which is characterized in that the system comprises：Clock signal Source, radar seeker comprehensive test device, signal processor and host computer display terminal；The signal processor includes：Mould Number conversion module, FPGA signal pre-processing modules, DSP imaging modules；

It is arranged on the reference clock output end and the radar seeker comprehensive test device being arranged on the signal source of clock Reference clock input terminal connects；

The sampling clock output end being arranged on the signal source of clock and the sampling clock being arranged on the analog-to-digital conversion module are defeated Enter end connection；

The analog signal output being arranged on the radar seeker comprehensive test device is arranged on the analog-to-digital conversion module Input end of analog signal connection；

The synchronous signal output end being arranged on the radar seeker comprehensive test device and the FPGA signal pre-processing modules Synchronous signal input end connection；

The digital signal input end of the digital signal output end of the analog-to-digital conversion module and the FPGA signal pre-processing modules Connection；

The digital signal output end of the FPGA signal pre-processing modules and the digital signal of the DSP imagings module input End connection；

The digital signal output end of the DSP imagings module is believed by the number of Ethernet and the host computer display terminal The connection of number input terminal.

2. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 1, which is characterized in that

The radar seeker comprehensive test device is completed described imitative for obtaining emulation radar echo signal from simulation software True radar echo signal and is connect the guinea pig echo-signal by four road SMA to the conversion of guinea pig echo-signal Mouth is sent to four road input end of analog signal of analog-to-digital conversion module；

The radar seeker comprehensive test device is additionally operable to setting radar return frame synchronizing signal and pulse synchronous signal, and The radar return frame synchronizing signal and the pulse synchronous signal are sent to FPGA Signal Pretreatment moulds by bnc interface Block；

The analog-to-digital conversion module, for being amplified successively to the guinea pig echo-signal, single-ended transfer difference operation with And A/D samplings, and the digital radar signal obtained after A/D is sampled is sent to FPGA Signal Pretreatments by 12 LVDS interfaces Module；

The FPGA signal pre-processing modules are used for according to the radar return frame synchronizing signal and pulse synchronous signal to described Digital radar signal carries out the pretreatment operation of Digital Down Convert and pulse compression successively, obtains pretreated digital radar letter Number, and the pretreated digital radar signal is sent to DSP imaging modules by SRIO interfaces table tennis；

The DSP imagings module, for being imaged to the pretreated digital radar signal, and by radar signal Imaging results are sent to host computer display terminal by gigabit Ethernet；

The host computer display terminal is used for real-time display radar signal imaging results.

3. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute Stating analog-to-digital conversion module includes：Four amplifiers and four A/D converters, four amplifiers are converted with four A/D Device is correspondingly connected with；

The amplifier is amplified for the guinea pig echo-signal to input, and amplified single-ended signal is changed into Differential signal；The amplifier is passed through the gain that guinea pig echo-signal is amplified by FPGA signal pre-processing modules SPI interface is controlled；

The A/D converter samples to obtain digital radar signal for carrying out A/D to amplified differential signal, and will be described Digital radar signal is sent to FPGA signal pre-processing modules.

4. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute Stating FPGA signal pre-processing modules includes：Data preparation submodule, Digital Down Convert submodule, pulse compression submodule, data It buffers submodule and SRIO transmits submodule；

Unsigned number is become signed number for being arranged to the digital radar signal by the data preparation submodule, And by data bit width by 12 Bits Expandings be 16, and by each pulse repetition period data points interception be 4096 points, it is right Data carry out clock domain conversion, and are transmitted to Digital Down Converter Module；

The Digital Down Convert submodule, data that treated for receiving data preparation submodule are same according to radar return frame Step signal and pulse synchronous signal are mixed data, are filtered, and generate radar return frame synchronizing signal and impulsive synchronization letter Number, it is sent to pulse compression submodule；

Submodule is compressed in the pulse, data that treated for receiving Digital Down Convert submodule, and according to radar return frame Synchronizing signal and pulse synchronous signal carry out 4096 point FFT operations, matched filtering and 4096 point IFFT operations to data, and produce Raw radar return frame synchronizing signal and pulse synchronous signal, are sent to data buffering submodule；

The data buffering submodule for carrying out clock domain conversion to data, and transmits submodule for SRIO and provides pulse Begin transmission mark；

The SRIO transmits submodule, the data for receiving data buffering submodule, and detection frame beginning flag completes SRIO streams Agreement is write, data table tennis is transferred to DSP imaging modules.

5. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute It includes three dsp chips to state DSP imaging modules, is denoted as DSP1, DSP2, DSP3 respectively；The DSP1 passes through Hyperlink Interface is connect with DSP2, and the DSP3 is connect by PCI-Express interfaces with DSP2；

FPGA signal pre-processing modules, for sending 4096 pulse datas to DSP1 and then sending same data to DSP3 The pretreated digital radar signal is passed through SRIO interface table tennis by the data of amount, the rotation successively between DSP1 and DSP3 Pang be sent to DSP imaging modules；

The DSP1 and DSP3, for the pretreated digital radar for receiving the transmission of FPGA signal pre-processing modules of rattling Signal；And respectively to the pretreated digital radar signal that receives carry out Doppler center estimation, Range Walk Correction, away from From curvature correction, the imaging process of secondary range pulse pressure, motion error extraction and compensation, Azimuth Compression and geometric correction, obtain It is sent to DSP2 to radar signal imaging results, and by the radar signal imaging results；

Radar signal imaging results are sent to host computer display terminal by the DSP2 by gigabit Ethernet.

6. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 5, which is characterized in that institute It states DSP2 and gigabit Ethernet conversion chip is connected to by SGMII interfaces, the gigabit Ethernet conversion chip passes through RJ45 nets Mouth is connected to host computer display terminal.