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CN108563274A - A kind of continuously adjustable linearin-dB variable gain circuit structure - Google Patents

A kind of continuously adjustable linearin-dB variable gain circuit structure Download PDF

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CN108563274A
CN108563274A CN201810220134.2A CN201810220134A CN108563274A CN 108563274 A CN108563274 A CN 108563274A CN 201810220134 A CN201810220134 A CN 201810220134A CN 108563274 A CN108563274 A CN 108563274A
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CN108563274B (en
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鲁征浩
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    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
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    • G05F1/46Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
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Abstract

本发明公开了一种连续可调分贝线性可变增益电路结构,包括:放大器核心电路、共模输出偏置电路、指数比例电流产生电路、指数比例电流偏置电路;本发明提出的连续可调的精确分贝线性可变增益放大结构,通过三组负反馈结构,两组偏置复制结构和一个电流分流结构差分对的巧妙系统性设计,在一个电流舵结构的差分放大晶体管对中,在保证总电流不变即输出共模电压不变的情况下,简单有效且精确的实现了一个随着外加控制电压线性变化而呈指数变化的晶体管沟道电流,该电流决定了该晶体管的跨导也随着控制电压线性变化而呈指数变化,进而实现了一个满足分贝线性增益控制的连续可调可变增益放大器结构。

The invention discloses a continuously adjustable decibel linear variable gain circuit structure, including: an amplifier core circuit, a common-mode output bias circuit, an exponential proportional current generating circuit, and an exponential proportional current bias circuit; the continuously adjustable gain circuit proposed by the present invention The precise decibel linear variable gain amplification structure, through the ingenious systematic design of three sets of negative feedback structures, two sets of bias replication structures and a current shunt structure differential pair, in a differential amplifier transistor pair of a current steering structure, in ensuring When the total current is constant, that is, the output common-mode voltage is constant, a transistor channel current that changes exponentially with the linear change of the applied control voltage is simply, effectively and accurately realized. This current determines the transconductance of the transistor. As the control voltage changes exponentially, a continuously adjustable variable gain amplifier structure satisfying decibel linear gain control is realized.

Description

一种连续可调分贝线性可变增益电路结构A Continuously Adjustable Decibel Linear Variable Gain Circuit Structure

技术领域technical field

本发明涉及增益放大器,特别涉及一种新型的连续可调分贝线性可变增益电路结构。The invention relates to a gain amplifier, in particular to a novel continuously adjustable decibel linear variable gain circuit structure.

背景技术Background technique

可变增益放大电路广泛应用于通信电路系统中,例如自动增益控制等,以提高系统的动态范围。通常这种增益控制要求电路增益随着线性控制电压的变化而指数变化,即分贝线性(dB-Linear)变化。也就是说,控制电压是线性的,而增益是分贝线性的(指数变化)。实现这一功能有两大类方法,一类是基于离散的可编程分步数字增益控制机制,另一类是纯模拟的连续可调增益控制机制。在很多应用中,要求采用纯模拟的连续可调分贝线性控制以避免数字增益控制中所出现的毛刺现象。Variable gain amplifier circuits are widely used in communication circuit systems, such as automatic gain control, etc., to improve the dynamic range of the system. Usually this kind of gain control requires that the gain of the circuit changes exponentially with the change of the linear control voltage, that is, changes in decibels linearly (dB-Linear). That is, the control voltage is linear, while the gain is linear in decibels (exponential change). There are two broad approaches to this function, one based on a discrete programmable step-by-step digital gain control mechanism, and the other a purely analog continuously adjustable gain control mechanism. In many applications, pure analog continuously adjustable decibel linear control is required to avoid the glitch phenomenon that occurs in digital gain control.

纯模拟的连续可调分贝线性连续增益电路主要有以下几类实现方法,第一种是采用基于泰勒级数逼近的伪指数(pseudo-exponential)控制电路结构,这一种结构的缺点在于增益和电压之间的指数关系精度不高;第二种则是精确的分贝线性控制电路,通常是以三级管为核心,通过一系列转换电路以获得大范围的精确分贝线性增益控制关系,这一类电路应用范围广,但其难点在于大范围的精确分贝线性增益控制电路的设计,通常此类电路的分贝线性控制结构极为复杂。The pure analog continuously adjustable decibel linear continuous gain circuit mainly has the following types of implementation methods. The first is to use a pseudo-exponential control circuit structure based on Taylor series approximation. The disadvantage of this structure lies in the gain and The accuracy of the exponential relationship between the voltages is not high; the second is an accurate decibel linear control circuit, usually with a three-stage tube as the core, through a series of conversion circuits to obtain a wide range of accurate decibel linear gain control relationships, this Such circuits have a wide range of applications, but the difficulty lies in the design of large-scale accurate decibel linear gain control circuits. Usually, the decibel linear control structure of such circuits is extremely complex.

发明内容Contents of the invention

为此本发明提出连续可调分贝线性控制线路,通过提出一种新型指数电流产生和复制结构,以达到简化电路结构的目的。For this reason, the present invention proposes a continuously adjustable decibel linear control circuit, and achieves the purpose of simplifying the circuit structure by proposing a novel exponential current generation and replication structure.

本发明目的:在于提供一种新型的连续可调分贝线性可变增益电路结构,其电路结构简单,且实现的放大电路还具有可以控制的恒定共模输出电压的优点。The purpose of the present invention is to provide a novel continuously adjustable decibel linear variable gain circuit structure, the circuit structure is simple, and the realized amplifying circuit also has the advantage of a controllable constant common-mode output voltage.

为实现上述目的,本发明的采用如下技术方案:To achieve the above object, the present invention adopts the following technical solutions:

一种连续可调分贝线性可变增益电路结构,包括:放大器核心电路、共模输出偏置电路、指数比例电流产生电路、指数比例电流偏置电路;A continuously adjustable decibel linear variable gain circuit structure, comprising: an amplifier core circuit, a common-mode output bias circuit, an exponential proportional current generating circuit, and an exponential proportional current bias circuit;

所述放大器核心电路为差分对电流舵结构,包括场效应管M1、M2组成的差分对M1/M2、场效应管M3、M4组成的差分对M3/M4,一对差分负载电阻R1/R2,以及尾电流偏置晶体管M13,输入差分信号为VIN+/VIN-,分别连接差分对M1/M2的栅极,输出差分信号为VOUT+/VOUT-,VOUT+连接M2/M4的漏极,VOUT-连接M1/M3的漏极,差分对M1/M2的漏极分别通过电阻R1/R2连接高电平VDD,两对差分对M1/M2、M3/M4的源极分别连接到晶体管M13的漏极,M13的源极接地;The core circuit of the amplifier is a differential pair current steering structure, including a differential pair M 1 /M 2 composed of field effect transistors M1 and M2 , a differential pair M 3 /M 4 composed of field effect transistors M3 and M4, and a pair of differential load resistors R 1 /R 2 , and the tail current bias transistor M 13 , the input differential signal is V IN+ /V IN- , connected to the gates of the differential pair M 1 /M 2 respectively, and the output differential signal is V OUT+ /V OUT -, V OUT+ is connected to the drain of M 2 /M 4 , V OUT- is connected to the drain of M 1 /M 3 , and the drain of the differential pair M 1 /M 2 is respectively connected to the high-level VDD through the resistor R 1 /R 2 . The sources of the differential pairs M 1 /M 2 and M 3 /M 4 are respectively connected to the drain of the transistor M 13 , and the source of M 13 is grounded;

所述共模输出偏置电路生成电压VB1加载在M13栅极;The common-mode output bias circuit generates a voltage V B1 and loads it on the gate of M13 ;

所述指数比例电流产生电路和指数比例电流偏置电路依次连接,生成电压VB2加载在M3/M4栅极;通过电压VB1和电压VB2的联合作用,使得尾电流晶体管M13中的偏置电流为I0恒定可控,同时流过M1的沟道电流I1与I0呈指数关系,从而使增益呈分贝线性变化。The exponential proportional current generation circuit and the exponential proportional current bias circuit are sequentially connected to generate a voltage VB2 to be loaded on the gate of M3 / M4 ; through the joint action of the voltage VB1 and the voltage VB2 , the tail current transistor M13 The bias current I 0 is constant and controllable, and the channel current I 1 flowing through M 1 has an exponential relationship with I 0 , so that the gain changes linearly in decibels.

优选的,所述共模输出偏置电路,包括场效应管M5、M6组成的差分对M5/M6,场效应管M7、M8组成的差分对M7/M8,一对差分负载电阻R3/R4,以及尾电流偏置晶体管M14;差分对M5/M6栅极接外接共模电压VCM,M7/M8栅极上加的电压来自于指数比例电流偏置电路所产生的偏置电压VB2,差分负载电阻R3/R4的输出端短接在一起并连接到运算放大器OP1的正输入端,OP1的负输入端接共模参考电压VCM,OP1的输出端电压VB1接M14的栅极,形成负反馈回路。Preferably, the common mode output bias circuit includes a differential pair M 5 /M 6 composed of field effect transistors M5 and M6, a differential pair M 7 /M 8 composed of field effect transistors M7 and M8 , and a pair of differential load resistors R 3 /R 4 , and tail current bias transistor M 14 ; the gate of the differential pair M 5 /M 6 is connected to an external common-mode voltage V CM , and the voltage added to the gate of M 7 /M 8 comes from an exponential proportional current bias The bias voltage V B2 generated by the circuit, the output terminals of the differential load resistors R 3 /R 4 are shorted together and connected to the positive input terminal of the operational amplifier OP1, and the negative input terminal of OP1 is connected to the common-mode reference voltage V CM , OP1 The output terminal voltage VB1 is connected to the gate of M 14 to form a negative feedback loop.

优选的,所述共模输出偏置电路与放大器核心电路形成的负反馈回路,迫使共模输出偏置电路中的负载电阻R3/R4的输出端电压VX1等于VCM,则VDD-1/2*I0*R=VCM,I0由此公式决定,即I0=2*(VDD-VCM)/R。Preferably, the negative feedback loop formed by the common-mode output bias circuit and the amplifier core circuit forces the output terminal voltage V X1 of the load resistor R 3 /R 4 in the common-mode output bias circuit to be equal to V CM , then V DD -1/2*I 0 *R=V CM , I 0 is determined by this formula, that is, I 0 =2*(V DD −V CM )/R.

优选的,所述指数比例电流产生电路包括三极管Q1、Q2组成的差分结构三极管Q1/Q2,一对差分电阻R5/R6,尾电流晶体管M16及运算放大器OP2;运算放大器OP2的正输入端接Q2支路负载电阻R的输出端VX3,负输入端接外加共模电压VCM,OP2的输出端接的M16栅极,和M16及Q2形成负反馈回路。Preferably, the exponential proportional current generating circuit includes a differential structure transistor Q 1 /Q 2 composed of transistors Q 1 and Q 2 , a pair of differential resistors R 5 /R 6 , a tail current transistor M 16 and an operational amplifier OP2; The positive input terminal of OP2 is connected to the output terminal V X3 of the load resistance R of the Q 2 branch, the negative input terminal is connected to the external common mode voltage VCM, the output terminal of OP2 is connected to the gate of M 16 , and forms a negative feedback loop with M 16 and Q 2 .

优选的,所述指数比例电流偏置电路包括场效应管M9、M10组成的差分对M9/M10,场效应管M11、M12组成的差分对M11/M12,一对差分电阻对R7/R8,尾电流晶体管M15,以及运算放大器OP3,差分对M9/M10连接差分电阻对R7/R8,M11/M12直接连接到电源电压;尾电流晶体管M15栅极加载由共模输出偏置电路中产生的偏置电压VB1,电阻对R7/R8的输出端短接并连接到运算放大器OP3的负输入端,OP3的正输入端接指数比例电流产生电路产生的电压VY1,OP3的输出端产生偏置电压VB2,并加载到差分对M11/M12的栅极,构成负反馈回路。Preferably, the exponential proportional current bias circuit includes a differential pair M 9 /M 10 composed of field effect transistors M9 and M10, a differential pair M 11 /M 12 composed of field effect transistors M11 and M12, and a pair of differential resistor pairs R 7 /R 8 , the tail current transistor M 15 , and the operational amplifier OP3, the differential pair M 9 /M 10 is connected to the differential resistance pair R 7 /R 8 , and M 11 /M 12 is directly connected to the supply voltage; the gate of the tail current transistor M 15 Load the bias voltage V B1 generated by the common-mode output bias circuit, the output of the resistor pair R 7 /R 8 is shorted and connected to the negative input of the operational amplifier OP3, and the positive input of OP3 is connected to an exponentially proportional current The voltage V Y1 generated by the generation circuit, the output terminal of OP3 generates a bias voltage V B2 , which is loaded to the gate of the differential pair M 11 /M 12 to form a negative feedback loop.

优选的,所述差分对M1/M2栅极加载的差分信号VIN+/VIN-的共模电压在工作时也设置为VCM,由于复制偏置VB1的关系,M14的栅极偏压和M13的栅极偏压都等于VB1,M13的尾电流等于M14的尾电流I0,即I0=2*(VDD-VCM)/R,并且VX2=VX1=VCM;差分对M1/M2的电流设为I1,差分对M3/M4的电流设为I2,在I1和I2的分配关系中,I1在恒定的I0总电流中所占的比例由M3栅极的偏置电压VB2确定。Preferably, the common-mode voltage of the differential signal V IN+ /V IN- loaded on the gate of the differential pair M 1 /M 2 is also set to V CM during operation. Due to the relationship of the replica bias V B1 , the gate of M 14 Both the polar bias voltage and the gate bias voltage of M 13 are equal to V B1 , the tail current of M 13 is equal to the tail current I 0 of M 14 , that is, I 0 =2*(V DD -V CM )/R, and V X2 = V X1 = V CM ; the current of the differential pair M 1 /M 2 is set to I 1 , the current of the differential pair M 3 /M 4 is set to I 2 , in the distribution relationship between I 1 and I 2 , I 1 is at a constant The proportion of I 0 in the total current is determined by the bias voltage V B2 of the gate of M 3 .

优选的,所述指数比例电流产生电路形成的负反馈回路,使得VX3=VX2=VCM,Q2支路的电流IB2等于放大器核心电路中M1支路的电流,即IB2=I0/2=(VDD-VCM)/R,这是一个恒定可控的值;同时Q2基极上加载的电压VR是一个参考电压,Q1基极上加载的电压是一个线性控制电压VCPreferably, the negative feedback loop formed by the exponential proportional current generation circuit makes V X3 =V X2 =V CM , and the current I B2 of the Q 2 branch is equal to the current of the M 1 branch in the amplifier core circuit, that is, I B2 = I 0 /2=(V DD -V CM )/R, which is a constant and controllable value; at the same time, the voltage VR loaded on the base of Q 2 is a reference voltage, and the voltage loaded on the base of Q 1 is a Linear control voltage V C .

优选的,Q1和Q2两个支路的电流IB1和IB2有如下关系式成立:Preferably, the currents I B1 and I B2 of the two branches of Q 1 and Q 2 have the following relationship established:

公式(1)中VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度,也就是说IB1和IB2呈指数关系,或者说IB1和I0呈指数关系;IB1这个指数电流在Q1支路的电阻R上产生了一个电压VY1,该电压连接到指数比例电流偏置电路的运算放大器OP3的正输入端上,通过负反馈产生偏置电压VB2In the formula (1), V T =kT/q, k is Boltzmann's constant, q is the electron charge, T is the absolute temperature, that is to say, I B1 and I B2 are exponentially related, or I B1 and I 0 are in the form of Exponential relationship; I B1 This exponential current produces a voltage V Y1 on the resistor R of the Q 1 branch, which is connected to the positive input of the operational amplifier OP3 of the exponential proportional current bias circuit, and is biased by negative feedback Voltage V B2 .

优选的,所述指数比例电流偏置电路构成负反馈回路,使得电压VY2和VY1相等,M9/M10支路上流过电阻R的电流I1/2等于IB1Preferably, the exponential proportional current bias circuit forms a negative feedback loop, so that the voltages V Y2 and V Y1 are equal, and the current I 1 /2 flowing through the resistor R on the M 9 /M 10 branch is equal to I B1 :

因此,I1和I0呈指数关系,其中I0恒定可控。Therefore, I 1 and I 0 are exponentially related, where I 0 is constant and controllable.

优选的,连续可调分贝线性可变增益电路结构的增益表达式为:Preferably, the gain expression of the continuously adjustable decibel linear variable gain circuit structure is:

其中Cox是晶体管栅氧化层单位面积电容,是M1晶体管的宽长比,μn是电子的迁移率,R是负载电阻,VDD为电源电压,VCM为外加共模电压,VR为控制参考电压,VC为线性变化的控制电压,VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度,连续可调分贝线性可变增益电路结构的增益随着控制电压VC线性变化而呈分贝线性变化。Where C ox is the capacitance per unit area of the gate oxide layer of the transistor, is the width-to-length ratio of the M 1 transistor, μ n is the mobility of electrons, R is the load resistance, V DD is the power supply voltage, V CM is the external common-mode voltage, VR is the control reference voltage, and V C is the control of linear change Voltage, V T =kT/q, k is Boltzmann's constant, q is electron quantity, T is absolute temperature, continuously adjustable in decibels The gain of the linear variable gain circuit structure is in decibels as the control voltage V C changes linearly linear change.

本发明的优点:Advantages of the present invention:

本发明提出的连续可调的精确分贝线性可变增益放大结构,通过三组负反馈结构,两组偏置复制结构和一个电流分流结构差分对的巧妙系统性设计,在一个电流舵结构的差分放大晶体管对中,在保证总电流不变即输出共模电压不变的情况下,简单有效且精确的实现了一个随着外加控制电压线性变化而呈指数变化的晶体管沟道电流,该电流决定了该晶体管的跨导也随着控制电压线性变化而呈指数变化,进而实现了一个满足分贝线性增益控制的连续可调可变增益放大器结构。The continuously adjustable and accurate decibel linear variable gain amplification structure proposed by the present invention, through the ingenious systematic design of three sets of negative feedback structures, two sets of bias replication structures and a current shunt structure differential pair, in the differential pair of a current steering structure In the middle of the amplifying transistor pair, under the condition that the total current remains unchanged, that is, the output common-mode voltage remains unchanged, a simple, effective and accurate realization of a transistor channel current that changes exponentially with the linear change of the applied control voltage is determined by the current. The transconductance of the transistor also changes exponentially with the linear change of the control voltage, thereby realizing a continuously adjustable variable gain amplifier structure satisfying decibel linear gain control.

附图说明Description of drawings

下面结合附图及实施例对本发明作进一步描述:The present invention will be further described below in conjunction with accompanying drawing and embodiment:

图1为本发明的连续可调分贝线性可变增益电路结构的原理图;Fig. 1 is the schematic diagram of the continuously adjustable decibel linear variable gain circuit structure of the present invention;

图2表1参数实现的分贝线性可变增益电路的增益与控制电压的关系。The relationship between the gain and the control voltage of the decibel linear variable gain circuit realized by the parameters in Table 1 in Fig. 2.

具体实施方式Detailed ways

如图1所示,本发明包括四个部分,左上角电路模块1放大电路核心部分、右上角电路模块2共模输出偏置电路、左下角电路模块3指数比例电流产生电路和右下角电路模块4指数比例电流偏置电路。下面将依据这四部分对整个发明作详细介绍。As shown in Figure 1, the present invention comprises four parts, upper left corner circuit module 1 amplifying circuit core part, right upper corner circuit module 2 common mode output bias circuit, left lower corner circuit module 3 exponential proportional current generation circuit and right lower corner circuit module 4 exponentially proportional current bias circuit. The whole invention will be described in detail below based on these four parts.

整个电路的输入端为VIN+/VIN-,输出为VOUT+/VOUT-,外加共模电压为VCM,外加参考电压VR,外加线性增益控制电压VC。放大器的增益即输出信号和输入信号的比值随着控制电压VC的线性变化而呈分贝线性变化(指数变化)。The input terminal of the whole circuit is V IN+ /V IN- , the output is V OUT+ /V OUT- , the external common mode voltage is V CM , the reference voltage V R is external, and the linear gain control voltage V C is external. The gain of the amplifier, that is, the ratio of the output signal to the input signal, changes linearly in decibels (exponential change) with the linear change of the control voltage V C .

放大器核心电路为传统的差分对电流舵结构,如图1的左上角所示,由两对差分对M1/M2,M3/M4,一对差分负载电阻R1/R2(阻值均为R),以及尾电流偏置晶体管M13组成,输入差分信号为VIN+/VIN-,输出差分信号为VOUT+/VOUT-,设尾电流晶体管M13中的偏置电流为I0,输出差分信号VOUT+/VOUT-的共模电压由电源电压VDD减去电阻R上的电压降1/2*I0*R,而放大器的增益为AV=gm1*R,其中gm1是晶体管M1的跨导,要使得放大器的增益随着VC的线性变化而表现出分贝线性变化(指数变化),就需要使得晶体管M1的跨导呈指数变化,或者说使得晶体管M1的沟道电流I1呈指数变化。在本设计中,我们通过复制偏置技术,使得M13的尾电流I0保持恒定,同时通过巧妙的指数电流复制技术,使得M1的沟道电流I1随着控制电压VC的线性变化而呈现出指数变化。本发明中左上角放大器核心电路的电路结构尽管表面上看是传统的电流舵差分对结构,但其发明核心是加载在M13栅极的电压VB1,和加载在M3/M4栅极的电压VB2,这两个电压分别由本发明图1中的第二部分共模输出偏置电路和第三、第四部分指数比例电流产生和偏置电路生成,通过VB1和VB2的联合作用,一方面使得放大器的输出共模电压VX2等于外加的共模偏置电压VCM,这意味着流过放大器负载电阻的电流I0恒定可控,另一方面使得流过M1的沟道电流I1与总电流I0呈指数关系,从而达到增益呈分贝线性变化的设计目的。The core circuit of the amplifier is a traditional differential pair current steering structure, as shown in the upper left corner of Figure 1, which consists of two pairs of differential pairs M 1 /M 2 , M 3 /M 4 , and a pair of differential load resistors R 1 /R 2 ( The value is R), and the tail current bias transistor M 13 is composed, the input differential signal is V IN+ /V IN- , the output differential signal is V OUT+ /V OUT- , and the bias current in the tail current transistor M 13 is I 0 , the common-mode voltage of the output differential signal V OUT+ /V OUT- is the power supply voltage V DD minus the voltage drop on the resistor R 1/2*I 0 *R, and the gain of the amplifier is A V =g m1 *R , where g m1 is the transconductance of transistor M1 , to make the gain of the amplifier show a linear change in decibels (exponential change) with the linear change of V C , it is necessary to make the transconductance of transistor M1 change exponentially, or The channel current I1 of the transistor M1 changes exponentially. In this design, we keep the tail current I 0 of M 13 constant by replicating the bias technique, and at the same time make the channel current I 1 of M 1 change linearly with the control voltage V C through the ingenious exponential current replication technique showed an exponential change. Although the circuit structure of the amplifier core circuit in the upper left corner of the present invention is a traditional current steering differential pair structure on the surface, the core of the invention is the voltage V B1 loaded on the M 13 gate, and the voltage V B1 loaded on the M 3 /M 4 gate The voltage V B2 of the present invention is generated by the second part of the common mode output bias circuit and the third and fourth part of the exponential proportional current generation and bias circuit in Fig. 1 of the present invention respectively, through the combination of V B1 and V B2 On the one hand, it makes the output common-mode voltage V X2 of the amplifier equal to the external common-mode bias voltage V CM , which means that the current I 0 flowing through the load resistance of the amplifier is constant and controllable; on the other hand, it makes the channel flowing through M 1 The channel current I 1 has an exponential relationship with the total current I 0 , so as to achieve the design purpose that the gain changes linearly in decibels.

实现M13尾电流I0恒定的方法如下所述,如图1右上角的共模输出偏置电路所示,该部分电路中的两对差分对M5/M6,M7/M8,差分负载电阻R3/R4,以及尾电流偏置晶体管M14和图1中的左上角电路1放大器核心电路M1/M2,M3/M4,差分负载电阻R1/R2,尾电流偏置晶体管M13完全一致,图1右上角电路2中的差分对M5/M6栅极接外接共模电压VCM,M7/M8栅极上加的电压来自于图1右下角电路4所产生的偏置电压VB2,图1右上角电路2中的一对差分负载电阻的输出端短接在一起并连接到运算放大器OP1的正输入端,OP1的负输入端接共模参考电压VCM,OP1的输出端接M14的栅极,形成负反馈回路,该负反馈回路迫使图1右上角电路2中的负载电阻R3/R4的输出端电压VX1等于VCM,这意味着如下公式成立VDD-1/2*I0*R=VCM,I0可以由此公式决定即I0=2*(VDD-VCM)/R。图1左上角电路1中的差分输入对M1/M2栅极加载的差分信号VIN+/VIN-的共模电压在工作时也设置为VCM,由于复制偏置VB1的关系,即图1中电路1和电路2主体结构相同,M14的栅极偏压和M13的栅极偏压都等于VB1,图1左上角电路1中的电流分配关系和右上角的电路2完全一致,即M13的尾电流等于M14的尾电流I0即I0=2*(VDD-VCM)/R,并且VX2=VX1=VCM,而I1和I2的分配关系或者说I1在恒定的I0总电流中所占的比例由M3栅极的偏置电压VB2确定,图1中左下角电路3和右下角的电路4合作产生偏置电压VB2,使得I1的值作为I0的一部分并呈指数变化,具体发明实现方法描述如下。The method to realize the constant tail current I 0 of M 13 is as follows, as shown in the common mode output bias circuit in the upper right corner of Fig. 1, two pairs of differential pairs M 5 /M 6 , M 7 /M 8 in this part of the circuit, Differential Load Resistor R 3 /R 4 , and Tail Current Bias Transistor M 14 and Top Left Circuit in Figure 1 Amplifier Core Circuit M 1 /M 2 , M 3 /M 4 , Differential Load Resistor R 1 /R 2 , The tail current bias transistor M 13 is exactly the same, the gate of the differential pair M 5 /M 6 in circuit 2 in the upper right corner of Figure 1 is connected to the external common mode voltage V CM , and the voltage applied to the gate of M 7 /M 8 comes from Figure 1 The bias voltage V B2 generated by circuit 4 in the lower right corner, the output terminals of a pair of differential load resistors in circuit 2 in the upper right corner of Figure 1 are shorted together and connected to the positive input terminal of the operational amplifier OP1, and the negative input terminal of OP1 is connected to The common-mode reference voltage V CM , the output terminal of OP1 is connected to the gate of M 14 , forming a negative feedback loop, which forces the output terminal voltage V X1 of the load resistor R 3 /R 4 in the circuit 2 in the upper right corner of Figure 1 to be equal to V CM , which means that the following formula holds: V DD −1/2*I 0 *R=V CM , and I 0 can be determined by this formula, that is, I 0 =2*(V DD −V CM )/R. The common-mode voltage of the differential signal V IN+ /V IN- loaded on the gate of the differential input pair M 1 /M 2 in circuit 1 in the upper left corner of Figure 1 is also set to V CM during operation, due to the relationship of the replica bias V B1 , That is, the main structure of circuit 1 and circuit 2 in Fig. 1 is the same, the gate bias voltage of M 14 and the gate bias voltage of M 13 are both equal to V B1 , the current distribution relationship in circuit 1 in the upper left corner of Fig. 1 and the circuit 2 in the upper right corner It is exactly the same, that is, the tail current of M 13 is equal to the tail current I 0 of M 14 , that is, I 0 =2*(V DD -V CM )/R, and V X2 =V X1 =V CM , while I 1 and I 2 The distribution relationship or the proportion of I1 in the constant I0 total current is determined by the bias voltage V B2 of the gate of M3 . In Figure 1, the circuit 3 in the lower left corner and the circuit 4 in the lower right corner cooperate to generate the bias voltage V B2 , so that the value of I 1 is taken as a part of I 0 and changes exponentially, and the specific implementation method of the invention is described as follows.

图1左下角电路3由一对差分结构三极管Q1和Q2,一对差分电阻R5/R6,尾电流晶体管M16及运算放大器OP2组成,运算放大器OP2的正输入端接Q2支路负载电阻R5/R6的输出端VX3,负输入端接外加共模电压VCM,OP2的输出端接的M16栅极,和M16及Q2形成负反馈回路,使得如下关系成立VX3=VX2=VCM。这意味着Q2支路的电流IB2等于图1左上角电路1中M1支路的电流即IB2=I0/2=(VDD-VCM)/R这是一个恒定可控的值。同时Q2基极上加载的电压VR是一个参考电压,Q1基极上加载的电压是一个线性控制电压VC,由于三极管的特性,Q1和Q2两个支路的电流IB1和IB2有如下关系式成立:Circuit 3 in the lower left corner of Figure 1 is composed of a pair of differential transistors Q 1 and Q 2 , a pair of differential resistors R 5 /R 6 , tail current transistor M 16 and operational amplifier OP2. The positive input terminal of operational amplifier OP2 is connected to Q 2 The output terminal V X3 of the road load resistor R 5 /R 6 , the negative input terminal is connected to the external common mode voltage VCM, the output terminal of OP2 is connected to the gate of M 16 , and forms a negative feedback loop with M 16 and Q 2 , so that the following relationship is established V X3 =V X2 =V CM . This means that the current I B2 of the Q 2 branch is equal to the current of the M 1 branch in the circuit 1 in the upper left corner of Figure 1, that is, I B2 =I 0 /2=(V DD -V CM )/R, which is a constant and controllable value. At the same time, the voltage V R loaded on the base of Q 2 is a reference voltage, and the voltage loaded on the base of Q 1 is a linear control voltage V C . Due to the characteristics of the triode, the current I B1 of the two branches of Q 1 and Q 2 and I B2 have the following relationship established:

公式(1)中VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度,也就是说IB1和IB2呈指数关系,或者说IB1和I0呈指数关系。IB1这个指数电流在Q1支路的电阻R5/R6上产生了一个电压VY1,该电压连接到图1右下角电路4的运算放大器OP3的正输入端上,通过负反馈产生偏置电压VB2,具体设计细节如下。图1右下角电路4由差分对M9/M10,M11/M12和尾电流晶体管M15,一对差分电阻R7/R8,以及运算放大器OP3组成,其晶体管和负载电阻元器件的值与图1右上角电路2中的元器件完全一致,但连接方式略有不同,在右上角电路2中,差分对M5/M6,M7/M8并联连接,两个支路的电流汇总到差分电阻上。而在右下角电路4中,差分对M9/M10连接差分电阻对R7/R8,M11/M12直接连接到电源电压,这样做的目的是形成一种电流分流结构,将M9/M10,M11/M12两个支路的电流分开,图1右下角电路4中尾电流晶体管M15栅极加载由图1右上角电路2中产生的偏置电压VB1,一对差分电阻R7/R8的输出端短接并连接到运算放大器OP3的负输入端,OP3的正输入端接图1左下角电路3产生的电压VY1,OP3的输出端产生关键的偏置电压VB2并加载到差分对M11/M12的栅极,构成负反馈回路,使得电压VY2和VY1相等,这就意味着M9/M10支路上流过电阻R的电流I1/2等于IB1,也就是说如下等式成立:In the formula (1), V T =kT/q, k is Boltzmann's constant, q is the electron charge, T is the absolute temperature, that is to say, I B1 and I B2 are exponentially related, or I B1 and I 0 are in the form of Exponential relationship. The exponential current of I B1 produces a voltage V Y1 on the resistor R5 / R6 of the Q1 branch, which is connected to the positive input of the operational amplifier OP3 of the circuit 4 in the lower right corner of Figure 1, and is biased by negative feedback. Set the voltage V B2 , the specific design details are as follows. Circuit 4 in the lower right corner of Figure 1 is composed of differential pairs M 9 /M 10 , M 11 /M 12 and tail current transistor M 15 , a pair of differential resistors R 7 /R 8 , and an operational amplifier OP3. Its transistors and load resistor components The value of is exactly the same as the components in circuit 2 in the upper right corner of Figure 1, but the connection method is slightly different. In circuit 2 in the upper right corner, the differential pair M 5 /M 6 and M 7 /M 8 are connected in parallel, and the two branches The current summed to the differential resistor. In circuit 4 in the lower right corner, the differential pair M 9 /M 10 is connected to the differential resistor pair R 7 /R 8 , and M 11 /M 12 is directly connected to the power supply voltage. The purpose of this is to form a current shunt structure, and M 9 /M 10 , the currents of the two branches of M 11 /M 12 are separated, and the gate of the tail current transistor M 15 in the circuit 4 in the lower right corner of Figure 1 is loaded with the bias voltage V B1 generated by the circuit 2 in the upper right corner of Figure 1, a pair The output terminal of the differential resistor R 7 /R 8 is shorted and connected to the negative input terminal of the operational amplifier OP3, the positive input terminal of OP3 is connected to the voltage V Y1 generated by circuit 3 in the lower left corner of Figure 1, and the output terminal of OP3 produces the key bias The voltage V B2 is loaded to the gate of the differential pair M 11 /M 12 to form a negative feedback loop, so that the voltage V Y2 and V Y1 are equal, which means that the current I 1 flowing through the resistor R on the M 9 /M 10 branch /2 is equal to I B1 , that is to say, the following equation holds:

因此,I1和I0呈指数关系且I0是一个恒定可控的值,由于复制偏置的原因,图1左上角电路1中的M1/M2支路电流I1和总的尾电流I0与电路2电路3中的相应的电流完全一致,即主放大器中的I1和I0也满足公式(2)的关系,且I0=2*(VDD-VCM)/R,是一个可以通过控制外加共模电压VCM来控制的电流。由于I0在VCM固定的情况下是一个定值,那么I1就是一个随着控制电压VC-VR线性变化而呈指数变化的值,由于M1晶体管的跨导gm1正比于电流I1的二分之一次方,也是一个随着控制电压VC-VR线性变化而呈指数变化的值,因此图1中放大器核心电路的增益也随着控制电压VC-VR线性变化而呈指数变化,也就是说这是一个满足分贝线性控制关系的可变增益放大结构。该放大器的增益表达式为:Therefore, I 1 and I 0 have an exponential relationship and I 0 is a constant and controllable value. Due to the replication bias, the M 1 /M 2 branch current I 1 and the total tail of the circuit 1 in the upper left corner of Fig. 1 The current I 0 is exactly the same as the corresponding current in circuit 2 and circuit 3, that is, I 1 and I 0 in the main amplifier also satisfy the relationship of formula (2), and I 0 =2*(V DD -V CM )/R , is a current that can be controlled by controlling the external common-mode voltage V CM . Since I 0 is a fixed value when V CM is fixed, then I 1 is a value that changes exponentially with the linear change of control voltage V C -VR , because the transconductance g m1 of M 1 transistor is proportional to the current The half power of I 1 is also a value that changes exponentially with the linear change of the control voltage V C -VR , so the gain of the amplifier core circuit in Figure 1 is also linear with the control voltage V C -VR It changes exponentially, that is to say, it is a variable gain amplification structure that satisfies the decibel linear control relationship. The gain expression for this amplifier is:

其中Cox是晶体管栅氧化层单位面积电容,是M1晶体管的宽长比,μn是电子的迁移率,R是负载电阻,VDD为电源电压,VCM为外加共模电压,VR为控制参考电压,VC为线性变化的控制电压,VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度。由公式(3)可知该电路模块的增益随着控制电压VC线性变化而呈指数变化,或者说呈分贝线性变化。Where C ox is the capacitance per unit area of the gate oxide layer of the transistor, is the width-to-length ratio of the M 1 transistor, μ n is the mobility of electrons, R is the load resistance, V DD is the power supply voltage, V CM is the external common-mode voltage, VR is the control reference voltage, and V C is the control of linear change Voltage, V T =kT/q, k is Boltzmann's constant, q is electron charge, and T is absolute temperature. It can be seen from formula (3) that the gain of the circuit module changes exponentially, or in other words, changes linearly in decibels as the control voltage V C changes linearly.

下面给出一种基于本发明提出的基于复制偏置技术的新型分贝线性可变增益电路结构的具体实现,采用0.13um CMOS工艺,实例电路中各个关键晶体管的参数如表1所示。电路中的运算放大器属于常见的电路元件,故在实施例中不作专门说明。该电路工作在1.2V的电源电压下。对该电路采用表1所示的参数实现并进行仿真。仿真结果如图2所示,结果表明,在1.2V电源电压下,采用0.8V的共模电压VCM和0.8V的参考电压VR,控制电压VC从0.8V线性变化到0.9V,电路的增益从-8dB变化到10dB,且其分贝值的变化是线性的,即实现了精确的连续可调分贝线性增益控制。多个同样的放大单元级联,可以实现更宽的增益控制范围,如4个同样的本发明提出放大电路级联,可以实现-32dB到40dB的增益控制。A specific implementation of a new decibel linear variable gain circuit structure based on replica bias technology proposed by the present invention is given below, using a 0.13um CMOS process. The parameters of each key transistor in the example circuit are shown in Table 1. The operational amplifier in the circuit is a common circuit element, so no special description is given in the embodiment. The circuit operates on a supply voltage of 1.2V. The circuit is implemented and simulated using the parameters shown in Table 1. The simulation results are shown in Figure 2. The results show that, under the power supply voltage of 1.2V, the common mode voltage V CM of 0.8V and the reference voltage VR of 0.8V are used, and the control voltage V C changes linearly from 0.8V to 0.9V. The circuit The gain changes from -8dB to 10dB, and the change of its decibel value is linear, which realizes the precise continuous adjustable decibel linear gain control. Cascade connection of a plurality of identical amplifying units can realize a wider gain control range. For example, cascade connection of four identical amplifying circuits proposed by the present invention can realize gain control from -32dB to 40dB.

表1本发明提出的新型连续可调分贝线性可变增益电路结构参数表Table 1 The structure parameter table of the novel continuously adjustable decibel linear variable gain circuit proposed by the present invention

上述实施例只为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明主要技术方案的精神实质所做的修饰,都应涵盖在本发明的保护范围之内。The above-mentioned embodiments are only to illustrate the technical conception and characteristics of the present invention, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All modifications made according to the spirit of the main technical solutions of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1.一种连续可调分贝线性可变增益电路结构,其特征在于,包括:放大器核心电路、共模输出偏置电路、指数比例电流产生电路、指数比例电流偏置电路;1. A continuously adjustable decibel linear variable gain circuit structure is characterized in that it comprises: amplifier core circuit, common mode output bias circuit, exponential proportional current generation circuit, exponential proportional current bias circuit; 所述放大器核心电路为差分对电流舵结构,包括场效应管M1、M2组成的差分对M1/M2、场效应管M3、M4组成的差分对M3/M4,一对差分负载电阻R1/R2,以及尾电流偏置晶体管M13,输入差分信号为VIN+/VIN-,分别连接差分对M1/M2的栅极,输出差分信号为VOUT+/VOUT-,VOUT+连接M2/M4的漏极,VOUT-连接M1/M3的漏极,差分对M1/M2的漏极分别通过电阻R1/R2连接高电平VDD,两对差分对M1/M2、M3/M4的源极分别连接到晶体管M13的漏极,M13的源极接地;The core circuit of the amplifier is a differential pair current steering structure, including a differential pair M 1 /M 2 composed of field effect transistors M1 and M2 , a differential pair M 3 /M 4 composed of field effect transistors M3 and M4, and a pair of differential load resistors R 1 /R 2 , and the tail current bias transistor M 13 , the input differential signal is V IN+ /V IN- , connected to the gates of the differential pair M 1 /M 2 respectively, and the output differential signal is V OUT+ /V OUT- , V OUT+ is connected to the drain of M 2 /M 4 , V OUT- is connected to the drain of M 1 /M 3 , and the drain of the differential pair M 1 /M 2 is respectively connected to the high-level VDD through the resistor R 1 /R 2 . The sources of the differential pairs M 1 /M 2 and M 3 /M 4 are respectively connected to the drain of the transistor M 13 , and the source of M 13 is grounded; 所述共模输出偏置电路生成电压VB1加载在M13栅极;The common-mode output bias circuit generates a voltage V B1 and loads it on the gate of M13 ; 所述指数比例电流产生电路和指数比例电流偏置电路依次连接,生成电压VB2加载在M3/M4栅极;通过电压VB1和电压VB2的联合作用,使得尾电流晶体管M13中的偏置电流为I0恒定可控,同时流过M1的沟道电流I1与I0呈指数关系,从而使增益呈分贝线性变化。The exponential proportional current generation circuit and the exponential proportional current bias circuit are sequentially connected to generate a voltage VB2 to be loaded on the gate of M3 / M4 ; through the joint action of the voltage VB1 and the voltage VB2 , the tail current transistor M13 The bias current I 0 is constant and controllable, and the channel current I 1 flowing through M 1 has an exponential relationship with I 0 , so that the gain changes linearly in decibels. 2.根据权利要求1所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述共模输出偏置电路,包括场效应管M5、M6组成的差分对M5/M6,场效应管M7、M8组成的差分对M7/M8,一对差分负载电阻R3/R4,以及尾电流偏置晶体管M14;差分对M5/M6栅极接外接共模电压VCM,M7/M8栅极上加的电压来自于指数比例电流偏置电路所产生的偏置电压VB2,差分负载电阻R3/R4的输出端短接在一起并连接到运算放大器OP1的正输入端,OP1的负输入端接共模参考电压VCM,OP1的输出端电压VB1接M14的栅极,形成负反馈回路。2. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 1, characterized in that the common mode output bias circuit comprises a differential pair M 5 /M 6 composed of field effect transistors M5 and M6 , the differential pair M 7 /M 8 composed of field effect transistors M7 and M8, a pair of differential load resistors R 3 /R 4 , and the tail current bias transistor M 14 ; the gate of the differential pair M 5 /M 6 is connected to an external common mode The voltage V CM , the voltage added to the gate of M 7 /M 8 comes from the bias voltage V B2 generated by the exponential proportional current bias circuit, and the output ends of the differential load resistors R 3 /R 4 are shorted together and connected to The positive input terminal of the operational amplifier OP1, the negative input terminal of OP1 are connected to the common-mode reference voltage V CM , the output terminal voltage VB1 of OP1 is connected to the gate of M 14 , forming a negative feedback loop. 3.根据权利要求2所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述共模输出偏置电路与放大器核心电路形成的负反馈回路,迫使共模输出偏置电路中的负载电阻R3/R4的输出端电压VX1等于VCM,则VDD-1/2*I0*R=VCM,I0由此公式决定,即I0=2*(VDD-VCM)/R。3. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 2, characterized in that, the negative feedback loop formed by the common-mode output bias circuit and the amplifier core circuit forces the common-mode output bias circuit to The output terminal voltage V X1 of the load resistor R 3 /R 4 is equal to V CM , then V DD -1/2*I 0 *R=V CM , and I 0 is determined by this formula, that is, I 0 =2*(V DD -V CM )/R. 4.根据权利要求3所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述指数比例电流产生电路包括三极管Q1、Q2组成的差分结构三极管Q1/Q2,一对差分电阻R5/R6,尾电流晶体管M16及运算放大器OP2;运算放大器OP2的正输入端接Q2支路负载电阻R的输出端VX3,负输入端接外加共模电压VCM,OP2的输出端接的M16栅极,和M16及Q2形成负反馈回路。4. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 3, characterized in that, the exponential proportional current generating circuit comprises a differential structure triode Q 1 /Q 2 composed of triodes Q 1 and Q 2 , A pair of differential resistors R 5 /R 6 , tail current transistor M 16 and operational amplifier OP2; the positive input terminal of the operational amplifier OP2 is connected to the output terminal V X3 of the load resistor R of the Q 2 branch, and the negative input terminal is connected to the external common mode voltage VCM , the output terminal of OP2 is connected to the gate of M 16 , forming a negative feedback loop with M 16 and Q 2 . 5.根据权利要求4所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述指数比例电流偏置电路包括场效应管M9、M10组成的差分对M9/M10,场效应管M11、M12组成的差分对M11/M12,一对差分电阻对R7/R8,尾电流晶体管M15,以及运算放大器OP3,差分对M9/M10连接差分电阻对R7/R8,M11/M12直接连接到电源电压;尾电流晶体管M15栅极加载由共模输出偏置电路中产生的偏置电压VB1,电阻对R7/R8的输出端短接并连接到运算放大器OP3的负输入端,OP3的正输入端接指数比例电流产生电路产生的电压VY1,OP3的输出端产生偏置电压VB2,并加载到差分对M11/M12的栅极,构成负反馈回路。5. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 4, wherein the exponential proportional current bias circuit comprises a differential pair M 9 /M 10 composed of field effect transistors M9 and M10, The differential pair M 11 /M 12 composed of field effect transistors M11 and M12, a pair of differential resistor pairs R 7 /R 8 , the tail current transistor M 15 , and the operational amplifier OP3, and the differential pair M 9 /M 10 are connected to the differential resistor pair R 7 /R 8 , M 11 /M 12 are directly connected to the supply voltage; the gate of the tail current transistor M 15 is loaded with the bias voltage V B1 generated in the common-mode output bias circuit, and the output terminal of the resistor pair R 7 /R 8 Short circuit and connect to the negative input terminal of the operational amplifier OP3, the positive input terminal of OP3 is connected to the voltage V Y1 generated by the exponential proportional current generation circuit, the output terminal of OP3 generates the bias voltage V B2 , and loads it to the differential pair M 11 /M The gate of 12 constitutes a negative feedback loop. 6.根据权利要求3所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述差分对M1/M2栅极加载的差分信号VIN+/VIN-的共模电压在工作时也设置为VCM,由于复制偏置VB1的关系,M14的栅极偏压和M13的栅极偏压都等于VB1,M13的尾电流等于M14的尾电流I0,即I0=2*(VDD-VCM)/R,并且VX2=VX1=VCM;差分对M1/M2的电流设为I1,差分对M3/M4的电流设为I2,在I1和I2的分配关系中,I1在恒定的I0总电流中所占的比例由M3栅极的偏置电压VB2确定。6. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 3, wherein the common-mode voltage of the differential signal V IN+ /V IN- loaded on the gate of the differential pair M 1 /M 2 It is also set to V CM during operation. Due to the relationship of replica bias V B1 , the gate bias voltage of M 14 and the gate bias voltage of M 13 are both equal to V B1 , and the tail current of M 13 is equal to the tail current I of M 14 0 , that is, I 0 =2*(V DD -V CM )/R, and V X2 =V X1 =V CM ; the current of the differential pair M 1 /M 2 is set to I 1 , and the current of the differential pair M 3 /M 4 The current is set as I 2 , and in the distribution relationship between I 1 and I 2 , the proportion of I 1 in the constant I 0 total current is determined by the bias voltage V B2 of the gate of M 3 . 7.根据权利要求5所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述指数比例电流产生电路形成的负反馈回路,使得VX3=VX2=VCM,Q2支路的电流IB2等于放大器核心电路中M1支路的电流,即IB2=I0/2=(VDD-VCM)/R,这是一个恒定可控的值;同时Q2基极上加载的电压VR是一个参考电压,Q1基极上加载的电压是一个线性控制电压VC7. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 5, characterized in that, the negative feedback loop formed by the exponential proportional current generating circuit makes V X3 =V X2 =V CM , Q 2 The current I B2 of the branch is equal to the current of the M 1 branch in the core circuit of the amplifier, that is, I B2 =I 0 /2=(V DD -V CM )/R, which is a constant and controllable value; at the same time, the Q 2 base The voltage VR loaded on the pole is a reference voltage, and the voltage loaded on the base of Q 1 is a linear control voltage V C . 8.根据权利要求7所述的新型连续可调分贝线性可变增益电路结构,其特征在于,Q1和Q2两个支路的电流IB1和IB2有如下关系式成立:8. novel continuously adjustable decibel linear variable gain circuit structure according to claim 7, is characterized in that, the current I B1 and I B2 of Q 1 and Q 2 two branches have following relational expression to set up: 公式(1)中VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度,也就是说IB1和IB2呈指数关系,或者说IB1和I0呈指数关系;IB1这个指数电流在Q1支路的电阻R上产生了一个电压VY1,该电压连接到指数比例电流偏置电路的运算放大器OP3的正输入端上,通过负反馈产生偏置电压VB2In the formula (1), V T =kT/q, k is Boltzmann's constant, q is the electron charge, T is the absolute temperature, that is to say, I B1 and I B2 are exponentially related, or I B1 and I 0 are in the form of Exponential relationship; I B1 This exponential current produces a voltage V Y1 on the resistor R of the Q 1 branch, which is connected to the positive input of the operational amplifier OP3 of the exponential proportional current bias circuit, and is biased by negative feedback Voltage V B2 . 9.根据权利要求8所述的新型连续可调分贝线性可变增益电路结构,其特征在于,所述指数比例电流偏置电路构成负反馈回路,使得电压VY2和VY1相等,M9/M10支路上流过电阻R的电流I1/2等于IB19. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 8, characterized in that, the exponential proportional current bias circuit forms a negative feedback loop, so that the voltages V Y2 and V Y1 are equal, M 9 / The current I 1 /2 flowing through the resistor R on the branch M 10 is equal to I B1 : 因此,I1和I0呈指数关系,其中I0恒定可控。Therefore, I 1 and I 0 are exponentially related, where I 0 is constant and controllable. 10.根据权利要求9所述的新型连续可调分贝线性可变增益电路结构,其特征在于,连续可调分贝线性可变增益电路结构的增益表达式为:10. The novel continuously adjustable decibel linear variable gain circuit structure according to claim 9, wherein the gain expression of the continuously adjustable decibel linear variable gain circuit structure is: 其中Cox是晶体管栅氧化层单位面积电容,是M1晶体管的宽长比,μn是电子的迁移率,R是负载电阻,VDD为电源电压,VCM为外加共模电压,VR为控制参考电压,VC为线性变化的控制电压,VT=kT/q,k是玻尔兹曼常数,q是电子电量,T是绝对温度,连续可调分贝线性可变增益电路结构的增益随着控制电压VC线性变化而呈分贝线性变化。Where C ox is the capacitance per unit area of the gate oxide layer of the transistor, is the width-to-length ratio of the M 1 transistor, μ n is the mobility of electrons, R is the load resistance, V DD is the power supply voltage, V CM is the external common-mode voltage, VR is the control reference voltage, and V C is the control of linear change Voltage, V T =kT/q, k is Boltzmann's constant, q is electron quantity, T is absolute temperature, continuously adjustable in decibels The gain of the linear variable gain circuit structure is in decibels as the control voltage V C changes linearly linear change.
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