CN108594103B - Measurement structure and method of MOSFET overshoot voltage and undershoot voltage - Google Patents

Abstract

MOSFET overshoot/undershoot voltage measurement structures and methods, comprising: an N well and a P well having a PMOS and an NMOS, respectively; the first well region arranged in the N well is in contact connection with a first power supply voltage; the second well region arranged in the P well is in contact connection with a second power supply voltage; during the overshoot voltage test, one of the source end or the drain end of the PMOS is used as an input end for inputting the excitation current and is simultaneously used as an output end for recording the output voltage, and the source end or the drain end of the NMOS is connected with a second power supply voltage; during the down-rush voltage test, one of the source terminal or the drain terminal of the NMOS is used as an input terminal for inputting the excitation current and simultaneously as an output terminal for recording the output voltage, and the source terminal or the drain terminal of the PMOS is connected to the first power supply voltage. According to the invention, a PNPN structure formed by adjacent source/drain terminals and well contacts is used as a test structure, and a latch method is used for measuring the overshoot voltage and the undershoot voltage, so that the test structure is simplified, and the test efficiency is improved.

Description

Measurement structure and method of MOSFET overshoot voltage and undershoot voltage

technical field

The invention relates to a structure and method for measuring voltage parameters of MOSFET parasitic diodes, in particular to a structure and method for measuring overshoot voltage and undershoot voltage of MOSFET parasitic diodes.

Background technique

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are currently widely used in various integrated circuits, not only for digital logic devices, but also for memory devices, switch control devices, and the like. MOSFETs typically have high input impedance due to the presence of a gate insulating layer.

However, as device feature sizes continue to shrink, the thickness of the gate insulating layer between the metal gate and the channel region of the doped semiconductor, the thickness of the spacers on the sidewalls of the metal gate, and the shallow trenches between adjacent devices The depth of the trench isolation is also reduced accordingly. If the fluctuation of the input voltage, such as the overshoot voltage of the rising edge of the signal and the undershoot voltage of the falling edge exceeds a certain critical value, the local electric field will be too large and the insulating dielectric layer will be broken down. Causes a short circuit between conductors or semiconductors that should be insulated from each other. Even if the subsequent voltage returns to the rated range, the large voltage and high current caused by the breakdown short circuit will change the distribution of carriers in the semiconductor region and the distribution of stored charges in the insulating region, and the device will not be able to resume normal operation. Therefore, the effects of such overshoot and undershoot voltages are destructive.

For this reason, during the design and manufacturing process of advanced process nodes, especially during circuit design, it is necessary to determine the overshoot voltage (the difference between the voltage and V _dd when the device begins to show negative resistance) and the undershoot voltage that the MOSFET can withstand. (the difference from V _ss when the device begins to exhibit negative resistance) is clearly defined. However, the definitions of overshoot voltage and undershoot voltage are now at the circuit level, and there is no definition of overshoot voltage and undershoot voltage at the device level. Therefore, how to measure the above-mentioned voltage parameters of MOSFET with low cost and high efficiency is of great significance to improve the success rate of circuit design.

SUMMARY OF THE INVENTION

Therefore, the object of the present invention is to provide a simple and efficient MOSFET overshoot voltage/undershoot voltage measurement structure and method.

To this end, the present invention provides a MOSFET overshoot voltage/undershoot voltage measurement structure, characterized in that it includes:

Adjacent N-well and P-well in the substrate, with PMOS and NMOS, respectively;

the contact of the first well region arranged in the N well is used to connect the first power supply voltage;

contacting a second well region disposed in the P well for connecting to a second power supply voltage;

During the overshoot voltage test, the source terminal or the drain terminal of the PMOS is used as the input terminal for inputting the excitation current and simultaneously as the output terminal for recording the output voltage, and the source terminal or the drain terminal of the NMOS is connected to the second power supply voltage;

During the undershoot voltage test, the source terminal or the drain terminal of the NMOS is used as the input terminal for inputting the excitation current and simultaneously as the output terminal for recording the output voltage, and the source terminal or the drain terminal of the PMOS is connected to the first supply voltage.

Wherein, the first well region contact is adjacent to the source terminal or the drain terminal of the PMOS.

Wherein, the contact of the second well region is adjacent to the source terminal or the drain terminal of the NMOS.

Wherein, the first well region contact includes an N-type doped region, and the second well region contact includes a P-type doped region.

The present invention further provides a method for measuring using the MOSFET overshoot voltage/undershoot voltage measurement structure described in any one of the above, characterized in that, comprising:

contacting the first well region with a first power supply voltage, and contacting the second well region with a second power supply voltage, inputting an input excitation current into the input terminal, and judging whether a latch occurs;

If so, record the difference between the output voltage and the first or second supply voltage as an overshoot voltage or an undershoot voltage, respectively;

If not, continue to adjust the input excitation current.

Wherein, the step of adjusting the input excitation current further includes: if it is determined that the latch-up does not occur, increasing the input excitation current until it is determined that the latch-up occurs and recording the output voltage.

Wherein, the input excitation current includes 1000-20,000 peak waveforms per second; optionally, the waveform width is 10-300ns.

Based on the idea of PNPN structure, this application adopts the parasitic diode P-well (PWELL) and source/drain (N plus) of N-type MOSFET, and the parasitic diode N-well (NWELL) and source/drain (P plus) to form a PNPN structure for testing, and then use the conventional latchup method to test to obtain the overshoot voltage of the parasitic diode of the N-type MOSFET and the undershoot voltage of the parasitic diode of the P-type MOSFET.

According to the MOSFET overshoot voltage/undershoot voltage measurement structure and method of the present invention, the PNPN structure formed by the source-drain terminals and well contacts of adjacent NMOS and PMOS is used as the test structure, and the overshoot voltage and the undershoot voltage are measured by the latch method. The impulse voltage simplifies the test structure and improves the test efficiency.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims and specific features are defined in the dependent claims.

Description of drawings

The technical solutions of the present invention are described in detail below with reference to the accompanying drawings, wherein:

1 shows a schematic cross-sectional view of a test structure according to an embodiment of the present invention;

FIG. 2 shows a schematic layout of a test structure according to an embodiment of the present invention;

FIG. 3 shows an equivalent circuit diagram of a test structure according to an embodiment of the present invention; and

FIG. 4 shows the test results of overshoot voltage (right side) and undershoot voltage (left side) according to an embodiment of the present invention, respectively.

Detailed ways

The features and technical effects of the technical solutions of the present invention are described in detail below with reference to the accompanying drawings and schematic embodiments, and a test structure and method for measuring MOSFET overshoot voltage/undershoot voltage with low cost and high efficiency are disclosed. It should be noted that similar reference numerals denote similar structures, and the terms "first", "second", "upper", "lower", etc. used in this application may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures unless specifically stated.

As shown in FIG. 1 , it is a cross-sectional view of a test structure according to an embodiment of the present invention. In VLSI, NMOS and PMOS are formed in P-well and N-well, respectively, on the wafer substrate (if the entire substrate has n-doping, the N-well may not be needed). No matter how the circuit layout is designed, there is always a certain NMOS in the P well adjacent to a certain PMOS in the N well, so that the well region and the substrate form a pn junction, and the source and drain regions of the MOSFET and the well region also have a pn junction. , so there is a pnpn parasitic structure from the power supply Vdd to the ground potential GND, that is, a parasitic thyristor structure, which is actually equivalent to two bipolar junction transistors (BJTs) of parasitic PNP and NPN.

When the collector of one BJT (such as the source terminal of NMOS) is suddenly increased to a certain value by external interference, it will be fed back to the other BJT (such as the drain terminal of PMOS), and when the PNPN structure formed by the two parasitic BJTs When the loop gain is greater than 1, a low-impedance path is formed, thus resulting in a latch-up effect. The equivalent circuit diagram is shown in Figure 3, the first power supply voltage VDD is connected to the base of the pnp parasitic BJT and the collector of the npn parasitic BJT through the well resistor Rwell, the emitter of the pnp parasitic BJT is connected to VDD, and the collector is connected through the substrate resistor Rsub Ground, the emitter of the npn parasitic BJT is grounded, and the low impedance path is shown by the dashed arrow in the figure.

Therefore, the inventor uses adjacent NMOS and PMOS to form a layout structure as shown in FIG. 2 (which is the layout structure corresponding to the top view of FIG. 1 , the pins from top to bottom are 1, 2, 3, and 4 in sequence, according to the sectional view in FIG. 1 ) The PNPN structure of the layout design shown in order from right to left is used as a test structure for overshoot voltage/undershoot voltage. Among them, pin 4 is used as an n-well contact connected to the first power supply voltage (V _dd ), that is, the first well region contact, and is distributed around pin 3, that is, around the source or drain of the PMOS device in the N-well, preferably adjacent to it. In a preferred embodiment of the present invention, the N+ contacts in the N well corresponding to the pin 4 are distributed in a ring shape (a continuous ring, or a surrounding structure composed of discrete sub-well regions) to improve the uniformity of current distribution. Similarly, the contact of the second well region connected to Vss (potential zero) or GND corresponding to pin 1 (distributed around pin 2, that is, around the source or drain of the NMOS device in the p-well) can also be annular. Distribution (continuous ring, or surrounding structure of discrete sub-well regions).

Overshoot voltage test procedure: Terminal 1 is the P-well contact (ie, the second well region contact) connected to the second power supply voltage (Vss or GND), and terminal 2 is connected to the second power supply voltage, that is, Vss (potential zero) or One of the source or drain contacts of the NMOS in the p-well of GND (the other is floating), the terminal 3 is the source or drain contact of the PMOS in the n-well, and the terminal 4 is connected to the first power supply voltage (Vdd) The N-well contact (ie, the first well region contact). A current excitation signal is input to terminal 3, and the voltage of terminal 3 is recorded. The voltage/current point at which the device begins to exhibit negative resistance is recorded as V_over/I_over, and the overshoot voltage is defined as the difference between V_over and Vdd, as shown on the right side of Figure 4. Among them, the horizontal axis represents the voltage recorded at the terminal 3, the vertical axis represents the current supplied to the terminal 3, the trigger voltage V _TRIG when the latch effect is triggered is recorded as the voltage V _OVER , that is, the voltage at the terminal 3, and the trigger current I _TRIG is recorded as current I _OVER , the overshoot voltage is defined as V _MARGIN =V _OVER -Vdd.

Undershoot voltage test procedure: Terminal 1 is the P-well contact (ie, the second well region contact) connected to the second power supply voltage (Vss or GND), and Terminal 2 is one of the source or drain contacts of the NMOS in the p-well ( The other is floating) and used as input and output at the same time, terminal 3 is the source or drain contact of the PMOS in the n-well connected to the first power supply voltage (Vdd), and terminal 4 is connected to the first power supply voltage (Vdd) the N-well contacts. A current excitation signal is input to terminal 2, and the voltage of terminal 2 is recorded. The voltage/current point at which the device begins to appear negative resistance is recorded as V_under/I_under, and the undershoot voltage is defined as V_under, that is, the difference between the voltage of terminal 2 and Vss, as shown on the left side of Figure 4. Among them, the horizontal axis represents the voltage recorded at the terminal 2, the vertical axis represents the current supplied to the terminal 2, the trigger voltage V _TRIG when the latch effect is triggered is recorded as the voltage V _UNDER , and the trigger current I _TRIG is recorded as the current I _UNDER , then the following The surge voltage is defined as V _MARGIN =V _SS -V _UNDER .

Before the test, preset parameters including multiple test signals, such as 1000-20,000, preferably 5,000-10,000 spike waveforms per second as the excitation current, the waveform width is 10ns-300ns and preferably 100-150ns, and the amplitude is from 0 to 100uA, The step size is 0.2uA. In a preferred embodiment of the present invention, for the MOSFET to be tested, according to its process node (such as feature size) and manufacturing parameters or design rules (such as the device model used in SPICE simulation), reference is made to the historical results of previous measurements or stored in the database. For the measurement results of similar devices, the initial input excitation current is estimated, for example, the preset excitation current is at least 85%, and preferably at least 95%, of the historical results or the measurement results stored in the database, and is smaller than the historical results or the measurement results stored in the database. 99% and preferably less than 97%, so as to improve the measurement efficiency, save the time for stepwise adjustment of the input excitation current, and thus reduce the measurement cost.

In this way, through the above test process, the specifications of the overshoot voltage/undershoot voltage of the parasitic diode of the MOSFET can be quickly and accurately determined with a simplified structure, and the circuit design can adapt to the process characteristics and improve the success of the circuit design given the circuit constraints. rate, avoid rework of the circuit design, and improve the design cycle.

In fact, the test structure of the present application reasonably utilizes the adjacent NMOS and PMOS in the adjacent P and N wells to form the PNPN test structure, which is suitable for various process nodes such as sub-micron or deep sub-micron processes, and is also suitable for different Vdd Devices such as low voltage MOSFETs (eg Vdd of 5V or 1.2V) suitable for digital logic, memory devices and high voltage MOSFETs suitable for power drive (eg Vdd of 12V or 100V or even higher). In addition, the test structure of the present application can be applied not only to MOSFETs, but also to structures such as BJTs or BiMOSs with isolation between adjacent well regions.

According to the MOSFET overshoot voltage/undershoot voltage measurement structure and method of the present invention, the PNPN structure formed by the source-drain terminals and well contacts of adjacent NMOS and PMOS is used as the test structure, and the overshoot voltage and the undershoot voltage are measured by the latch method. The impulse voltage simplifies the test structure and improves the test efficiency.

Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structure without departing from the scope of the invention. In addition, many modifications, as may be adapted to a particular situation or material, may be made from the disclosed teachings without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structures and methods of making the same are to include all embodiments that fall within the scope of the present invention .

Claims (9)

1. a measuring structure of MOSFET overshoot voltage/undershoot voltage, is characterized in that, comprises: Adjacent N-well and P-well in the substrate, with PMOS and NMOS, respectively; the contact of the first well region arranged in the N well is used to connect the first power supply voltage; contacting a second well region disposed in the P well for connecting to a second power supply voltage; During the overshoot voltage test, one of the source or drain of the PMOS is used as the input for inputting the excitation current and simultaneously as the output for recording the output voltage, the other of the source or drain of the PMOS is floating, the NMOS The source terminal or the drain terminal is connected to the second power supply voltage; During the undershoot voltage test, one of the source or drain of the NMOS is used as the input for inputting the excitation current and simultaneously as the output for recording the output voltage, the other of the source or drain of the NMOS is floating, the other of the source or the drain of the PMOS The source terminal or the drain terminal is connected to the first power supply voltage. 2. The measurement structure of claim 1, wherein the first well region contact is adjacent to the source terminal or the drain terminal of the PMOS. 3. The measurement structure of claim 1, wherein the second well region contact is adjacent to the source terminal or the drain terminal of the NMOS. 4. The measurement structure of claim 1, wherein the first well contact includes an N-type doped region, and the second well region contact includes a P-type doped region. 5. The measurement structure of claim 4, wherein the N-type doped region is a heavily doped region. 6. The measurement structure of claim 4, wherein the P-type doped region is a heavily doped region. 7. A method for measuring using the measurement structure of the MOSFET overshoot voltage/undershoot voltage according to any one of claims 1 to 6, characterized in that, comprising: The first well region is connected to the first power supply voltage, the second well region is contacted to the second power supply voltage, and the excitation current input is used as the source or drain of the input terminal of the PMOS, or the excitation current input is used as the input terminal. Source or drain of NMOS to determine whether latch-up occurs; If yes, the difference between the output voltage of the source or drain of the PMOS and the first power supply voltage is recorded as the overshoot voltage, and the difference between the output voltage of the source or drain of the NMOS and the second power supply voltage is recorded as the undershoot Voltage; If not, continue to adjust the excitation current. 8. The method of claim 7, wherein the step of adjusting the input excitation current further comprises: If it is judged that latch-up has not occurred, increase the input excitation current until it is judged that latch-up has occurred and record the output voltage. 9. The method of claim 7, wherein the input excitation current comprises 1000-20,000 peak waveforms per second; optionally, the waveform width is 10-300 ns.

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