CN108595351A - A kind of DMA sending control methods of network-oriented forward process - Google Patents
A kind of DMA sending control methods of network-oriented forward process Download PDFInfo
- Publication number
- CN108595351A CN108595351A CN201810445371.9A CN201810445371A CN108595351A CN 108595351 A CN108595351 A CN 108595351A CN 201810445371 A CN201810445371 A CN 201810445371A CN 108595351 A CN108595351 A CN 108595351A
- Authority
- CN
- China
- Prior art keywords
- dma
- num
- txwr
- sent
- pointer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
- Computer And Data Communications (AREA)
Abstract
The present invention relates to a kind of DMA sending control methods of network-oriented forward process.Using the DMA address of storage of array grouping to be sent, while by the size for being dimensioned to all buffering areas in system of array.This control method need not safeguard a position busy for the interaction of software and hardware state for each array item, and DMA does not need the state in interface hardware rewriting memory when sending, therefore reduces bus overhead, can be obviously improved DMA sending performances.
Description
Technical field
The present invention be directed to a kind of hairs that direct memory access (DMA) is proposed between CPU and network interface in the network equipment
Send control method.
Background technology
In the realization of the network equipments such as high-performance router and interchanger, CPU generally passes through direct memory access (DMA)
Mode receives and dispatches message from network interface.This DMA communication means is directly to access memory by nothing by I/O buses by network interface
The intervention of CPU is needed, therefore the processing of CPU will not be interrupted when grouping passes in and out memory.
For the interface drive program of the network equipment in initialization, the pre- N number of packet buffer of first to file of meeting is put into free buffer
Qu Chizhong, and it is previously-completed physical address and the logical address mapping of each buffering area.After the completion of initialization, interface often receives one
When a grouping, just apply for that a freebuf is put into the grouping of reception, after forwarding is completed in grouping, as soon as a grouping is often sent,
The buffering area release that the grouping is occupied, is recycled by freebuf, is that the grouping of receipt of subsequent uses.
When DMA sends and is grouped, CPU will be ready for sending the buffer zone address of grouping in memory and notice network interface card, network interface card master
It is dynamic message to be sent is read into network interface from memory to send out.In order to recycle transmission buffering area, it will usually buffer
The busy mode bits of 1 bit are set in area.Busy mode bits are set as 1, interface by software by after the grouping write-in buffering area of transmission
Hardware will be grouped after buffering area reading, and 0 is set as by busy.When it is 0 that software, which checks busy, reusable this delays
Rush the new message to be sent of area's storage；If the positions busy of software discovery buffering area are 1, then it represents that hardware not yet will wherein
Grouping read, the buffering area cannot be used.
Therefore, interface hardware needs accessing operation at least twice, first, will report when the DMA for carrying out a message is sent
Text is read from memory, second is that by the positions busy clear 0 of the buffering area.Since bus bandwidth is limited, accessing operation limits twice
The performance of DMA transmissions is made.
Invention content
Present disclosure is a kind of novel DMA sending control methods.Using this method, interface hardware when DMA is sent
Literary accessing operation of once reading the newspaper only is needed, without modifying to busy mode bits, therefore bus overhead is reduced, can show
It writes and promotes DMA sending performances.
DMA operation principles proposed by the present invention are as shown in Fig. 1.
One, the data structure and variable of software are sent
It is the array that the length safeguarded in memory is M to send control table, the content of each array item be directed to one it is to be sent
Buffering of packets regional address.Core of the invention is exactly the transmission buffering that will be sent control table capacity M and be set as all in system
The quantity N in area.Such as initialize, Network Interface Driver applies for 64K buffering area in total, is just arranged then sending control table
It is 64K；
Software maintenance variable TxWr_pointer is directed to available transmission control table list item of next free time.When software has point
When group needs to send, by the transmission control table list item of the address write-in TxWr_pointer directions of the packet buffer；
TxWr_pointer is initialized as 0, if sometime the value of TxWr_pointer be k, as long as then software have it is to be sent
(such as the address of buffering area b) will fill in packet buffer into the list item k for sending control table, then existing pointer refers in the list item
To buffering area in will not be centainly grouping that hardware comes and sends not yet.(because if the list item pointer is also directed to not send out
The grouping sent has occupied N number of buffering area then being all the grouping for transmission in list item k ... N-1,0,1 ... K-1, and soft
Part currently sends the buffering area b being grouped, therefore at least N+1 buffering area in system there are one storage, this is system institute with N
There is the hypothesis test of buffering area number.As long as therefore buffering area to be sent will be written transmission control table, and tx_ptr etc. at this time
In k, then current entry k must be idle)；
Therefore, software carries out the synchronous of transmission state without using busy with DMA hardware, and DMA processes are sent for each grouping
Reduce by a secondary bus write operation, to improve the performance of DMA；
It sends software and also safeguards two variables of TxWr_num and Tx-Timer.TxWr_num is initialized as 0, has recorded warp-wise hair
Send the number of the grouping to be sent of control table write-in, software that a grouping to be sent, TxWr_ is written to transmission control table every time
Num adds 1；After the value notice DMA of TxWr_num is sent hardware by software, the value clear 0；Tx_timer has recorded from last time software
TxWr_num is advertised to hardware to start, to the time currently undergone.When TxWr_num is more than preset threshold values (K), or
When person Tx_timer overtime (reaching S seconds), software needs the value of TxWr_num noticing hardware, and hardware-initiated DMA is notified to send
Grouping.
Two, the register setting of DMA hardware
Interface DMA sends the register of two software-accessibles of hardware maintenance, TxRead_point_R and Txbuf_add_num_
R。
TxRead_point_R is initialized as sending the base address of control table, and direction should currently send the corresponding transmission control of grouping
The address of table list item；
Txbuf_add_num_R is initialized as 0, has recorded software and fills in buffering of packets regional address into transmission control table,
The grouping number not yet sent.
Three, software workflow
DMA software workflows proposed by the present invention are as shown in Fig. 2.Processing is divided into five steps；
The first step：When system initialization, by variable TxWr_pointer, TxWr_num and Tx_timer clear 0, by hardware register
TxRead_pointer_R is set to the base address for sending control table；
Second step：When there is message transmission, buffer zone address write-in where message is sent to the list item TxWr_ of control table
In pointer, TxWr_num is added 1 respectively；
Third walks：If TxWr_num is equal to K or Tx_timer equal to S, TxWr_num is write into hardware register Txbuf_
In rdy_num_R, while by TxWr_num and Tx_timer clear 0；
4th step：If TxWr_pointer is M-1, by TxWr_pointer clear 0, TxWr_pointer is otherwise added 1；
5th step：Second step is returned, next grouping is waited for send.
Four, DMA hardware workflow
Transmission DMA hardware workflow proposed by the present invention is as shown in Fig. 3.
The first step：When initialization, by Txbuf_rdy_num_R and Txbuf_add_num_R clear 0, software initialization Txread_
The value of pointer_R；
Second step：If Txbuf_add_num_R is more than 0, shows there is new grouping to need to send, Txbuf_add_R values are set as
The value of Txbuf_add_num_R, while by Txbuf_add_num_R clear 0；
Third walks：According to the address that Txread_pointer_R is preserved, read what Txbuf_add_R was respectively grouped from memory successively
DMA address reads the grouping sent by DMA, is sent out from interface；The content of Txread_pointer_R is updated simultaneously；
4th step returns to second step, waits for the value of software upgrading Txbuf_add_num_R.
The control method proposed by the present invention for sending DMA is realized by way of sending software and the collaboration of interface DMA hardware
High performance DMA.
Description of the drawings
Fig. 1 is the transmission DMA operation principles of the present invention；
Fig. 2 is to send software processing flow；
Fig. 3 is that interface sends DMA hardware process flow.
Specific implementation mode
The control method proposed by the present invention for sending DMA is realized by way of sending software and the collaboration of interface DMA hardware
High performance DMA.DMA sends software and is realized in the driving of network interface, and sending DMA hardware can be realized by FPGA,
It can be embedded into network interface card special chip and realize.The time S for sending threshold values K and Tx_timer time-out in software can be by static ginseng
Number configuration.K and S are bigger, and the expense that software and hardware interacts during transmission DMA is smaller, but it is bigger to be grouped the delay sent.Recommend K
Optional range is 32-128, and the optional ranges of S are 8us-512us, and user can be according to the interface rate of realization, at bus bandwidth, CPU
The factors such as reason expense and the delay requirement of packets forwarding determine specific parameter；
List item due to sending control table is physically continuous, and DMA hardware is with can once reading multiple transmission DMA
Location further decreases the expense of DMA；
Tissue is carried out in the way of array；The physical address of packet buffer to be sent is directed toward in storage in each list item；Hardware
Dma logic can read the physics DMA address of grouping to be sent from access control list, while it is pending to calculate next storage
Send the list item position of grouping address；
Number of the list item number not less than packet buffer in system of control table is sent, therefore need not be that each send controls
List item safeguards a position busy for the interaction of software and hardware state, can reduce the memory access behaviour that a DMA hardware changes busy
Make.
Claims (3)
1. a kind of DMA sending control methods of network-oriented forward process, the mode for sending software and DMA hardware collaboration realizes height
The DMA of performance, DMA send software and are realized in the driving of network interface, send DMA hardware and are realized by FPGA, can be also embedded in
To being realized in network interface card special chip, which is characterized in that
The time S for sending threshold values K and Tx_timer time-out in software passes through static parameter configuration；
Tissue is carried out in the way of array；
It is the array that the length safeguarded in memory is M to send control table, the content of each array item be directed to one it is to be sent
Buffering of packets regional address, control table capacity M will be sent be set as the quantity N of all transmission buffering areas in system；
The physical address of packet buffer to be sent is directed toward in storage in each list item；
DMA hardware logic reads the physics DMA address of grouping to be sent from access control list, while calculating next storage and waiting for
Send the list item position of grouping address；
Number of the list item number not less than packet buffer in system of control table is sent, therefore need not be that each send controls
List item safeguards a position busy for the interaction of software and hardware state, can reduce the accessing operation that a DMA hardware changes busy.
2. a kind of DMA sending control methods of network-oriented forward process according to claim 1, which is characterized in that institute
It states to send software and handle and is divided into five steps；
The first step：When system initialization, by variable TxWr_pointer, TxWr_num and Tx_timer clear 0, by hardware register
TxRead_pointer_R is set to the base address for sending control table；
Second step：When there is message transmission, buffer zone address write-in where message is sent to the list item TxWr_ of control table
In pointer, TxWr_num is added 1 respectively；
Third walks：If TxWr_num is equal to K or Tx_timer equal to S, TxWr_num is write into hardware register Txbuf_
In rdy_num_R, while by TxWr_num and Tx_timer clear 0；
4th step：If TxWr_pointer is M-1, by TxWr_pointer clear 0, TxWr_pointer is otherwise added 1；
5th step：Second step is returned, next grouping is waited for send.
3. a kind of DMA sending control methods of network-oriented forward process according to claim 1, which is characterized in that institute
Stating DMA hardware workflow is specially：
1st step：When initialization, by Txbuf_rdy_num_R and Txbuf_add_num_R clear 0, software initialization Txread_
The value of pointer_R；
2nd step：If Txbuf_add_num_R is more than 0, shows there is new grouping to need to send, Txbuf_add_R values are set as
The value of Txbuf_add_num_R, while by Txbuf_add_num_R clear 0；
3rd step：According to the address that Txread_pointer_R is preserved, the DMA that Txbuf_add_R is respectively grouped is read from memory successively
Address reads the grouping sent by DMA, is sent out from interface；The content of Txread_pointer_R is updated simultaneously；
4th step returns to the 2nd step, waits for the value of software upgrading Txbuf_add_num_R.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810445371.9A CN108595351B (en) | 2018-05-11 | 2018-05-11 | DMA (direct memory access) sending control method oriented to network forwarding processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810445371.9A CN108595351B (en) | 2018-05-11 | 2018-05-11 | DMA (direct memory access) sending control method oriented to network forwarding processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108595351A true CN108595351A (en) | 2018-09-28 |
| CN108595351B CN108595351B (en) | 2021-04-09 |
Family
ID=63636543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810445371.9A Active CN108595351B (en) | 2018-05-11 | 2018-05-11 | DMA (direct memory access) sending control method oriented to network forwarding processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108595351B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112835823A (en) * | 2021-01-25 | 2021-05-25 | 无锡众星微系统技术有限公司 | Storage controller response sending method |
| CN116319602A (en) * | 2021-12-07 | 2023-06-23 | 联发科技股份有限公司 | Packet forwarding device with buffer reclamation and related packet forwarding method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1908925A (en) * | 2006-08-15 | 2007-02-07 | 武汉虹旭信息技术有限责任公司 | Method for improving PCI communication credibility and efficiency |
| CN101188560A (en) * | 2007-12-18 | 2008-05-28 | 杭州华三通信技术有限公司 | Method and device for dynamically detecting forward capability |
| CN101673253A (en) * | 2009-08-21 | 2010-03-17 | 曙光信息产业(北京)有限公司 | Realizing method of direct memory access (DMA) |
| CN102420749A (en) * | 2011-11-28 | 2012-04-18 | 曙光信息产业(北京)有限公司 | Device and method for realizing network card issuing function |
| CN102724112B (en) * | 2012-05-31 | 2015-03-25 | 华为技术有限公司 | Transmission method, receiving terminal equipment and system based on TCP (transmission control protocol) |
-
2018
- 2018-05-11 CN CN201810445371.9A patent/CN108595351B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1908925A (en) * | 2006-08-15 | 2007-02-07 | 武汉虹旭信息技术有限责任公司 | Method for improving PCI communication credibility and efficiency |
| CN101188560A (en) * | 2007-12-18 | 2008-05-28 | 杭州华三通信技术有限公司 | Method and device for dynamically detecting forward capability |
| CN101673253A (en) * | 2009-08-21 | 2010-03-17 | 曙光信息产业(北京)有限公司 | Realizing method of direct memory access (DMA) |
| CN102420749A (en) * | 2011-11-28 | 2012-04-18 | 曙光信息产业(北京)有限公司 | Device and method for realizing network card issuing function |
| CN102724112B (en) * | 2012-05-31 | 2015-03-25 | 华为技术有限公司 | Transmission method, receiving terminal equipment and system based on TCP (transmission control protocol) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112835823A (en) * | 2021-01-25 | 2021-05-25 | 无锡众星微系统技术有限公司 | Storage controller response sending method |
| CN112835823B (en) * | 2021-01-25 | 2022-03-01 | 无锡众星微系统技术有限公司 | Storage controller response sending method |
| CN116319602A (en) * | 2021-12-07 | 2023-06-23 | 联发科技股份有限公司 | Packet forwarding device with buffer reclamation and related packet forwarding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108595351B (en) | 2021-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103888293B (en) | Data channel scheduling method of multichannel FC network data simulation system | |
| CN109558344B (en) | A DMA transmission method suitable for network transmission and DMA controller | |
| US9846650B2 (en) | Tail response time reduction method for SSD | |
| US6735662B1 (en) | Method and apparatus for improving bus efficiency given an array of frames to transmit | |
| CN105094983A (en) | Computer, control device and data processing method | |
| US20190042151A1 (en) | Hybrid framework of nvme-based storage system in cloud computing environment | |
| CN102945215A (en) | Information processing apparatus and method, and program | |
| CN106598752A (en) | Remote zero-copy method | |
| CN101150486A (en) | A management method for receiving network data of zero copy buffer queue | |
| CN111290979B (en) | Data transmission method, device and system | |
| CN116414767A (en) | Reordering method and system for AXI protocol-based out-of-order response | |
| CN117707991B (en) | Data reading and writing method, system, equipment and storage medium | |
| CN117215989B (en) | Heterogeneous acceleration device, heterogeneous acceleration system, heterogeneous acceleration method, heterogeneous acceleration device and storage medium | |
| CN108595351A (en) | A kind of DMA sending control methods of network-oriented forward process | |
| CN102713873B (en) | inserts gaps in the information sent from the drive to the host device | |
| CN112035898A (en) | Multi-node multi-channel high-speed parallel processing method and system | |
| CN111181874B (en) | A message processing method, device and storage medium | |
| TW200406682A (en) | Method, system and program for configuring components on a bus for input/output operations | |
| CN101741727B (en) | How to use triple buffering to process data | |
| CN113177211A (en) | FPGA chip for privacy computation, heterogeneous processing system and computing method | |
| CN114995770B (en) | Data processing method, device, equipment, system and readable storage medium | |
| US12019909B2 (en) | IO request pipeline processing device, method and system, and storage medium | |
| CN112269649B (en) | Method, device and system for implementing asynchronous execution of host tasks | |
| JP7363344B2 (en) | Memory control device and control method | |
| US9424227B2 (en) | Providing byte enables for peer-to-peer data transfer within a computing environment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |