CN108614271B - Multichannel ultrasonic wave arbitrary waveform signal generator with feedback correction - Google Patents

Abstract

The invention discloses a multi-channel ultrasonic arbitrary waveform signal generator with feedback correction, including a PC terminal, a JTAG interface, an FPGA, an active crystal oscillator, a DAC module, a filter module, a feedback module and a start key; the invention adopts DDS technology for parallel processing Generate m-channel phase signals; and add a feedback module and feedback signal processing module after the filter circuit; its characteristic is that only one m-channel selector and ADC module are used to detect multi-channel signals, which greatly reduces the consumption of resources and makes the structure More compact; at the same time, the feedback signal processing module can detect the actual initial phase of multi-channel signals; it only uses a zero point detection module to obtain the initial phase of all channels in sequence and combines the look-up table to perform amplitude and phase conversion, which greatly reduces Feedback signal processing resources occupied.

Description

A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction

Technical field

The invention relates to a multi-channel DDS signal generator, and in particular to a multi-channel ultrasonic arbitrary waveform signal generator with feedback correction.

Background technique

Ultrasonic phased array technology controls the emission of each element of the array transducer to form various effects such as focusing and scanning of the synthetic sound beam, thereby performing ultrasonic imaging. In the phased array ultrasonic emission state, each array element in the array transducer is sequentially excited according to a certain delay rule, and the generated ultrasonic emission sub-beams are synthesized in space to form a focus point and directivity. Changing the delay pattern of excitation of each array element can change the focus position and beam direction, forming a scanning focus within a certain spatial range. The key digital technology in the ultrasonic phased array system mainly refers to the spatio-temporal control of the beam. Advanced digital electronic technology and microcomputer technology are used to accurately control the phased beam in the launch state to obtain the best launch beam characteristics.

Compared with traditional frequency synthesizers, direct digital frequency synthesizers (DDS) have many advantages in frequency synthesis and arbitrary waveform generation, such as fast frequency conversion, short output signal setup time, high spectrum purity, extremely high frequency accuracy and resolution and easy control of various modulation methods. FPGA (Field-Programmable Gate Array), as a high-performance programmable logic device, can provide excellent solutions for a variety of circuits. For digital frequency synthesis, implementation with FPGA will be more flexible and easier to control. Moreover, because FPGA has a particularly high level of integration, the entire system can be downloaded to the same chip to implement a so-called system on a chip (SoC), thereby increasing the size of the product and improving the reliability of the system.

In the existing multi-channel ultrasonic signal transmission technology, the basic structure of each channel consists of a phase accumulator (PD), a waveform memory (RAM), a digital-to-analog converter (DAC) and a low-pass filter (LPF), which are independent of each other. Multi-channel signal generator with certain phase difference.

The above-mentioned ultrasonic phased array transmission technology has the following shortcomings: 1. Due to the delay difference between wiring and chips, the phase error between the actual phase and the ideal phase is large. 2. A multi-channel signal generator with feedback requires multiple phase accumulators (PD), waveform memory (RAM), digital-to-analog converter (DAC), filter circuits and analog-to-digital converters (ADC) to form a circuit when using multiple channels. Complex and difficult to implement.

Contents of the invention

The purpose of the present invention is to provide a multi-channel ultrasonic arbitrary waveform signal generator with feedback correction in view of the shortcomings of the existing technology.

The object of the present invention is achieved through the following technical solutions: a multi-channel ultrasonic arbitrary waveform signal generator with feedback correction, including a PC terminal, JTAG interface, FPGA, DAC module, filter module, and feedback module;

The PC side stores the phase and amplitude mapping data of the ultrasonic waveform into m waveform lookup table RAMs through the JTAG interface, where m represents the number of channels, and stores the amplitude and phase mapping data into two phase lookup table RAMs. The first phase lookup table stores the phase information of the first and fourth quadrants, and the second phase lookup table stores the phase information of the second and third quadrants. The data type of the phase signal and the amplitude signal is a binary unsigned number, defined The highest bit represents the sign bit, and the remaining bits represent the data bits;

The FPGA receives the mapping data, channel control signal, frequency control signal and initial phase signal in the corresponding RAM through the JTAG interface; DDS is used inside the FPGA to form m channels and m channel signals based on the channel control signal and frequency control signal. Search the corresponding waveform lookup table in turn to obtain the amplitude signal corresponding to the phase, then connect the amplitude signal to the DAC module for digital-to-analog conversion, and then use the filter module to filter the output waveform. Each channel after filtering Connect to the feedback module;

The feedback module is composed of a multiplexer and an ADC module; the multiplexer and the ADC module sample each channel in turn, and transport the sampled signals to the feedback signal processing module in the FPGA;

The feedback signal processing module includes a buffer, a zero point detection module, a phase compensation unit, a phase difference calculation unit, a state detection unit and a phase correction unit;

The zero point detection module is composed of a comparator and an m-digit counter. The counter of the zero point detection module starts counting and compares the sampled amplitude signal with the minimum amplitude signal in the m channels. If the amplitude signal is detected, If the value is greater than the minimum amplitude, the amplitude signal is recorded as _wi , and the corresponding channel number i is obtained from the counter, and the subsequent m-1 amplitude signals are recorded as: wi ₊₁ w _i+2 ...w _m w ₁ w ₂ …w _i-1 , the corresponding channel number is recorded as: i+1 i+2 … 1 2 …i-1; then take the value of each channel after one counting period: w′ _i w ′ _i+1 w′ _i+2 … w′ _m w′ ₁ w′ ₂ … w′ _i-1 ; send the obtained data to the state detection unit, and compare the previous amplitude signal of each channel with the next amplitude The signals are subtracted, and the value of the highest bit, that is, the sign bit, is represented by A; if the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, then A = 0, if it is less than, then A = 1; at the same time, m The path amplitude signal w _i w _i+1 w _i+2 … w _m w ₁ w ₂ … w _i-1 is sent to the phase compensation unit, and the corresponding phase value is obtained from the phase lookup table using the table lookup method. If A= 1, then query the corresponding phase from the first phase lookup table; if A=0, query the corresponding phase value from the second phase lookup table; and compensate the phase of each channel;

The phase difference calculation unit subtracts the compensated phase value from the preset initial phase signal to obtain the phase difference of each channel, and the highest bit, that is, the sign bit value is represented by B; if the compensated phase value is greater than the initial phase, Then B=0, if less than B=1; then modify the initial phase according to the phase difference calculation unit; B=0 means the phase is ahead, B= means the phase is lagging; if it is ahead, the initial phase of the channel is modified according to the phase correction unit The phase difference is subtracted. If it lags behind, the complement of the phase difference is added to the initial phase according to the phase correction unit, and finally it is fed back to the DDS for correction.

Furthermore, MATLAB is used to generate the phase-to-amplitude .mif file and the amplitude-to-phase .mif file on the PC. The RAM IP core is generated through the IP core function in the Quartus Ⅱ software, and the generated .mif file data is imported. Among them; the control instructions and transmission parameters are transmitted to the FPGA through the JTAG interface.

Further, the clock signal f _cLk is generated through the active crystal oscillator and connected to the multiplexer and ADC of the FPGA, DAC module, feedback module respectively.

Further, the channel control signal includes the channel number and channel number m selected by the user, the frequency control signal is the frequency signal for transmitting the ultrasonic waveform set by the user, and the initial phase signal is the frequency signal for transmitting the ultrasonic waveform set by the user. initial phase signal.

Further, the FPGA receives the channel control signal and the frequency control signal to generate a corresponding phase accumulator, and sends the data output by the phase accumulator to the corresponding m adders for accumulation with the received initial phase signal to obtain each According to the address information of the channel, go to its corresponding waveform lookup table to find the amplitude signal corresponding to the phase.

The beneficial effects of the present invention are: compared with the existing technology, the present invention uses DDS technology to generate m phase signals in parallel. And add a feedback module and feedback signal processing module after the filter circuit. Its characteristic is that only one m-channel selector and ADC module are used to detect multi-channel signals, which greatly reduces resource consumption and makes the structure more compact. At the same time, the feedback signal processing module can detect the actual initial phase of multi-channel signals. It uses only one zero-point detection module to obtain the initial phases of all channels in sequence and combines the look-up table method to convert the amplitude and phase, which improves the accuracy of phase detection and greatly reduces the resources occupied by feedback signal processing.

Description of the drawings

Figure 1 is a schematic diagram of the overall structure of the present invention;

Figure 2 is a diagram of the internal working principle of FPGA;

Figure 3 is the working principle diagram of DDS;

Figure 4 is a schematic block diagram of the feedback module;

Figure 5 is a schematic block diagram of feedback signal processing.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

The present invention can use MATLAB to generate a phase-to-amplitude .mif file and an amplitude-to-phase .mif file on the PC (personal computer) side. Through the rich IP core (intellectual property core) function in the QuartusⅡ software provided by Altera, the RAM IP core is generated and the generated .mif file data is imported into it. Write the control program and emission parameters, and transfer them to the development board of Altera's FPGA (Field Programmable Gate Array) chip through the JTAG interface, so that the corresponding phase and amplitude information are stored in the corresponding waveform lookup table (RAM) and Phase lookup table (RAM), and form a dedicated circuit inside the FPGA.

Figure 1 is a schematic diagram of the overall structure of the present invention. The present invention mainly includes a PC terminal, JTAG interface, FPGA, active crystal oscillator, DAC module, filter module, feedback module and start key. The PC side stores the phase and amplitude mapping data of the ultrasonic waveform into m waveform lookup tables through the JTAG interface, where m represents the number of channels. The amplitude and phase mapping data are stored in two phase lookup tables. The first one The phase lookup table of the amplitude and phase mapping stores the phase information of the first and fourth quadrants, and the second phase lookup table of the amplitude and phase mapping stores the phase information of the second and third quadrants. And form corresponding dedicated circuits inside the FPGA. The clock signal f _cLk generated by the active crystal oscillator is connected to the FPGA, DAC module and feedback module respectively.

Figure 2 shows the internal working principle diagram of FPGA. The FPGA receives the mapping data, channel control signal, frequency control signal and initial phase signal in the corresponding RAM through the JTAG interface; the channel control signal includes the channel number and channel number m selected by the user, and the frequency control signal is set by the user Transmit the frequency signal of the ultrasonic waveform, and the initial phase signal is the initial phase signal of the ultrasonic waveform set by the user; when the data transmission is completed, press the start button; use DDS (direct digital frequency synthesizer) inside the FPGA, according to The channel control signal and the frequency control signal form m channels. The signals of the m channels are sequentially obtained from the corresponding waveform lookup table i to obtain the amplitude signal corresponding to the phase, and then the amplitude signal is connected to the DAC (digital-to-analog converter) Digital-to-analog conversion is performed in the module, and then the output waveform is filtered. Each filtered channel is connected to the feedback module, and the signal output by the feedback module is connected to the feedback signal processing module in the FPGA.

Figure 3 shows the working principle diagram of DDS. The FPGA receives the channel control signal and frequency control signal to generate a corresponding phase accumulator, and sends the data output by the phase accumulator to the corresponding m adders to accumulate with the received initial phase signal to obtain the address information of each channel. According to the address information, go to its corresponding waveform lookup table i to find the amplitude signal corresponding to the phase.

Figure 4 shows a schematic block diagram of the feedback module in the present invention. It consists of a multiplexer and an ADC module. The multiplexer and the ADC module use the same frequency f _cLk clock signal. It samples each channel in turn and transmits the sampled signals to the feedback signal processing module in the FPGA.

Figure 5 shows a schematic block diagram of feedback signal processing of the present invention. The zero-point detection module consists of a comparator and an m-digit counter. The value of m is determined by the channel control signal. Its working principle is that the counter starts counting and compares the sampled amplitude signal with the minimum amplitude signal among the m channels. If the detected amplitude is greater than the minimum value, the amplitude signal is recorded as _wi , and the corresponding channel number i is obtained from the counter, and the data is stored in the memory in sequence, and the subsequent m-1 amplitude signals are It is recorded as: w _i+1 w _i+2 … w _m w ₁ w ₂ … w _i-1 , and the corresponding channel number is recorded as: i+1 i+2 … 1 2 … i-1; and so on Take the value of each channel after one counting period: w′ _i w′ _i+1 w′ _i+2 … w′ _m w′ ₁ w′ ₂ … w′ _i-1 . The obtained data is sent to the state detection unit, and the previous amplitude signal of each channel is subtracted from the next amplitude signal. The value of the highest bit, that is, the sign bit, is represented by A. If the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, then A=0; if it is less than the amplitude of the next amplitude signal, A=1.

At the same time, m amplitude signals w _i w _i+1 w _i+2 ... w _m w ₁ w ₂ ... w _i-1 are sent to the phase compensation unit, and the corresponding phase value p is obtained from the phase lookup table using the table lookup method. _i , if A=1, query the corresponding phase value from the first phase lookup table. If A=0, query the corresponding phase value from the second phase lookup table. And compensate the phase of each channel: that is, the phase of channel i is p _i -0, the phase of the second channel is p _i+1 -1, and the phase of the last channel is p _i-1 -(m-1) .

The phase difference calculation unit subtracts the compensated phase value from the preset initial phase signal to obtain the phase difference of each channel. The value of the highest bit, the sign bit, is represented by B. If the compensated phase value is greater than the initial phase, then B = 0, if less than B=1. The initial phase is then modified according to the phase difference calculation unit. For example, B=0 means the phase leads; B=1 means the phase lags. If it leads, the phase difference is subtracted from the initial phase of the channel. If it lags, the complement of the phase difference is added to the initial phase, and finally it is fed back to the DDS for correction.

In this description, it should be pointed out that the multi-channel signal generator provided in the embodiment of the present invention is only a specific example of the present invention. Obviously, the technical solution of the present invention is not limited to the signal generator described in the above example. In fact, various modifications, transformations and transformations can be made to the technical solution of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. Any simple modifications and equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention should be considered to belong to the protection scope of the present invention.

Claims (5)

1. A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction, characterized by including a PC terminal, JTAG interface, FPGA, DAC module, filter module, and feedback module; The PC side stores the phase and amplitude mapping data of the ultrasonic waveform into m waveform lookup table RAMs through the JTAG interface, where m represents the number of channels, and stores the amplitude and phase mapping data into two phase lookup table RAMs. The first phase lookup table stores the phase information of the first and fourth quadrants, and the second phase lookup table stores the phase information of the second and third quadrants. The data type of the phase signal and the amplitude signal is a binary unsigned number, defined The highest bit represents the sign bit, and the remaining bits represent the data bits; The FPGA receives the mapping data, channel control signal, frequency control signal and initial phase signal in the corresponding RAM through the JTAG interface; DDS is used inside the FPGA to form m channels and m channel signals based on the channel control signal and frequency control signal. Search the corresponding waveform lookup table in turn to obtain the amplitude signal corresponding to the phase, then connect the amplitude signal to the DAC module for digital-to-analog conversion, and then use the filter module to filter the output waveform. Each channel after filtering Connect to the feedback module; The feedback module is composed of a multiplexer and an ADC module; the multiplexer and the ADC module sample each channel in turn, and transport the sampled signals to the feedback signal processing module in the FPGA; The feedback signal processing module includes a buffer, a zero point detection module, a phase compensation unit, a phase difference calculation unit, a state detection unit and a phase correction unit; The zero point detection module is composed of a comparator and an m-digit counter. The counter of the zero point detection module starts counting and compares the sampled amplitude signal with the minimum amplitude signal in the m channels. If the amplitude signal is detected, If the value is greater than the minimum amplitude, the amplitude signal is recorded as w _i , and the corresponding channel number i is obtained from the counter, and the subsequent m-1 amplitude signals are recorded as: w _i+1 w _i+2 ... w _m w ₁ w ₂ … w _i-1 , the corresponding channel number is recorded as: i+1 i+2 … 1 2 …i-1; then take the value of each channel after one counting period: w′ _i w ′ _i+1 w′ _i+2 … w′ _m w′ ₁ w′ ₂ … w′ _i-1 ; send the obtained data to the state detection unit, and compare the previous amplitude signal of each channel with the next amplitude The signals are subtracted, and the value of the highest bit, that is, the sign bit, is represented by A; if the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, then A = 0, if it is less than, then A = 1; at the same time, m The path amplitude signal w _i w _i+1 w _i+2 … w _m w ₁ w ₂ … w _i-1 is sent to the phase compensation unit, and the corresponding phase value is obtained from the phase lookup table using the table lookup method. If A= 1, then query the corresponding phase value from the first phase lookup table; if A=0, query the corresponding phase value from the second phase lookup table; and compensate the phase of each channel; The phase difference calculation unit subtracts the compensated phase value from the preset initial phase signal to obtain the phase difference of each channel, and the highest bit, that is, the sign bit value is represented by B; if the compensated phase value is greater than the initial phase, Then B=0, if less than B=1; then modify the initial phase according to the phase difference calculation unit; B=0 means the phase is ahead, B= means the phase is lagging; if it is ahead, the initial phase of the channel is modified according to the phase correction unit The phase difference is subtracted. If it lags behind, the complement of the phase difference is added to the initial phase according to the phase correction unit, and finally it is fed back to the DDS for correction. 2. A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, characterized in that MATLAB is used to generate a phase-to-amplitude .mif file and an amplitude-to-phase .mif file on the PC. file, generate the RAM IP core through the IP core function in the Quartus II software, and import the generated .mif file data into it; transfer the control instructions and launch parameters into the FPGA through the JTAG interface. 3. A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, characterized in that the clock signal f _cLk is generated by an active crystal oscillator and is connected to the FPGA, DAC module and feedback module respectively. on the multiplexer and ADC. 4. A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, wherein the channel control signal includes a user-selected channel number and channel number m, and the frequency control signal is A frequency signal for transmitting ultrasonic waveforms set by the user, and the initial phase signal is an initial phase signal for transmitting ultrasonic waveforms set by the user. 5. A multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, characterized in that the FPGA receives the channel control signal and the frequency control signal to generate a corresponding phase accumulator to accumulate the phases. The data output by the device is sent to the corresponding m adders and accumulated with the received initial phase signal to obtain the address information of each channel. According to the address information, it is entered into its corresponding waveform lookup table to find the amplitude signal corresponding to the phase.