CN108667852B

CN108667852B - Method for framing and sending SV message by FPGA

Info

Publication number: CN108667852B
Application number: CN201810496312.4A
Authority: CN
Inventors: 赵立; 王涛; 肖庆华; 余传坤; 苏忠阳; 蔡泽祥
Original assignee: Guangzhou Smart Energy Technology Co ltd
Current assignee: Guangzhou Smart Energy Technology Co ltd
Priority date: 2018-05-22
Filing date: 2018-05-22
Publication date: 2021-02-12
Anticipated expiration: 2038-05-22
Also published as: CN108667852A

Abstract

The invention provides a method for framing and sending SV messages by an FPGA (field programmable gate array), which comprises the following steps of: 1) receiving configuration information issued by software; 2) selecting a sending channel and carrying out operation; 3) framing SV messages; 4) sending SV messages; the channel unit, the multiplier unit, the divisor unit, the sampling threshold value unit, the quality unit and the SV frame header unit are configuration information which is issued to an FPGA internal storage unit by software. According to the method for realizing SV message framing and sending by the FPGA, the SV framing, the threshold value comparison, the quality bit acquisition and the multiplication and division operation from the secondary value to the primary value are realized by the FPGA method, and compared with a CPU, the efficiency is higher; the framing form is flexible, and SV framing can be performed on analog quantity data acquired by AD by selecting any channel.

Description

Method for framing and sending SV message by FPGA

Technical Field

The invention relates to the technical field of power systems, in particular to a method for framing and sending SV messages by an FPGA.

Background

At present, the IEC61850 standard proposes the concept of substation automation system function layering. Dividing the transformer substation equipment into three layers according to functions: namely a process layer, a spacer layer, and a station control layer.

The process layer mainly has the functions of converting the alternating current analog quantity, the direct current analog quantity and the state quantity into digital signals on site and providing the digital signals to an upper layer, and receiving and executing a control command issued by the upper layer. The process layer devices include primary devices and their intelligent components.

The main function of the spacing layer is to collect the signal of the spacing primary equipment, control and operate the primary equipment, upload the related information to the station control layer equipment and receive the command of the station control layer equipment. The spacer layer equipment consists of control, protection and monitoring devices for each spacer.

The station control layer has the main functions of monitoring and controlling the primary and secondary devices of the whole station and communicating with a remote control center. The station control layer equipment comprises a monitoring host, a telecontrol workstation, an operation workstation, a time synchronization system and the like.

Sv (sampled value) messages also use a publisher/subscriber communication structure. SV messages are a time-driven communication method, i.e. sampled values are sent every fixed time. The most important transmission requirements are real-time performance and rapidity. When the message transmission is lost due to network reasons, the publisher (current and voltage sensor) is not critical, and the latest current and voltage information should be collected continuously. And the subscriber (e.g., the protection device) must be able to detect it. This can be solved by the sample counter parameter SmpCnt in the SV message.

In the prior art, the SV message is packaged by utilizing the stronger computing capability of a CPU, the sending time is appointed for the SV message, the SV message is sent to a sending buffer area of an FPGA, the FPGA periodically inquires whether the sending buffer area has the message or not, if the message exists, the sending time of the message is analyzed, the sending time is compared with the time of a high-precision timer in the FPGA, and the SV message is sent out at the sending time point of the SV message. The calculation and the package of SV messages are completed by a CPU, and the FPGA is only responsible for the timed sending of SV messages.

In the prior art, the acquired value is required to be sent to a CPU firstly, then the CPU processes the acquired value to acquire quality information, performs multiplication and division operation from a secondary value to a primary value, then packages the acquired value into an SV message and appoints sending time, so that the processing process causes overlong delay and increases the processing time of the CPU, and the message sending time needs to be repeatedly corrected so as to achieve the maximum and minimum delay and accurate sending.

Therefore, it is necessary to provide a method for framing and transmitting SV messages by an FPGA to solve the above technical problems.

Disclosure of Invention

The invention mainly solves the technical problem of providing a method for realizing SV message framing and sending by an FPGA (field programmable gate array). the method of the FPGA is adopted to realize SV framing, threshold value comparison, quality bit acquisition and multiplication and division operation from a secondary value to a primary value, and the efficiency is higher compared with a CPU (central processing unit); the group packing form is flexible, and SV frame packing can be carried out on analog quantity data acquired by AD by selecting any channel.

In order to solve the above technical problems, one technical solution adopted by the present invention is to provide a method for framing and sending SV messages by an FPGA, comprising the steps of:

1) receiving configuration information issued by software:

receiving channel selection of collected data;

receiving a multiplier of multiplication operation to be carried out by a corresponding channel;

receiving a divisor of division operation to be performed by a corresponding channel;

receiving a sampling threshold value of a corresponding channel;

receiving quality of a corresponding channel;

receiving an SV message header;

AD acquisition analog quantity data based on the FPGA;

2) selecting a sending channel and calculating:

comparing the analog quantity data with a corresponding sampling threshold value to obtain invalid bit information of a quality domain;

performing multiplication and division operation on the selected channel according to the channel selection information;

performing quality domain correction on the selected channel according to the channel selection information;

3) framing SV messages:

framing an SV message header, a channel multiplication and division result and a quality domain correction result;

adding a destination address, a source address and a check domain;

updating a sampling count value and sampling synchronization domain information at each group of SV frame time sequence;

4) and (3) sending SV messages:

and sending SV messages through the Ethernet.

Preferably, in the step 3), the group SV frames are performed at a frequency of 4KHz per second, the count value at the head of a second is 0, and the count range is 0 to 3999.

Preferably, the receiving of the configuration information in step 1) can be configured or modified only under the condition that SV message transmission is not enabled.

The invention has the beneficial effects that: according to the method for realizing SV message framing and sending by the FPGA, the SV framing, the threshold value comparison, the quality bit acquisition and the multiplication and division operation from the secondary value to the primary value are realized by the FPGA method, and the efficiency is higher compared with a CPU; the framing form is flexible, and SV framing can be performed on analog quantity data acquired by AD by selecting any channel.

Drawings

Fig. 1 is a schematic flowchart of a method for framing and transmitting SV messages by an FPGA according to a first preferred embodiment of the present invention;

fig. 2 is a schematic diagram illustrating a first preferred embodiment of a method for framing and sending SV messages by an FPGA according to the present invention.

Detailed Description

The technical solution of the present invention will be described in detail with reference to the drawings.

Referring to fig. 1 and fig. 2, the method for framing and sending SV messages by an FPGA of this embodiment includes the steps of:

1) receiving configuration information 212 issued by software:

receiving a channel selection of the collected data (channel unit 21);

a multiplier (multiplier unit 22) for receiving a multiplication operation to be performed by the corresponding channel;

receiving a divisor to be subjected to division operation of a corresponding channel (divisor unit 23);

receiving a sampling threshold value (threshold value unit 25) of a corresponding channel;

receiving the quality of the corresponding channel (quality unit 26);

receiving an SV packet header (SV frame header unit 24);

AD acquisition analog quantity data based on the FPGA (AD acquisition analog quantity data 213);

2) the transmit channel 27 is selected and operated on:

comparing the analog quantity data with a corresponding sampling threshold value by a threshold value 28 to obtain invalid bit information of a quality domain;

performing a multiply-divide operation (converting the quadratic value into a primary value 29) on the selected channel according to the channel selection information;

performing quality domain correction 210 on the selected channel according to the channel selection information;

3) SV message framing 211:

adding a destination address, a source address and a check domain;

4) sending SV message 215:

sending SV message through Ethernet;

the channel unit 21, the multiplier unit 22, the divisor unit 23, the sampling threshold unit 25, the quality unit 26, and the SV frame header unit 24 are configuration information that is issued by software to an internal storage unit of the FPGA.

In this embodiment, the analog data 213 acquired by the AD is acquired by the FPGA instead of being issued by software, which has the advantage that the AD acquired data is directly subjected to SV framing transmission by hardware without passing through a software layer, thereby improving the data transmission efficiency.

According to the method for realizing SV message framing and sending by the FPGA, the SV message framing, the threshold value comparison, the quality bit acquisition and the multiplication and division operation from the secondary value to the primary value are realized by utilizing the FPGA chip, and compared with the SV message framing and sending by using a traditional CPU chip, the efficiency is higher; and the framing form is more flexible, and SV message framing can be carried out on analog quantity data acquired by AD by selecting channels at will.

In this embodiment, the framing format is shown in the following table:

in a preferred embodiment of the present invention, in the step 3), the group SV frames are performed at a frequency of 4KHz per second, and the count value at the head of second is 0, and the count range is 0 to 3999. Of course, the specific value of the frequency in this embodiment is not limited to 4KHz, and the specific value is selected according to the design requirement, which is not limited thereto.

In an embodiment of the present invention, preferably, the receiving of the configuration information in step 1) can be configured or modified only without enabling SV message transmission.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures made by using the contents of the specification and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.

Claims

1. A method for realizing SV message framing and sending by FPGA is characterized in that: the method comprises the following steps:

1) receiving configuration information issued by software:

receiving channel selection of collected data;

receiving a sampling threshold value of a corresponding channel;

receiving quality of a corresponding channel;

receiving an SV message header;

AD acquisition analog quantity data based on the FPGA;

2) selecting a sending channel and calculating:

3) framing SV messages:

adding a destination address, a source address and a check domain;

4) and (3) sending SV messages:

and sending SV messages through the Ethernet.

2. The method for framing and transmitting SV messages by FPGA according to claim 1, wherein the method comprises the following steps: in the step 3), the SV frame group is carried out at the frequency of 4KHz per second, the counting value at the second head is 0, and the counting range is 0-3999.

3. The method for framing and transmitting SV messages by FPGA according to claim 1, wherein the method comprises the following steps: the reception of the configuration information of step 1) can only be configured or modified without enabling SV message transmission.