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CN108682649B - SOI substrate, semiconductor device and method of forming the same - Google Patents

SOI substrate, semiconductor device and method of forming the same Download PDF

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CN108682649B
CN108682649B CN201810343686.2A CN201810343686A CN108682649B CN 108682649 B CN108682649 B CN 108682649B CN 201810343686 A CN201810343686 A CN 201810343686A CN 108682649 B CN108682649 B CN 108682649B
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CN108682649A (en
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陈达
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China Core Integrated Circuit Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

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Abstract

本发明公开了SOI衬底、半导体器件及其形成方法。该半导体器件包括：SOI衬底，该SOI衬底的顶层硅与氧化层的接触面上存在凹陷区域，所述凹陷区域位于有源区；位于顶层硅中的隔离结构；位于顶层硅上方的栅极结构，该栅极结构包括：栅极，以及位于栅极两侧顶层硅中的源区和漏区；覆盖所述顶层硅、所述栅极结构以及所述侧壁的层间电介质层；位于所述凹陷区域上方并贯穿所述层间电介质层和所述顶层硅的孔；填充所述凹陷区域的石墨层以及填充所述孔的石墨柱。根据本发明有利于抑制SOI结构的浮体效应。

Figure 201810343686

The invention discloses an SOI substrate, a semiconductor device and a forming method thereof. The semiconductor device comprises: an SOI substrate, a recessed area is present on the contact surface of the top layer silicon and the oxide layer of the SOI substrate, the recessed area is located in the active area; an isolation structure is located in the top layer silicon; a gate is located above the top layer silicon a gate structure, the gate structure includes: a gate, and a source region and a drain region located in the top silicon on both sides of the gate; an interlayer dielectric layer covering the top silicon, the gate structure and the sidewalls; a hole over the recessed region and extending through the interlayer dielectric layer and the top layer silicon; a graphite layer filling the recessed region and a graphite pillar filling the hole. According to the present invention, it is advantageous to suppress the floating body effect of the SOI structure.

Figure 201810343686

Description

SOI substrate, semiconductor device and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an SOI substrate, a semiconductor device, and a method for forming the same.
Background
SOI is known as Silicon-On-Insulator, i.e., a Silicon-On-Insulator, technique in which an oxide layer is introduced between a top Silicon layer and a bottom Silicon layer. Compared with a bulk silicon substrate and the like, the SOI substrate has the following advantages in device performance: reduced parasitic capacitance, lower power consumption, eliminated latch-up, suppressed pulse current interference of the substrate, etc. Fig. 1 shows a common SOI structure comprising a bottom silicon layer 101, an oxide layer 102 and a top silicon layer 103.
SOI structures also have their own drawbacks, such as the floating body effect of SOI structures. According to the thickness of the top layer silicon and the maximum depletion layer width X below the channel position under the grid electrode when the device worksdmaxIn relation to (3), SOI devices can be classified into Fully Depleted Silicon On Insulator (FDSOI) devices and Partially Depleted Silicon On Insulator (PDSOI) devices. For thick film partially depleted SOI devices, the top silicon thickness is greater than 2XdmaxThe top silicon layer is in an electrically floating state relative to the bottom silicon layer due to the isolation of the oxide layer, and the floating body structure can bring significant influence on the device characteristics, which is called as a floating body effect. Floating body effects are a particular problem for SOI devices and can cause warpage effects, parasitic bipolar transistor effects, abnormal sub-threshold tilt, threshold voltage drift of the device, and the like. The floating body effect can not only reduce the gain of the device and cause the unstable operation of the device, but also reduce the leakage breakdown voltage and cause the latch-up effect of a single tube, thereby bringing about larger off-state leakage current and increasing the power consumption. These all limit the application of the device in the circuit, especially making the design of the speed and power consumption compromise becomeIt is more difficult.
Disclosure of Invention
The invention aims to solve the problems that: the floating body effect of the SOI structure is suppressed.
In order to solve the above-described problems, according to an aspect of the present invention, there is provided a method of forming an SOI substrate, including: providing a first silicon substrate having a buried hydrogen implant layer; etching the first surface of the first silicon substrate to form a concave region, wherein the concave region is positioned in the active region, and the etching does not reach the hydrogen injection layer; bonding the first surface of the first silicon substrate and the surface of an oxide layer of a second silicon substrate, wherein the second silicon substrate comprises a bottom silicon layer and the oxide layer positioned above the bottom silicon layer; and performing annealing operation on the hydrogen injection layer to strip the silicon layer on the non-bonded side of the first silicon substrate, wherein the silicon layer on the side bonded with the surface of the oxide layer of the second silicon substrate in the first silicon substrate is used as the top silicon of the SOI substrate.
Optionally, providing the first silicon substrate comprises: providing a first silicon wafer; and at room temperature, implanting hydrogen ions into the first surface of the first silicon wafer to form the first silicon substrate with a buried hydrogen implantation layer, wherein the first surface of the first silicon wafer is the first surface of the first silicon substrate.
Optionally, before implanting hydrogen ions into the first surface of the first silicon wafer, the method further comprises: and carrying out thermal oxidation on the first surface of the first silicon wafer at room temperature to form an oxide layer on the first surface of the first silicon wafer.
Optionally, before the bonding, the method further comprises: providing a second silicon wafer; and carrying out thermal oxidation on the upper surface of the second silicon wafer at room temperature so as to form the oxide layer on the upper surface of the second silicon wafer.
Optionally, after the peeling, the method further comprises: and performing high-temperature annealing operation on the bonding contact surface to enhance the bonding strength of the first silicon substrate and the second silicon substrate.
Optionally, after the peeling, the method further comprises: and growing an epitaxial layer on the exposed surface after stripping to increase the thickness of the top silicon.
Optionally, in the formed SOI substrate, the overall thickness of the top silicon is 1.5um to 10um, and the thickness of the silicon layer located above the recess region is more than 1 um.
Optionally, the SOI substrate is formed, wherein the overall thickness of the top silicon is 100nm to 500nm, and the depth of the recessed region is 1nm to 10 nm.
According to another aspect of the present invention, there is provided an SOI substrate including: a bottom silicon layer; an oxide layer over the bottom silicon layer; and the top layer silicon is positioned above the oxide layer, a concave area is arranged on the contact surface of the top layer silicon and the oxide layer, and the concave area is positioned in the active area.
Optionally, the overall thickness of the top layer silicon is 1.5um to 10um, wherein the thickness of the silicon layer above the recess region is more than 1 um.
Optionally, the overall thickness of the top silicon layer is 100nm to 500nm, and the depth of the recessed region is 1nm to 10 nm.
According to another aspect of the present invention, there is provided a method of forming a semiconductor device, including: providing an SOI substrate as described above; forming an isolation structure in the top silicon layer to isolate the active region; forming a gate structure, the gate structure comprising: a grid electrode above the top layer silicon, and a source region and a drain region which are positioned in the top layer silicon at two sides of the grid electrode; forming an interlayer dielectric layer covering the top silicon and the gate structure; forming a hole penetrating through the interlayer dielectric layer and the top silicon layer above the recessed region, wherein the hole is at least positioned between the gate structure and one of the two adjacent isolation structures; forming a graphite layer in the recessed region and forming graphite columns in the pores.
Optionally, at least two of the holes are arranged between each gate structure and the adjacent isolation structure.
Optionally, the graphite layer and the graphite columns are prepared using a chemical vapor deposition or atomic layer deposition process.
According to another aspect of the present invention, there is provided a semiconductor device including: the SOI substrate as described above; an isolation structure in the top silicon to isolate the active region; a gate structure located over the top silicon, the gate structure comprising: a grid electrode above the top layer silicon, and a source region and a drain region which are positioned in the top layer silicon at two sides of the grid electrode; an interlayer dielectric layer covering the top silicon and the gate structure; a hole located above the recessed region and penetrating through the interlayer dielectric layer and the top silicon layer, wherein the hole is at least located between the gate structure and one of the two adjacent isolation structures; a graphite layer filling the recessed region and a graphite column filling the hole.
Optionally, at least two of the holes are arranged between each gate structure and the adjacent isolation structure.
The invention has the following advantages:
according to the SOI substrate obtained by the invention, the recessed region exists on the contact surface of the top layer silicon and the oxide layer, so that the graphite material is filled in the recessed region to absorb electrons/holes accumulated in the floating body and lead out the electrons/holes in the subsequent process of forming the semiconductor device, thereby inhibiting the floating body effect of the SOI device;
according to the semiconductor device obtained by the present invention, with the above-mentioned specific structure of the SOI substrate, holes are punched from the surface of the semiconductor device and passed to the recessed region, and a graphite material is formed in the holes and the recessed region to conduct electrons/holes accumulated in the floating body, thereby suppressing the floating body effect of the SOI device.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
Fig. 1 is a prior art SOI structure.
Fig. 2 is a flow chart of a method of forming an SOI substrate according to one embodiment of the present invention.
Fig. 3(a) -3 (E) are schematic cross-sectional views of an SOI structure at various stages in the formation thereof, respectively, in accordance with one embodiment of the present invention.
Fig. 4 is a flow chart of a method of forming a semiconductor device according to one embodiment of the invention.
Fig. 5(a) -5 (E) are schematic cross-sectional views of a semiconductor device at various stages in the formation process, respectively, in accordance with an embodiment of the present invention.
Detailed Description
As previously described, in thick film partially depleted SOI devices, the top silicon layer is electrically floating relative to the bottom silicon layer due to the isolation of the oxide layer, creating a floating body effect that affects the device performance.
In view of the above, the present invention provides an improved SOI structure, and a semiconductor device and method of forming the same.
The SOI substrate comprises a bottom silicon layer, an oxide layer positioned above the bottom silicon layer and a top silicon positioned above the oxide layer, wherein a concave region is arranged on the contact surface of the top silicon and the oxide layer, and the concave region is positioned in an active region, so that in the process of forming a semiconductor device, the concave region is filled with graphite materials to absorb electrons/holes accumulated in a floating body and lead out, and the floating body effect of the SOI device is restrained.
A semiconductor device according to an embodiment of the present invention includes: the SOI substrate as described above, an isolation structure in the top silicon to isolate the active region, a gate structure over the top silicon, the gate structure comprising: the gate structure comprises a gate above the top layer silicon, a source region and a drain region which are positioned in the top layer silicon at two sides of the gate, an interlayer dielectric layer covering the top layer silicon and the gate structure, and a hole which is positioned above the depressed region and penetrates through the interlayer dielectric layer and the top layer silicon, wherein the hole is at least positioned between the gate structure and one of the two adjacent isolation structures, a graphite layer filling the depressed region and a graphite column filling the hole. The graphite layer and the graphite column can lead out electrons/holes accumulated in the floating body, so that the floating body effect of the SOI device is suppressed. For example, for nMOSFET prepared based on the SOI substrate, the graphite layer and the graphite column can lead out holes accumulated in the floating body so as to inhibit SOI floating body effect; for pMOSFET prepared based on the SOI substrate, the graphite layer and the graphite column can lead out electrons accumulated in the floating body so as to inhibit SOI floating body effect.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be taken as a general scale, and the drawings are for illustrative purposes only and should not be taken as limiting the scope of the present invention. In addition, the three-dimensional space size of length, width and depth should be included in the actual manufacturing.
Fig. 2 is a flow chart of a method of forming an SOI substrate according to one embodiment of the present invention. Fig. 3(a) -3 (E) are schematic cross-sectional views of an SOI structure at various stages in the formation thereof, respectively, in accordance with one embodiment of the present invention. A method of forming an SOI substrate according to the present invention and a structure thereof will be described below with reference to fig. 2 and fig. 3(a) to 3 (E).
Referring to fig. 3(a), step 21, a first silicon substrate 1 is provided, the first silicon substrate 1 having a buried hydrogen implant layer 302.
In one possible implementation, providing the first silicon substrate 1 may include: providing a first silicon wafer, and implanting hydrogen ions into a first surface of the first silicon wafer at room temperature to form a first silicon substrate 1 with the hydrogen implantation layer 302 buried therein, where the first surface of the first silicon wafer is the first surface of the first silicon substrate 1. An amount of H can be implanted into the first silicon wafer at an energy+Particles in the formation of buried H-rich+A hydrogen implanted layer 302 of particles. The thickness and H of the silicon layer 303 between the first surface of the first silicon substrate 1 and the hydrogen implantation layer 302+Related to the implantation energy, H+The greater the implantation energy, H+The deeper the implant peak, the thicker the thickness of the silicon layer 303. The thickness of the silicon layer 303 may be set as desired.
In one example, before implanting hydrogen ions into the first surface of the first silicon wafer, the first surface of the first silicon wafer may be thermally oxidized at room temperature to form an oxide layer on the first surface of the first silicon wafer.
Referring to fig. 3(B), in step 22, the first surface of the first silicon substrate 1 is etched to form a recess region 304, the recess region 304 is located in the active region, and the etching does not reach the hydrogen injection layer 302.
Etching the first surface of the first silicon substrate 1 to form the recess region may include: forming a mask on a first surface of the first silicon substrate 1 to define the shape and size of the recess region 304; etching the first surface of the first silicon substrate 1 by using the mask as an etching barrier layer to form the recessed region 304; the mask is removed.
In one example, the recessed region 304 is as large as the active region; in another example, the recessed region 304 is smaller than the active region.
Fig. 3(B) is a cross-sectional view of the first silicon substrate 1 after etching.
Referring to fig. 3(C), step 23, bonding the first surface of the first silicon substrate 1 and an oxide layer surface of a second silicon substrate 2, where the second silicon substrate 2 includes a bottom silicon layer 401 and an oxide layer 402 located above the bottom silicon layer 401.
The second silicon substrate includes a bottom silicon layer 401 and an oxide layer 402. The second silicon substrate 2 can be obtained by: and performing thermal oxidation on the upper surface of the second silicon wafer at room temperature to form an oxide layer 402 on the upper surface of the second silicon wafer, thereby obtaining the second silicon substrate 2.
Before bonding, the first surface of the first silicon substrate and the surface of the oxide layer of the second silicon substrate to be bonded may be cleaned and activated. RCA cleaning, such as RCA1 (standard No. 1 solution), RCA2 (standard No. 2 solution) or their mixture, can be selected as required for bonding the surfacesAnd (5) cleaning. Before bonding and after cleaning, N can also be used+The plasma activates the surface to be bonded to increase the dangling bonds on the surface and activate the surface, which is more beneficial to enhancing the bonding strength. In one example, the activation time may be set to 30 seconds.
Fig. 3(D) is a cross-sectional view of the bonded structure.
Referring to fig. 3(E), step 24, an annealing operation is performed on the hydrogen implanted layer 302 in fig. 3(D) to strip the silicon layer 301 on the non-bonded side of the first silicon substrate 1, and the silicon layer 303 on the bonded side of the first silicon substrate 1 with the oxide layer surface 402 of the second silicon substrate 2 serves as the top silicon of the SOI substrate.
Performing an annealing operation on the hydrogen implanted layer 302 to peel off the silicon layer 301 on the non-bonded side of the first silicon substrate 1 may include: a low-temperature annealing operation is performed on the hydrogen implanted layer 302 so that hydrogen ions form bubbles to peel off the silicon layer 301 on the non-bonded side of the first silicon substrate 1.
In one example, after the silicon layer 301 is stripped, a high temperature annealing operation may be performed on the bonding interface to enhance the bonding strength of the first silicon substrate 1 and the second silicon substrate 2.
In one example, after the silicon layer 301 is stripped, the exposed surface of the stripped silicon layer 303 may be polished using a chemical mechanical polishing process (i.e., CMP) to planarize the surface.
The silicon layer 303 on the side of the first silicon substrate 1 bonded to the surface of the oxide layer 402 of the second silicon substrate 2 may be used as the top silicon of the SOI substrate. In one example, an epitaxial layer may be grown on the exposed surface after lift-off to increase the thickness of the top silicon 303 to ultimately form the desired SOI substrate.
As shown in fig. 3(E), the SOI substrate includes a bottom silicon layer 401, an oxide layer 402 located above the bottom silicon layer 401, and a top silicon 303 located above the oxide layer 402, where a recessed region 304 is located at a contact surface of the top silicon 303 and the oxide layer 401, and the recessed region 304 is located in an active region.
The thickness of the top silicon 303 in fig. 3(E) may be determined according to device specifications. In, for example, TM + Epi SOI, the top layer silicon 303 has an overall thickness of 1.5um to 10um, with the silicon layer above the recessed region having a thickness of 1um or more. In one example, the thickness of the corresponding silicon layer in the first silicon substrate 1 may be slightly larger than that of the top silicon, and the top silicon 303 with the overall thickness in the above range (1.5um to 10um) is directly obtained after bonding and/or polishing loss. In another example, the thickness of the corresponding silicon layer of the first silicon substrate 1 is greater than 1um but not as thick as the required thickness of the top silicon 303, and then epitaxial growth may be performed on the exposed surface after lift-off to make the top silicon 303 to the required thickness.
In the case of, for example, TM-SOI, the top silicon 303 in fig. 3(E) has an overall thickness of 100nm to 500nm, and the depth of the recess region is 1nm to 10 nm. In this case, it is generally not necessary to perform epitaxial growth of the top silicon after lift-off.
Fig. 4 is a flow chart of a method of forming a semiconductor device according to an embodiment of the present invention. Fig. 5(a) -5 (E) are schematic cross-sectional views of a semiconductor device at various stages in the formation process, respectively, in accordance with an embodiment of the present invention. A method of forming a semiconductor device according to the present invention and a structure thereof are described below with reference to fig. 4 and fig. 5(a) to 5 (E).
Referring to fig. 5(a), step 41, an SOI substrate as described above is provided, for example, an SOI substrate as shown in fig. 3 (E).
Step 42, forming an isolation structure 501 in the top silicon 303 to isolate the active region.
For example, isolation trenches may be formed in the top silicon layer and filled with an insulating material to form the isolation structures 501.
Referring to fig. 5(B), step 43, a gate structure is formed, the gate structure comprising: a grid electrode above the top layer silicon, and a source region 504 and a drain region 505 which are positioned in the top layer silicon on two sides of the grid electrode.
Shown in fig. 5(B) is a gate oxide layer 503 and a polysilicon gate 502 over the gate oxide layer 503. The gate electrode required for the semiconductor device can be formed by photolithography and etching.
The Source region 504 and the Drain region 505 can be formed in the top silicon layer on both sides of the gate by a Low Dose Drain (LDD) process and Source/Drain Implantation (S/D IMP). Region 506 in fig. 5(B) is a lightly doped (LDD) region.
Spacers (spacers) 507 may be formed over the top silicon 303 on both sides of the gate after the LDD process and before the S/D IMP. Spacer 507 protects polysilicon gate 502 and by adjusting the thickness of Spacer 507, the distance from Source/Drain implant region to polysilicon gate 502 can be determined.
In one example, a Salicide (Salicide) layer may be formed over the source, drain, and gate structures; in another example, a salicide layer may not be formed over the source, drain, and gate structures.
Referring to fig. 5(C), in step 44, an Inter-Layer Dielectric (ILD) Layer 508 is formed to cover the top silicon 303 and the gate structure.
The inter-level dielectric layer 508 may be used to isolate the front end of the process from the back end of the process. The inter-level dielectric layer 508 protects the devices and structures formed by the front-end and reduces the parasitic effects between the back-end metal and the front-end. The interlevel dielectric layer 508 may be planarized to provide a flat, stable surface for the back end of the process.
Referring to fig. 5(D), step 45, a hole 509 is formed through the interlayer dielectric layer 508 and the top silicon 303 above the recess region 304, wherein the hole 509 is at least located between the gate structure and one of the two adjacent isolation structures 501.
Referring to fig. 5(E), step 46, graphite layers are formed in the recessed regions 304 and graphite columns are formed in the holes 509.
In one example, the graphite layers and the graphite pillars may be prepared using a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process.
As described earlier, the graphite layer and the graphite columns can float accumulated electrons/holes in the body, thereby suppressing the floating body effect of the SOI device.
In one example, there are at least two of the holes 509 between each of the gate structures and the adjacent isolation structure 501. Since graphite is a material having high thermal conductivity, increasing the contact area of the graphite material with air by increasing the number of the holes 509 can promote heat exchange and accelerate the release of heat in the top silicon 303.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming an SOI substrate, comprising:
providing a first silicon substrate having a buried hydrogen implant layer;
etching the first surface of the first silicon substrate to form a recessed region, wherein the recessed region is located in an active region, the size of the first silicon substrate opposite to the bottom of the recessed region at least can surround an MOS (metal oxide semiconductor) tube, and at least one hole which is filled with graphite materials is formed in the recessed region at the periphery of the MOS tube, and the etching does not reach the hydrogen injection layer;
bonding the first surface of the first silicon substrate and the surface of an oxide layer of a second silicon substrate, wherein the second silicon substrate comprises a bottom silicon layer and the oxide layer positioned above the bottom silicon layer;
and performing annealing operation on the hydrogen injection layer to strip the silicon layer on the non-bonded side of the first silicon substrate, wherein the silicon layer on the side bonded with the surface of the oxide layer of the second silicon substrate in the first silicon substrate is used as the top silicon of the SOI substrate.
2. The method of forming of claim 1, wherein providing the first silicon substrate comprises:
providing a first silicon wafer;
and at room temperature, implanting hydrogen ions into the first surface of the first silicon wafer to form the first silicon substrate with a buried hydrogen implantation layer, wherein the first surface of the first silicon wafer is the first surface of the first silicon substrate.
3. The method of claim 2, further comprising, prior to implanting hydrogen ions into the first surface of the first silicon wafer:
and carrying out thermal oxidation on the first surface of the first silicon wafer at room temperature to form an oxide layer on the first surface of the first silicon wafer.
4. The method of forming as claimed in claim 1, further comprising, prior to bonding:
providing a second silicon wafer;
and carrying out thermal oxidation on the upper surface of the second silicon wafer at room temperature so as to form the oxide layer on the upper surface of the second silicon wafer.
5. The method of forming as claimed in claim 1, further comprising, after the peeling:
and performing high-temperature annealing operation on the bonding contact surface to enhance the bonding strength of the first silicon substrate and the second silicon substrate.
6. The method of forming as claimed in claim 1, further comprising, after the peeling:
and growing an epitaxial layer on the exposed surface after stripping to increase the thickness of the top silicon.
7. The method as claimed in claim 1 or 6, wherein the SOI substrate is formed, wherein the top silicon has an overall thickness of 1.5um to 10um, and the silicon layer above the recess region has a thickness of 1um or more.
8. The method of claim 1, wherein the SOI substrate is formed such that the top silicon has an overall thickness of 100nm to 500nm and the recess region has a depth of 1nm to 10 nm.
9. An SOI substrate, comprising:
a bottom silicon layer;
an oxide layer over the bottom silicon layer;
the top silicon is located the top silicon of oxide layer top, top silicon with there is the depressed area on the contact surface of oxide layer, the depressed area is located active area, and with the depressed area is relative the size of top silicon can surround a MOS pipe at least and MOS pipe periphery can to at least one hole of graphite material is filled to the depressed area.
10. The SOI substrate of claim 9, wherein:
the whole thickness of top silicon is 1.5um ~ 10um, wherein, is located the silicon layer thickness of depressed area top is more than 1 um.
11. The SOI substrate of claim 9, wherein:
the overall thickness of the top layer silicon is 100 nm-500 nm, and the depth of the depressed area is 1 nm-10 nm.
12. A method of forming a semiconductor device, comprising:
providing an SOI substrate as defined in any one of claims 9-11;
forming an isolation structure in the top silicon layer to isolate the active region;
forming a gate structure, the gate structure comprising: a grid electrode above the top layer silicon, and a source region and a drain region which are positioned in the top layer silicon at two sides of the grid electrode;
forming an interlayer dielectric layer covering the top silicon and the gate structure;
forming a hole penetrating through the interlayer dielectric layer and the top silicon layer above the recessed region, wherein the hole is at least positioned between the gate structure and one of the two adjacent isolation structures;
forming a graphite layer in the recessed region and forming graphite columns in the pores.
13. The method of claim 12, wherein each gate structure has at least two holes between it and an adjacent isolation structure.
14. The method of forming as claimed in claim 12, wherein the graphite layers and the graphite pillars are prepared using a chemical vapor deposition or atomic layer deposition process.
15. A semiconductor device, comprising:
an SOI substrate as defined in any one of claims 9-11;
an isolation structure in the top silicon to isolate the active region;
a gate structure located over the top silicon, the gate structure comprising: a grid electrode above the top layer silicon, and a source region and a drain region which are positioned in the top layer silicon at two sides of the grid electrode;
an interlayer dielectric layer covering the top silicon and the gate structure;
a hole located above the recessed region and penetrating through the interlayer dielectric layer and the top silicon layer, wherein the hole is at least located between the gate structure and one of the two adjacent isolation structures;
a graphite layer filling the recessed region and a graphite column filling the hole.
16. The semiconductor device of claim 15, wherein each gate structure has at least two of the holes between it and an adjacent isolation structure.
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