CN108682675A - A kind of flash memory and its manufacturing method - Google Patents
A kind of flash memory and its manufacturing method Download PDFInfo
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- CN108682675A CN108682675A CN201710208700.3A CN201710208700A CN108682675A CN 108682675 A CN108682675 A CN 108682675A CN 201710208700 A CN201710208700 A CN 201710208700A CN 108682675 A CN108682675 A CN 108682675A
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- 230000015654 memory Effects 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000011810 insulating material Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
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- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 30
- 238000010586 diagram Methods 0.000 description 12
- 238000003860 storage Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
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- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The embodiment of the invention discloses a kind of flash memory and its manufacturing methods, are related to technical field of memory, and wherein method includes：Semi-conductive substrate is provided, semiconductor substrate has spaced isolated area and active area, insulating materials is filled in isolated area；The first groove is formed in active area between arbitrary two neighboring isolated area；It grows tunnel oxide successively in the first groove and forms floating boom.Flash memory disclosed by the embodiments of the present invention and its manufacturing method, floating boom is formed in the first groove of active area, the contact area of floating boom and active area is set to increase, current channel length increases, to make the current density of flash cell and the current practice width of read-write increase, so that the read-write number of flash cell increases, operational efficiency is improved；In addition, during subsequently carrying out source area etching, no longer etch floating boom and tunnel oxide weakens photoresist remnants phenomenons, the reliability of flash memory is made to be improved to reduce the depth-to-width ratio of etching.
Description
Technical field
The present embodiments relate to technical field of memory more particularly to a kind of flash memory and its manufacturing methods.
Background technology
Flash memory is a kind of floating gate type memory part, is widely used in various industries, the active area of flash memory and floating boom
Contact area directly determines the size of the current density of storage unit.
With the development of flash memory processing procedure technology, the active area of continuous micro storage unit is to obtain the unit plane of bigger
Product storage density, but therefore the current density of storage unit also reduces with continuous, the electric current behaviour for causing storage unit to be read and write
Become smaller as width, read-write number reduces, and the reliability of storage unit reduces.In addition, in prior art, needed when forming source electrode
The depth-to-width ratio for the groove that perform etching, but be etched to source area is very high, causes the photoresist in source electrode etching process remaining
Hen Nan Cheongju are clean, and these remaining photoresists can hinder subsequent source ion to inject, and source area is caused to remain photoresist
Memory cell current is relatively low, and the inhomogeneities of this memory cell current distribution will seriously affect the operational efficiency of flash memory and reliable
Property.
It to be solved is asked in view of the above-mentioned problems, providing a kind of flash memory with high operational efficiency and high reliability and becoming one
Topic.
Invention content
A kind of flash memory of offer of the embodiment of the present invention and its manufacturing method, to solve the operational efficiency and reliability of existing flash memory
Low problem.
In a first aspect, an embodiment of the present invention provides a kind of manufacturing methods of flash memory, including：Semi-conductive substrate is provided,
The semiconductor substrate has spaced isolated area and active area, and insulating materials is filled in the isolated area；Arbitrary
The first groove is formed in the active area between the two neighboring isolated area；Tunnelling is grown successively in first groove
Oxide layer and formation floating boom.
Optionally, in the manufacturing method of above-mentioned flash memory, the cross sectional shape of first groove be semicircle, half elliptic,
Rectangle is trapezoidal, and the plane where the section is vertical with the upper surface of the semiconductor substrate.
Optionally, in the manufacturing method of above-mentioned flash memory, the folder of the side wall of first groove and first groove floor
Angle is fillet.
Optionally, in the manufacturing method of above-mentioned flash memory, the depth of first groove is
Optionally, in the manufacturing method of above-mentioned flash memory, it is described grown successively in first groove tunnel oxide with
And formed after floating boom, including：Insulating layer and control gate are sequentially formed, on the direction of the semiconductor substrate, institute
It states insulating layer and covers the isolated area and the floating boom, the control gate covers the insulating layer.
Optionally, described to sequentially form insulating layer and control gate includes in the manufacturing method of above-mentioned flash memory：It is filling
The surface for stating the isolated area of megohmite insulant forms the second groove；Sequentially form the insulating layer and the control gate.
Optionally, in the manufacturing method of above-mentioned flash memory, the insulating layer include stack gradually the first oxide skin(coating) to be formed,
Nitride layer and the second oxide skin(coating).
Optionally, in the manufacturing method of above-mentioned flash memory, the insulating materials is silica.
Optionally, in the manufacturing method of above-mentioned flash memory, it is described sequentially formed in first groove tunnel oxide and
After floating boom, further include：Planarization process is carried out to the floating boom, makes the flush of itself and the active area.
Second aspect, the embodiment of the present invention additionally provide a kind of flash memory, including：Semiconductor substrate, the semiconductor substrate
With spaced isolated area and active area, insulating materials is filled in the isolated area；First groove is formed in arbitrary phase
In the active area between two adjacent isolated areas；Tunnel oxide is covered in the surface of first groove；It is floating
Grid are formed in first groove, are covered on the tunnel oxide.
An embodiment of the present invention provides flash memory and its manufacturing methods, provide semi-conductive substrate, and semiconductor substrate first
With spaced isolated area and active area, insulating materials is filled in isolated area；Secondly in arbitrary two neighboring isolated area
Between active area in form the first groove；Then tunnel oxide is sequentially formed in the first groove and forms floating boom.This
By the way that floating boom to be formed in the first groove of active area in inventive embodiments, on the one hand so that the contact surface of floating boom and active area
Product increases, and current channel length increases, to make the current density of flash cell and the current practice width of read-write increase, most
Eventually so that the read-write number of flash cell increases, operational efficiency is improved；On the other hand so that subsequently carrying out source area quarter
During erosion, it is no longer necessary to etch floating boom and tunnel oxide, to reduce the depth-to-width ratio of etching groove, weaken photoresist
Remaining phenomenon so that the reliability of flash memory is improved；In addition the possibility contacted between floating boom is also eliminated, for subsequently into one
Step reduces flash memory size and creates condition.
Description of the drawings
Fig. 1 is a kind of flow diagram of the manufacturing method for flash memory that the embodiment of the present invention one provides；
Fig. 2A -2C are structural profile illustrations corresponding with each step of manufacturing method of a kind of flash memory in Fig. 1；
Fig. 3 A are a kind of cross-sectional views of first groove provided in an embodiment of the present invention；
Fig. 3 B are the enlarged diagrams of the regional area A in Fig. 3 A；
Fig. 4 is a kind of flow diagram of the manufacturing method of flash memory provided by Embodiment 2 of the present invention；
Fig. 5 is a kind of structural schematic diagram of flash memory provided by Embodiment 2 of the present invention；
Fig. 6 A be flash memory in Fig. 5 after forming control gate along the cross-sectional view of hatching A-A'；
Fig. 6 B be flash memory in Fig. 5 after forming control gate along the cross-sectional view of hatching B-B'；
Fig. 7 is a kind of cross-sectional view of the flash memory provided in the embodiment of the present invention；
Fig. 8 is a kind of structural schematic diagram of the flash memory provided in the embodiment of the present invention three.
Specific implementation mode
The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this
The described specific embodiment in place is used only for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition also
It should be noted that illustrating only for ease of description, in attached drawing and the relevant part of the embodiment of the present invention rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of flow diagram of the manufacturing method for flash memory that the embodiment of the present invention one provides, and Fig. 2A -2C are and figure
A kind of corresponding structural profile illustration of each step of the manufacturing method of flash memory in 1.With reference to figure 1, provided in the present embodiment
The manufacturing method of flash memory specifically comprise the following steps：
Step 110 provides semi-conductive substrate, and semiconductor substrate has spaced isolated area and active area, isolation
Insulating materials is filled in area.With reference to figure 2A, semiconductor substrate 11 have spaced isolated area 111, isolated area 111 it
Between be active area.Megohmite insulant is filled in isolated area 111, for separating active area to limit the range of active area.
The first groove is formed in step 120, the active area between arbitrary two neighboring isolated area.With reference to figure 2B, in phase
The first groove 112 is formed in active area between adjacent two isolated areas 111, two isolated areas are only schematically drawn in Fig. 2 B
111 and first groove 112.The depth and shape of first groove 112 need according to actual needs to determine, such as after
Thickness and the thickness of shape and tunnel oxide of continuous floating boom to be formed etc. design the depth and shape of the first groove 112
Shape.
Step 130 grows tunnel oxide in the first groove and forms floating boom successively.In conjunction with Fig. 2 B and Fig. 2 C,
It is initially formed tunnel oxide 12 in first groove 112, then forms floating boom 13 on tunnel oxide 12.It can be with from Fig. 2 C
Find out and floating boom 13 is formed in the first groove 112 so that the contact area of floating boom 13 and active area increases, current channel length
Increase, to make the current density of flash cell and the current practice width of storage unit read-write increase, finally so that flash memory
Read-write number increase, reliability enhancing.It should be noted that insulating layer and control gate can also be formed in the top of floating boom 13
And other belong to the component part of flash memory, do not specifically describe herein.
An embodiment of the present invention provides a kind of manufacturing methods of flash memory, provide semi-conductive substrate first, and semiconductor serves as a contrast
Bottom has spaced isolated area and active area, and insulating materials is filled in isolated area；Then in arbitrary two neighboring isolation
The first groove is formed in active area between area；Then tunnel oxide is sequentially formed in the first groove and forms floating boom.
By the way that floating boom to be formed in the first groove of active area in the embodiment of the present invention, on the one hand so that contact of the floating boom with active area
Area increases, and current channel length increases, to make the current density of flash cell and the current practice width of read-write increase,
Final that the read-write number of flash cell is increased, operational efficiency is improved；On the other hand so that subsequently carrying out source area
During etching, it is no longer necessary to etch floating boom and tunnel oxide, to reduce the depth-to-width ratio of etching groove, weaken light
The remaining phenomenon of resistance so that the reliability of flash memory is improved；In addition also eliminate the possibility contacted between floating boom, for subsequently into
One step reduces flash memory size and creates condition.
Optionally, on the basis of the above embodiments, the cross sectional shape of the first groove 112 is semicircle, half elliptic, length
Rectangular or trapezoidal, the plane where section is vertical with the upper surface of semiconductor substrate 11.Specifically, Fig. 3 A are the embodiment of the present invention
A kind of cross-sectional view of first groove provided, with reference to figure 3A, the cross sectional shape of the first groove 112 is trapezoidal；With reference to
The cross sectional shape of Fig. 2 B, the first groove 112 are rectangle.For the cross sectional shape of the first groove 112 it is rectangular in Fig. 2 B and Fig. 3 A
Shape and it is trapezoidal when structural schematic diagram；The case where cross sectional shape for the first groove 112 is semicircle and half elliptic, can join
Structural schematic diagram when cross sectional shape is rectangle and is trapezoidal is examined, is no longer drawn herein.When forming the first groove 112, by first
The shape processing of groove 112 is variously-shaped, to meet different structure design demands.
Optionally, on the basis of the above embodiments, the angle of the side wall of the first groove 112 and first groove floor
For fillet.Fig. 3 B are the enlarged diagrams of the regional area A in Fig. 3 A, with reference to figure 3B, the side wall of the first groove 112 and described the
The angle of one groove floor is fillet 1121, can reduce the stress concentration phenomenon of angle so that substrate 11 is using process
In be not easy to crack, increase the reliability of flash memory.
Optionally, on the basis of the above embodiments, the depth of the first groove 112 isBy the first groove
112 are designed as certain depth, and floating boom and tunnel oxide are formed in slot so that in the mistake for carrying out control gate and source electrode etching
Cheng Zhong need not etch floating boom and tunnel oxide, weaken photoresist remnants phenomenons to reduce etching depth, in the present embodiment
In preferably set the depth of the first groove 112 to
Embodiment two
Fig. 4 is a kind of flow diagram of the manufacturing method of flash memory provided by Embodiment 2 of the present invention.With reference to figure 4, upper
It is described to grow tunnel oxide successively in first groove and formed after floating boom on the basis of stating embodiment, may be used also
To include：Insulating layer and control gate are sequentially formed, on the direction of the semiconductor substrate, the insulating layer covers institute
Isolated area and the floating boom are stated, the control gate covers the insulating layer.
It should be noted that following step 210,220,230 and step 110,120, the 130 corresponding phases in embodiment one
Together, step 210,220,230 are equally applicable to the associated description of step 110,120,130.
With reference to figure 4, the manufacturing method of the flash memory in the embodiment of the present invention specifically comprises the following steps：
Step 210 provides semi-conductive substrate, and semiconductor substrate has spaced isolated area and active area, isolation
Insulating materials is filled in area.
The first groove is formed in step 220, the active area between arbitrary two neighboring isolated area.Illustratively, it refers to
Fig. 2 B in embodiment one, it is preferred to use wet etching and dry etch process etch having between two neighboring isolated area 111
Source region, to form the first groove 112.
Step 230 grows tunnel oxide in the first groove and forms floating boom successively.Illustratively, reference implementation
Fig. 2 C in example one, used in the first groove 112 wet process oxidation technology or moisture-generation process in situ formed thickness forTunnel oxide 12, then in the first groove 112 using low-pressure chemical vapor deposition process formed floating boom
13.After forming floating boom 13, the flush of itself and isolated area 111 is made using chemical mechanical milling tech grinding floating boom 13, with
Continue after an action of the bowels and forms insulating layer above it.
Step 240 sequentially forms insulating layer and control gate, on the direction perpendicular to semiconductor substrate, insulating layer covering
Isolated area and floating boom, control gate cover insulating layer.Fig. 5 is a kind of structural schematic diagram of flash memory provided by Embodiment 2 of the present invention,
With reference to figure 5, which includes control gate 25 and active area 26, and active area 26 includes drain region 261, source area 262 and grid
Polar region 263.
Fig. 6 A be flash memory in Fig. 5 after forming control gate along the cross-sectional view of hatching A-A', with reference to figure 6A,
On the direction of semiconductor substrate 21, tunnel oxide 22 and floating boom 23, isolated area are being formed on gate regions 263
211 and floating boom 23 on be formed with insulating layer 24, control gate 25 is formed on insulating layer 24.Fig. 6 B are that the flash memory in Fig. 5 is being formed
Along the cross-sectional view of hatching B-B' after control gate, two flash cells are schematically drawn with reference to figure 6B, in figure
Sectional view is formed with tunnel oxide 22 and floating boom 23 on gate regions 263, insulating layer 24, insulating layer is formed on floating boom 23
Control gate 25 is formed on 24.It only needs to etch control gate 25 and insulation from Fig. 6 B it can be seen that at etching source area 262
Layer 24.
In conjunction with Fig. 5-6B, it is located at due to floating boom 23 in first groove of semiconductor substrate 21, is subsequently carrying out source area 262
When etching, floating boom 23 and tunnel oxide 22 need not be etched so that the depth-to-width ratio of the etching groove in etching process reduces, and subtracts
Small photoresist remnants phenomenons.It is buried type additionally, due to floating boom 23, reduces the exposure risk between floating boom 23 so that further
The possibility of micro flash cell improves.
An embodiment of the present invention provides a kind of manufacturing methods of flash memory, grown successively in the first groove tunnel oxide with
And formed after floating boom, insulating layer and control gate are sequentially formed, wherein on the direction perpendicular to semiconductor substrate, insulating layer covers
Lid isolated area and floating boom, control gate cover insulating layer, on the one hand so that the contact area of floating boom and active area increases, current channel
Length increases, to make the current density of flash cell and the current practice width of read-write increase, finally so that flash cell
Read-write number increase, operational efficiency is improved；On the other hand so that subsequently during carrying out source area etching, no longer
Etching floating boom and tunnel oxide is needed to weaken photoresist remnants phenomenons to reduce the depth-to-width ratio of etching groove so as to dodge
The reliability deposited is improved；In addition the possibility contacted between floating boom is also eliminated, subsequently to further reduce flash memory size
Create condition.
Optionally, in other embodiments, described to sequentially form insulating layer and control gate includes：Filled with megohmite insulant
Isolated area surface formed the second groove；Sequentially form insulating layer and control gate.Fig. 7 is one provided in the embodiment of the present invention
The cross-sectional view of kind flash memory, with reference to figure 7, the difference with Fig. 6 A is to be formed with the second groove on the surface of isolated area 211
2111, insulating layer 24 and control gate 25 are formed in the second groove 2111, and 25 He of control gate is increased using the second groove 2111
Coupled ratio between floating boom 23.Illustratively, using one in wet etching and dry etch process removal isolated area 211
Divide megohmite insulant, to form the second groove 2111.
Optionally, on the basis of the above embodiments, insulating layer 24 includes stacking gradually the first oxide skin(coating), the nitrogen to be formed
Compound layer and the second oxide skin(coating).Optionally, on the basis of the above embodiments, the insulating materials is silica.
Optionally, on the basis of the above embodiments, it is described sequentially formed in first groove tunnel oxide and
After floating boom, further include：Planarization process is carried out to the floating boom, makes the flush of itself and the active area.Specifically, ginseng
Fig. 2 C in embodiment one are examined, by carrying out planarization process to floating boom 13, make its flush with active area so that follow-up
Other functional layers, such as insulating layer etc. are more easily formed on floating boom 13.
Embodiment three
Fig. 8 is a kind of structural schematic diagram of the flash memory provided in the embodiment of the present invention three, with reference to figure 8, in above-described embodiment
On the basis of, flash memory provided in this embodiment includes：Semiconductor substrate 81, the first groove 812, tunnel oxide 82 and floating boom
83, the other components of flash memory are not shown in fig. 8.
With reference to figure 8, flash memory provided in this embodiment includes：
Semiconductor substrate 81, the semiconductor substrate 81 have spaced isolated area 811 and active area, the isolation
Insulating materials is filled in area 811；
First groove 812 is formed in the active area between two isolated areas 811 of arbitrary neighborhood；
Tunnel oxide 82 is covered in the surface of the first groove 812；
Floating boom 83 is formed in the first groove 812, is covered on tunnel oxide 82.
An embodiment of the present invention provides a kind of flash memories, provide semi-conductive substrate first, and semiconductor substrate has interval
The isolated area and active area of setting are filled with insulating materials in isolated area；Then having between arbitrary two neighboring isolated area
The first groove is formed in source region；Then tunnel oxide is sequentially formed in the first groove and forms floating boom.The present invention is implemented
By the way that floating boom to be formed in the first groove of active area in example, on the one hand so that the contact area of floating boom and active area increases,
Current channel length increases, final to make to make the current density of flash cell and the current practice width of read-write increase
The read-write number of flash cell increases, and operational efficiency is improved；On the other hand so that subsequently in the mistake for carrying out source area etching
Cheng Zhong, it is no longer necessary to etch floating boom and tunnel oxide, to reduce the depth-to-width ratio of etching groove, it is existing to weaken photoresist remnants
As so that the reliability of flash memory is improved；In addition the possibility contacted between floating boom is also eliminated, subsequently to further reduce
Flash memory size creates condition.
Since the flash memory of the present embodiment can be made by the manufacturing method of the flash memory provided in the various embodiments described above, so can
With the content in reference the various embodiments described above, in order to be easier to understand the structure of the flash memory provided in the present embodiment.
Note that above are only preferred embodiment and the institute's application technology principle of the embodiment of the present invention.Those skilled in the art
It will be appreciated that the embodiment of the present invention is not limited to specific embodiment described here, can carry out for a person skilled in the art each
The protection domain that kind significantly changes, readjusts and substitutes without departing from the embodiment of the present invention.Therefore, although more than passing through
Embodiment is described in further detail the embodiment of the present invention, but the embodiment of the present invention is not limited only to the above implementation
Example can also include other more equivalent embodiments in the case where not departing from design of the embodiment of the present invention, and the present invention is implemented
The range of example is determined by scope of the appended claims.
Claims (10)
1. a kind of manufacturing method of flash memory, which is characterized in that including：
Semi-conductive substrate is provided, the semiconductor substrate has spaced isolated area and active area, in the isolated area
Filled with insulating materials；
The first groove is formed in the active area between the arbitrary two neighboring isolated area；
It grows tunnel oxide successively in first groove and forms floating boom.
2. manufacturing method according to claim 1, which is characterized in that the cross sectional shape of first groove be it is semicircle,
Half elliptic, rectangle or trapezoidal, the plane where the section are vertical with the upper surface of the semiconductor substrate.
3. manufacturing method according to claim 1 or 2, which is characterized in that the side wall of first groove and described first
The angle of groove floor is fillet.
4. manufacturing method according to claim 1, which is characterized in that the depth of first groove is
5. manufacturing method according to claim 1, which is characterized in that described to grow tunnelling successively in first groove
After oxide layer and formation floating boom, including：
Insulating layer and control gate are sequentially formed, described on the direction of the semiconductor substrate, the insulating layer covers
Isolated area and the floating boom, the control gate cover the insulating layer.
6. manufacturing method according to claim 5, which is characterized in that described to sequentially form insulating layer and control gate includes：
The second groove is formed on the surface of the isolated area filled with the megohmite insulant；
Sequentially form the insulating layer and the control gate.
7. according to the method described in claim 6, it is characterized in that, the insulating layer includes stacking gradually the first oxidation to be formed
Nitride layer, nitride layer and the second oxide skin(coating).
8. manufacturing method according to claim 1, which is characterized in that the insulating materials is silica.
9. manufacturing method according to claim 1, which is characterized in that described to sequentially form tunnelling in first groove
After oxide layer and floating boom, further include：
Carrying out planarization process to the floating boom makes the flush of itself and the active area.
10. a kind of flash memory, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate have spaced isolated area and active area, are filled in the isolated area
Insulating materials；
First groove is formed in the active area between two isolated areas of arbitrary neighborhood；
Tunnel oxide is covered in the surface of first groove；
Floating boom is formed in first groove, is covered on the tunnel oxide.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113517296A (en) * | 2020-04-10 | 2021-10-19 | 合肥晶合集成电路股份有限公司 | Nonvolatile memory structure and preparation method thereof |
| CN113517295A (en) * | 2020-04-10 | 2021-10-19 | 合肥晶合集成电路股份有限公司 | A kind of preparation method of non-volatile memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591817A (en) * | 2003-08-15 | 2005-03-09 | 台湾积体电路制造股份有限公司 | Structure of isolation trench and manufacturing method thereof |
| CN1913120A (en) * | 2005-07-26 | 2007-02-14 | 尔必达存储器株式会社 | Method of manufacturing a semiconductor device and the semiconductor device |
| KR20080001272A (en) * | 2006-06-29 | 2008-01-03 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
| CN105990359A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Separating gate type flash memory device and preparation method thereof |
-
2017
- 2017-03-31 CN CN201710208700.3A patent/CN108682675A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591817A (en) * | 2003-08-15 | 2005-03-09 | 台湾积体电路制造股份有限公司 | Structure of isolation trench and manufacturing method thereof |
| CN1913120A (en) * | 2005-07-26 | 2007-02-14 | 尔必达存储器株式会社 | Method of manufacturing a semiconductor device and the semiconductor device |
| KR20080001272A (en) * | 2006-06-29 | 2008-01-03 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
| CN105990359A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Separating gate type flash memory device and preparation method thereof |
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| CN113517296A (en) * | 2020-04-10 | 2021-10-19 | 合肥晶合集成电路股份有限公司 | Nonvolatile memory structure and preparation method thereof |
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