CN108683434A - On piece suitable for permanent envelope non-linear modulation integrates transmitting-receiving matching network and method - Google Patents

Abstract

The present invention provides a kind of integrated transmitting-receiving matching network of on piece being suitable for permanent envelope non-linear modulation and methods, chip is in reception state, first switching switch is closed, the transmitting terminal TX of on piece radiating circuit is set not have signal communication between the port of piece outside antenna, and second switches switch OFF, the signal of antenna port is able to send to the receiving terminal RX of on piece receiving circuit by antenna matching network, on-chip transformer；In emission state, the first switching switch OFF makes the signal of transmitting terminal TX pass through output bandpass filtering network and is sent to antenna port, and the second switching switch is closed, and on-chip transformer is made to be in the state that short circuit is connected to GND.The present invention can be designed in integrated circuit silicon on piece and be realized; piece is outer in addition to antenna is without additional matching device; the a large amount of higher harmonic components generated when permanent envelope non-linear modulation signal transmitting can be filtered out; it is provided in input and the band logical of required frequency range is selected, also form the static electric charge discharge prevention to antenna component end using on-chip inductor.

Description

On-chip integrated transceiver matching network and method suitable for constant-envelope nonlinear modulation

technical field

The invention relates to a radio frequency integrated circuit on-chip matching circuit, in particular to an on-chip antenna matching circuit suitable for a constant envelope non-linear modulation communication mode.

Background technique

The matching circuit of the existing radio frequency circuit antenna is often realized on the printed circuit board (PCB) by using off-chip components (capacitors, inductors, etc.), which put forward higher requirements on the precision of the impedance of the components and the design of the PCB. Added to the BOM (Bill of Materials) cost as well. Some people also try to make the matching network on-chip, but they cannot effectively filter out the high-order harmonics of the transmitted signal, which will interfere with other communication frequency bands.

With the development of integrated circuits, more and more circuits and peripheral devices are integrated on silicon chips, especially in the application fields of smart wearables and low-power Internet of Things devices, which put forward high requirements for the integration of chips. The antenna matching network, as well as the necessary BALUN (on-chip inductance transformer, used for single-end, double-end conversion, impedance conversion, etc., referred to as on-chip transformer), and the transceiver switch (SWITCH) are integrated on the chip, which not only reduces the cost of the integrated circuit The difficulty of matching during application increases the stability of work, and greatly reduces the number and volume of components on the printed circuit board, which fully meets the needs of smart wearable devices and low-power Internet of Things devices, and has great technical significance and market value.

In low-power Internet of Things and smart wearable devices, a common communication modulation method is constant envelope nonlinear modulation, such as Gauss Frequency Shift Keying (GFSK), which has low difficulty in implementing the transmission link. , The characteristics of low power consumption, so it is widely used. However, due to nonlinear modulation, the output spectrum often contains strong high-order harmonic components, which will cause serious interference to other frequency bands, and must be filtered to comply with communication compatibility specifications. At present, there is a lack of an on-chip antenna matching circuit that can effectively filter out high-order harmonic components in a constant-envelope nonlinear modulation communication mode.

Contents of the invention

In view of the above situation, the present invention provides an on-chip integrated circuit transceiver matching network and method suitable for constant-envelope nonlinear modulation communication, which can be designed and implemented on an integrated circuit silicon chip without additional off-chip matching devices, and can be extremely The ground filters out a large number of high-order harmonic components generated when the constant-envelope nonlinear modulation signal is transmitted, and at the same time provides a band-pass selection for the required frequency band when inputting and outputting, and also uses the on-chip inductor to form a natural pair of chip antenna terminals Static charge discharge protection.

In order to achieve the above object, a technical solution of the present invention is to provide an on-chip integrated circuit transceiver matching network suitable for constant envelope nonlinear modulation, which includes: on-chip inductance L1, inductance L2, capacitor C1, capacitor C2, capacitor C3 , switch S1 of NMOS tube, on-chip transformer; antenna is provided outside the chip;

The transmitting end TX for the output of the on-chip transmitting circuit is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the drain end of the switch S1 and a plate of the capacitor C2 at node B, and the source end of the switch S1 is connected to GND, and the switch S1 is connected to It is controlled by the receiving enable signal RXEN input into its gate;

The other plate of capacitor C2, one plate of capacitor C1 and one end of inductor L1 are all connected to the port of the antenna; the other plate of capacitor C1 is connected to GND;

The other end of the inductor L1 is connected to the input terminal of the primary coil of the on-chip transformer at node A, the other end of the primary coil is connected to GND with one plate of the capacitor C3, and the other plate of the capacitor C3 is connected to node A; the secondary of the on-chip transformer The coil is connected with the receiving end RX of the on-chip receiving circuit.

Optionally, when the chip is working in the receiving state, a fully DC-connected electrostatic discharge path is formed, which is connected from the antenna port to the primary coil of the on-chip transformer through the inductor L1, and then connected to GND;

When the chip is working in the transmitting state, it forms a static electricity discharge path that is completely connected with direct current, which is connected from the antenna port to GND through the inductor L1.

Optionally, the connection structure of the other end of the inductor L1 and the other plate of the capacitor C1 is replaced by:

The other end of inductor L1 is connected to GND, and the other plate of capacitor C1 is connected at node A to the primary coil input of the on-chip transformer;

When the chip works in the receiving state, it forms a static discharge path with complete DC connection, which is connected from the antenna port to GND through the inductor L1, and from the antenna port to GND through the primary coil of the on-chip transformer;

When the chip is working in the transmitting state, it forms a static electricity discharge path that is completely connected with direct current, which is connected from the antenna port to GND through the inductor L1.

Optionally, when the chip is working in the receiving state, the transmitting terminal TX has no output signal, the receiving enable signal RXEN is at a high level, and the inductor L2 is connected to GND through the switch S1 with source-drain conduction; the signal of the antenna passes through the inductor L1, The input matching network formed by capacitor C1, capacitor C2, capacitor C3 and the on-chip transformer enters the on-chip receiving circuit;

When the chip is working in the transmitting state, the on-chip transformer is short-circuited to GND; the inductor L1 and capacitor C1 form a resonant cavity; the receiving enable signal RXEN is low, the switch S1 is turned off, and the inductor L2 and capacitor C2 form the required frequency band The band-pass filter structure; the signal output by the transmitter TX is matched to the antenna port through the structure formed by the inductor L2, the inductor L1, the capacitor C1, the capacitor C2 and the capacitor C5, and the capacitor C5 is the connection between the drain of the switch S1 and the GND when the switch S1 is turned off. parasitic capacitance.

Optionally, the connection structure of the other plate of the capacitor C2, the other end of the inductor L1, and the two plates of the capacitor C3 is replaced by:

The other plate of capacitor C2 and the other end of inductor L1 are both connected to one plate of capacitor C3 at node C; the other plate of capacitor C3 is connected to the primary coil input terminal of the on-chip transformer at node A;

When the chip is working in the receiving state or the transmitting state, there are respectively formed a static electricity discharge path with complete DC connection, which is connected from the antenna port to the inductor L1, and then connected to GND.

Optionally, when the chip is working in the receiving state, the transmitting terminal TX has no output signal, the receiving enable signal RXEN is at a high level, and the inductor L2 is connected to GND through the switch S1 with source-drain conduction; the inductor L1, the capacitor C1, the capacitor C2 forms an input π-type matching network, and the antenna signal enters the on-chip receiving circuit through the on-chip input port formed by the capacitor C3 and the on-chip transformer;

When the chip is working in the transmitting state, the on-chip transformer is short-circuited to GND; the receiving enable signal RXEN is low, the switch S1 is turned off, the inductor L2 and the capacitor C2 form a band-pass filter structure of the required frequency band; the capacitor C3 is in the The plate on the side of node A is connected to GND, so that capacitor C3, inductor L1, and capacitor C1 form a transmission π-type matching network in the required frequency band; the signal output by the transmitter TX passes through inductor L2, inductor L1, and capacitor C1 The structure formed by , capacitor C2 and capacitor C3 is matched to the antenna port.

Optionally, the on-chip integrated circuit transceiver matching network is further provided with a switch S2 of an NMOS transistor, so that the drain end of the switch S2 is connected to node A, the source end of the switch S2 is connected to GND, and the switch S2 makes Can signal TXEN to control;

Or, when the chip works in the transmitting state, the secondary coil of the on-chip transformer can be short-circuited to the ground, then the switch S2 is not set.

Optionally, when the chip is working in the receiving state, the transmit enable signal TXEN is at zero level, the switch S2 is turned off, and the node A is connected to GND through the parasitic capacitance C4 formed from its drain terminal to GND when the switch S2 is turned off;

When the chip works in the transmitting state, the transmitting enable signal TXEN is at a high level, the source and drain of the switch S2 are turned on, and the node A is connected to GND through the switch S2.

Optionally, the connection to GND means connecting to the ground, or connecting to the negative terminal of the radio frequency input and output port of the chip, or connecting to the negative terminal of the antenna.

Another technical solution of the present invention is to provide an on-chip integrated circuit transceiver matching method suitable for constant envelope nonlinear modulation, using any one of the above-mentioned on-chip integrated circuit transceiver matching networks suitable for constant envelope nonlinear modulation;

Among them, in the transceiver circuit implemented by integrated circuit technology and using the constant envelope nonlinear modulation communication mode, the transmitting end TX of the on-chip transmitting circuit is connected to the port of the off-chip antenna through the output band-pass filter network; the output band-pass filter network having a first toggle switch connectable to GND;

The receiving end RX of the on-chip receiving circuit is connected to the antenna matching network through the on-chip transformer; the antenna matching network is connected to the port of the off-chip antenna, and is provided with a second switch that can be connected to GND;

When the chip works in the receiving state, the first switch is closed, so that there is no signal connection between the transmitting terminal TX and the antenna port, and the second switch is turned off, and the signal of the antenna port is sent to the antenna port through the antenna matching network and the on-chip transformer. To the receiving end RX;

When the chip works in the transmitting state, the first switch is turned off, so that the signal of the transmitting terminal TX is sent to the antenna port through the output band-pass filter network, and the second switch is closed, so that the on-chip transformer is short-circuited and connected to GND status.

The present invention discloses an on-chip matching network for transceiver circuits suitable for implementation with integrated circuit technology (CMOS, gallium arsenide, SOI, etc.) for constant-envelope nonlinear modulation communication modes (BPSK, GFSK, GMSK, etc.), including Transceiver switch, on-chip transformer (BALUN), and matching components. Not only can it be easily designed and realized on the integrated circuit silicon chip, but also no additional off-chip matching devices are needed, and it can greatly filter out a large number of high-order harmonic components generated when the constant-envelope nonlinear modulation signal is transmitted. It provides band-pass selection for the required frequency band, and also uses the on-chip inductor to form a natural protection against the static charge discharge (Electro-Static Discharge, ESD) of the chip antenna.

The matching network of most of the existing radio frequency circuits is implemented off-chip, that is, on a non-integrated circuit, and the usual matching network is only to complete the conversion and matching of the impedance of the circuit to the impedance of the antenna, so that the transmission and reception of the circuit Best in power transfer performance.

The characteristics of the present invention, the first is on-chip implementation (consisting of CMOS tube switches, capacitors and inductances that can be implemented on-chip), and the second is that not only can complete impedance conversion and matching, but also can realize high transmission signal on-chip for nonlinear modulation communication The third is to realize the electrostatic protection function at the same time.

Because the constant envelope nonlinear debugging method has the characteristics of high transmission efficiency, it is more and more used in various communication modulation methods, but one disadvantage of this method is that the spectrum of the transmitted signal will generate a large number of non-local channels. The higher harmonics in the channel will interfere with adjacent channels and even other communication frequency bands. In particular, the present invention optimizes the shortcomings of this communication method. In addition to the on-chip impedance matching design, an on-chip output band-pass filter network is specially added to filter out the high-order harmonics unique to this modulation method, making the transmission The frequency spectrum is limited to its own specific frequency band, thereby saving the filter network outside the chip, and achieving impedance matching at the same time. If it is not applied in a non-linear modulation mode, the frequency spectrum of the signal itself at the transmitting end does not generate high-order harmonics, and the output band-pass filter network at the transmitting end may not be needed.

The present invention also belongs to BPSK, GFSK, GMSK and other methods of constant envelope non-linear modulation communication, according to the impedance of the circuit itself, the power requirement of transmission and the difference of channel frequency band, etc., in the specific implementation mode below , to adapt to the adjustment such as the size of the tube, bias voltage and switch voltage, the parameter values of capacitors and inductors and the complexity of the network will also be different.

In order to reflect the ESD protection, in various embodiments disclosed in the present invention, except the off-chip antenna ANT is on the chip, other circuits are implemented on the chip, and the port of the off-chip antenna ANT is a pin that needs electrostatic protection on the chip; The pins of the chip must have certain electrostatic protection capabilities, otherwise they will be damaged by static electricity, causing the pins to fail and become unusable. Whether it is a transmitting state or a receiving state, the present invention always has a path of complete DC communication from the port of the off-chip antenna ANT to the GND ground, that is, there is always an electrostatic discharge path that can discharge the static electricity of the port of the off-chip antenna ANT to GND goes up.

Description of drawings

Fig. 1 is a schematic diagram of the topology of the on-chip matching network of the present invention;

Fig. 2 is a schematic structural diagram of the on-chip matching network in the first embodiment of the present invention;

Fig. 3 is a schematic diagram of the principle of the chip working in the receiving state in the first embodiment;

Fig. 4 is a schematic diagram of the principle of the chip working in the transmitting state in the first embodiment;

5 is a schematic structural diagram of the on-chip matching network in the second embodiment of the present invention;

Fig. 6 is a schematic diagram of the principle of the chip working in the receiving state in the second embodiment;

Fig. 7 is a schematic diagram of the principle of the chip working in the transmitting state in the second embodiment;

FIG. 8 is a schematic structural diagram of the on-chip matching network in the third embodiment of the present invention;

Fig. 9 is a schematic diagram of the principle of the chip working in the receiving state in the third embodiment;

Fig. 10 is a schematic diagram of the chip working in the transmitting state in the third embodiment.

Detailed ways

As shown in FIG. 1 , the present invention provides a novel on-chip matching network whose topological structure includes: an output bandpass filter network, an antenna matching network, an on-chip transformer B1, a switch S1 and a switch S2. The off-chip antenna ANT in the figure is an off-chip component of the integrated circuit, and the others are implemented on-chip.

Fig. 2 shows the first embodiment of the on-chip matching network of the present invention:

The output of the transmitter TX in the integrated circuit is connected to one end of the inductor L2 on the chip, and the other end of the inductor L2 is connected to the drain end of the switch S1 of the NMOS transistor and a plate of the capacitor C2 on the chip at node B, and the source end of the switch S1 is connected to GND. Its gate is controlled by receiving the enable signal RXEN. The other plate of the capacitor C2 is connected with one plate of the on-chip capacitor C1, connected to the off-chip antenna ANT, and connected to one end of the on-chip inductor L1; the other plate of the capacitor C1 is connected to GND.

The other end of the inductor L1 is connected to the input terminal of the primary coil of the on-chip transformer B1 and the drain terminal of the switch S2 of the NMOS transistor at node A, the other end of the primary coil of the on-chip transformer B1 is connected to GND, and the on-chip transformer B1 is connected in parallel with the capacitor C3. The source end of the switch S2 of the NMOS transistor is connected to GND, and the gate thereof is connected to the transmission enable signal TXEN. The secondary coil of the on-chip transformer B1 is connected to the receiving end RX. Here, the connection to GND is always used to represent the three situations of connecting to the ground, the negative terminal of the chip’s RF input and output port, or the negative terminal of the antenna.

As shown in Figure 3, when the chip is working in the receiving state, the transmitting terminal TX has no output signal. At this time, it is advisable to set the receiving enable signal RXEN as high level, so that the source and drain of the switch S1 are turned on, so that the inductor L2 and the capacitor The end node B connected by C2 is turned on to GND, the output of the transmitter TX only sees the inductive load of the inductor L2, and the capacitor C2 is actually incorporated into the capacitor C1 to become a part of the receiving match; at this time, the capacitor C1 and the capacitor C2 are connected in parallel, The plates on one side of them are connected to the port of the off-chip antenna ANT and one end of the on-chip inductor L1, and the other side is connected to GND and GND through the switch S1 respectively.

When receiving, the transmit enable signal TXEN may be set to zero level, the switch S2 is turned off, and C4 is the parasitic capacitance from the drain terminal of the switch S2 to GND when the switch S2 is turned off. The signal of the off-chip antenna ANT can only enter the on-chip receiving circuit through the Π-type matching network composed of inductor L1, capacitor C1, capacitor C2, capacitor C3, parasitic capacitor C4 and on-chip transformer B1, and the transmitter TX is connected to GND due to inductor L2. Therefore, no signal can enter the port of the off-chip antenna ANT.

As shown in Figure 4, when transmitting, the transmit enable signal TXEN may be set to a high level, the switch S2 is turned on, the node A of the inductor L1 is connected to GND through the switch S2, and the primary coil of the on-chip transformer B1 and the two primary coils of the capacitor C3 The sides are respectively connected to GND and connected to GND via the turned-on switch S2. At this time, the inductance L1 and the capacitor C1 form a parallel resonant cavity; and the RXEN on the gate of the switch S1 may be set to zero level, the switch S1 is turned off, and the emission The terminal TX signal leads to the port of the off-chip antenna ANT through the inductor L2 and the capacitor C2 connected to the inductor L2 at node B, wherein the capacitor C5 is the parasitic capacitance from the drain of the switch S1 to GND when the switch S1 is turned off.

When transmitting, the TX signal at the transmitting end is output to the port of the off-chip antenna ANT through the inductor L2, the inductor L1, the capacitor C1, the capacitor C2, and the capacitor C5, while the receiving on-chip transformer B1 is short-circuited to GND, and cannot receive signals from the off-chip antenna. ANT signal. Since the connection state of inductor L2 and capacitor C2 during transmission forms a band-pass filter characteristic in the required frequency band, it can effectively eliminate the high-order harmonic components of the output signal; at the same time, the resonant cavity formed by inductor L1 and capacitor C1 can further improve The output impedance in the desired frequency band further improves the output signal-to-noise ratio. If the secondary coil of the on-chip transformer B1 in the on-chip receiving part can be short-circuited to ground during transmission, the function of transmission can also be realized without the switch S2, because the characteristics of the on-chip transformer B1 can guarantee the function realized by the switch S2. Therefore, the switch S2 in the above-mentioned FIG. 2 is indicated by a dotted box.

FIG. 5 shows the second embodiment of the on-chip matching network of the present invention, which is mainly different from the first embodiment in that the positions of the inductor L1 and the capacitor C1 are exchanged.

The output end of the transmitting circuit (transmitting end TX) is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to a plate of the capacitor C2 at the node B, and the node B is also connected to the drain end of the switch S1 of the NMOS transistor, and the capacitor C2 The other plate is connected to the port of the off-chip antenna ANT, where the gate of the switch S1 is connected to receive the enable signal RXEN to control the switch S1 to be closed or turned off, and the source of the switch S1 is connected to GND (here, all connected to GND means connected to the ground, the negative terminal of the chip’s RF input and output port, or the negative terminal of the antenna).

The port of the off-chip antenna ANT is also connected to one end of the inductor L1 and one plate of the capacitor C1, the other end of the inductor L1 is connected to GND, and the other plate of the capacitor C1 is connected to node A, and connected to the on-chip transformer B1 The input terminal of the primary coil is connected, node A is also connected to the drain terminal of the switch S2 of the NMOS transistor and a plate of the capacitor C3, the other end of the input primary coil of the on-chip transformer B1 is connected to the other end of the capacitor C3 and connected to GND, and the switch S2 The gate of the switch S2 is connected to the transmit enable signal TXEN to control the closing or closing of the switch S2, and the source of the switch S2 is connected to GND.

As shown in Figure 6, when receiving, it is advisable to set TXEN to zero level and RXEN to high level, so that switch S1 is closed to connect node B to GND through switch S1, and switch S2 is turned off at this time. The transmitting end TX has no signal output at this time, and is connected to GND through the inductor L2 at the same time, and cannot reach the port of the off-chip antenna ANT. Inductor L1, capacitor C1, and capacitor C2 are connected in parallel to form the input matching network of off-chip antenna ANT, and the signal of off-chip antenna ANT is sent to the on-chip input port formed by on-chip transformer B1 and capacitor C3 at the same time. C4 is when switch S2 is turned off, switch S2 Parasitic capacitance of drain to GND.

As shown in Figure 7, when transmitting, it is advisable to set TXEN to be high and RXEN to be low, so that switch S2 is closed to connect node A to GND via switch S2, and switch S1 is turned off at this time. Since the switch S2 is closed and the node A is short-circuited to GND, the on-chip transformer B1 and capacitor C3 actually do not work, and one side plate of the capacitor C1 is connected to GND via the switch S2, and the inductor L1 forms a resonant cavity in the required frequency band, improving The load impedance of the transmitter increases the signal-to-noise ratio of the transmitter. At this time, the port of the off-chip antenna ANT is also connected to the transmitting terminal TX through the capacitor C2 and the inductance L2, and the transmitted signal at TX is matched to the off-chip antenna ANT through the structure shown in Fig. Higher harmonic components of a linearly modulated signal. If the secondary coil of the on-chip transformer B1 in the on-chip receiving part can be short-circuited to ground during transmission, the function of transmission can also be realized without the switch S2, because the characteristics of the on-chip transformer B1 can guarantee the function realized by the switch S2. Therefore, the switch S2 in the above-mentioned FIG. 5 is indicated by a dotted box.

FIG. 8 shows the third embodiment of the on-chip matching network of the present invention. The main difference between it and the first embodiment is that one plate of the capacitor C2 is not directly connected to the off-chip antenna ANT, but is connected to point A.

The output end of the transmitting circuit (transmitting end TX) is connected to the inductor L2, and the other end of the inductor L2 is connected to one plate of the capacitor C2 at the node B, and the node B is also connected to the drain end of the switch S1 of the NMOS transistor, and the other end of the capacitor C2 The plate is connected to node C, where the gate of the switch S1 is connected to receive the enable signal RXEN to control the switch S1 to be closed or turned off, and the source of the switch S1 is connected to GND (here, it is always connected to GND to indicate that it is connected to ground, The negative terminal of the chip's RF input and output port or the negative terminal of the antenna). The node C is also connected to one end of the inductor L1, the other end of the inductor L1 is connected to one plate of the capacitor C1 and connected to the off-chip antenna ANT, and the other plate of the capacitor C1 is connected to GND. The node C is also connected to one plate of the capacitor C3, and the other plate of the capacitor C3 is connected to the drain end of the switch S2 of the NMOS transistor and one end of the input primary coil of the on-chip transformer B1 at the node A. The gate of the switch S2 is connected to the transmit enable signal TXEN to control the switch S2 on or off, and the source of the switch S2 is connected to GND.

As shown in Figure 9, when receiving, it is advisable to set TXEN to zero level and RXEN to high level, so that switch S1 is closed to connect node B to GND through switch S1, and switch S2 is turned off at this time. The transmitting end TX has no signal output at this time, and is connected to GND through the inductor L2 at the same time, and cannot reach the port of the off-chip antenna ANT. Inductor L1, capacitor C1, and capacitor C2 form the input π-type matching network of the off-chip antenna ANT, and the signal terminal of the off-chip antenna ANT is simultaneously sent to the on-chip input port formed by the on-chip transformer B1 and capacitor C3, and C4 is when the switch S2 is turned off. The parasitic capacitance of switch S2 drain to GND.

As shown in Figure 10, when transmitting, it is advisable to set TXEN to be high and RXEN to be low, so that switch S2 is closed to connect node A to GND via switch S2, and switch S1 is turned off at this time. Since the switch S2 is closed and the node A is short-circuited to GND, the on-chip transformer B1 actually does not work, and one side plate of the capacitor C3 is connected to GND through the switch S2, and the inductor L1 and the capacitor C1 form a transmission π-type matching of the required frequency band network. At this time, the capacitor C2 and the inductor L2 are also connected to the TX output terminal to form a band-pass filter network on the required frequency band. The TX transmit signal is matched to the port of the off-chip antenna ANT through the structure shown in Figure 10, which is very good The high-order harmonic component of the constant-envelope nonlinear modulation signal is filtered out, and sufficient power transmission matching gain is provided. If the secondary coil of the on-chip transformer B1 in the on-chip receiving part can be short-circuited to ground during transmission, the function of transmission can also be realized without the switch S2, because the characteristics of the on-chip transformer B1 can guarantee the function realized by the switch S2. Therefore, the switch S2 in FIG. 8 is indicated by a dotted box.

The invention provides an on-chip integrated circuit transceiver matching network suitable for constant envelope nonlinear modulation communication, which can be designed and realized on the integrated circuit silicon chip without additional off-chip matching devices, and can greatly filter out the constant envelope A large number of high-order harmonic components generated when the nonlinear modulation signal is transmitted, at the same time, it provides a band-pass selection for the required frequency band at the input and output, and also uses the on-chip inductance to form a natural static charge discharge (ESD) on the chip antenna terminal. Protect.

Whether it is the transmitting state or the receiving state, in the three specific implementations of the present invention, there is always a path of complete DC communication from the port of the off-chip antenna ANT to the GND ground, that is, there is always an electrostatic discharge path that can discharge the off-chip The static electricity of the port of the antenna ANT is discharged to GND, so as to realize the protection of the static charge discharge of the chip antenna:

For example, in the first embodiment corresponding to Fig. 2, Fig. 3 and Fig. 4, in the receiving state, the electrostatic discharge path starting from the port of the off-chip antenna ANT is from the off-chip antenna ANT to the inductor L1 to the primary coil of the on-chip transformer B1 , and then to GND; and in the transmitting state, from the port of the off-chip antenna ANT to the inductor L1, and then to GND. In the second embodiment corresponding to Figure 5, Figure 6 and Figure 7, in the receiving state, the electrostatic discharge path is from the off-chip antenna ANT to the inductor L1 and from the off-chip antenna ANT to the primary coil of the on-chip transformer B1, and then to GND ; In the transmitting state, the electrostatic discharge path is from the off-chip antenna ANT to the inductor L1, and then to GND. In the third embodiment corresponding to FIG. 8 , FIG. 9 and FIG. 10 , no matter the receiving state or the transmitting state, there is always an electrostatic discharge path from the off-chip antenna ANT to the inductor L1 and then to GND.

Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as limiting the present invention. Various modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the above disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. An on-chip integrated circuit transceiver matching network suitable for constant-envelope nonlinear modulation is characterized in that it includes: on-chip inductance L1, inductance L2, capacitor C1, capacitor C2, capacitor C3, switch S1 of NMOS tube, on-chip Transformer; Antenna is provided outside the chip; The transmitting end TX for the output of the on-chip transmitting circuit is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the drain end of the switch S1 and a plate of the capacitor C2 at node B, and the source end of the switch S1 is connected to GND, and the switch S1 is connected to Its gate is controlled by the receiving enable signal RXEN; The other plate of capacitor C2, one plate of capacitor C1 and one end of inductor L1 are all connected to the port of the antenna; the other plate of capacitor C1 is connected to GND; The other end of the inductor L1 is connected to the input terminal of the primary coil of the on-chip transformer at node A, the other end of the primary coil is connected to GND with one plate of the capacitor C3, and the other plate of the capacitor C3 is connected to node A; the secondary of the on-chip transformer The coil is connected with the receiving end RX of the on-chip receiving circuit. 2. The on-chip integrated circuit transceiver matching network as claimed in claim 1, characterized in that, When the chip works in the receiving state, it forms a static discharge path with complete DC connection, which is connected from the antenna port to the primary coil of the on-chip transformer through the inductor L1, and then connected to GND; When the chip is working in the transmitting state, it forms a static electricity discharge path that is completely connected with direct current, which is connected from the antenna port to GND through the inductor L1. 3. The on-chip integrated circuit transceiver matching network as claimed in claim 1, characterized in that, Replace the connection structure of the other end of the inductor L1 and the other plate of the capacitor C1 with: The other end of inductor L1 is connected to GND, and the other plate of capacitor C1 is connected at node A to the primary coil input of the on-chip transformer; When the chip works in the receiving state, it forms a static discharge path with complete DC connection, which is connected from the antenna port to GND through the inductor L1, and from the antenna port to GND through the primary coil of the on-chip transformer; When the chip is working in the transmitting state, it forms a static electricity discharge path that is completely connected with direct current, which is connected from the antenna port to GND through the inductor L1. 4. the on-chip integrated circuit transceiver matching network as claimed in claim 1 or 3, is characterized in that, When the chip is working in the receiving state, the transmitting end TX has no output signal, the receiving enable signal RXEN is high level, the inductor L2 is connected to GND through the switch S1 with source-drain conduction; the signal of the antenna passes through the inductor L1, capacitor C1, capacitor The input matching network formed by C2, capacitor C3 and the on-chip transformer enters the on-chip receiving circuit; When the chip is working in the transmitting state, the on-chip transformer is short-circuited to GND; the inductor L1 and capacitor C1 form a resonant cavity; the receiving enable signal RXEN is low, the switch S1 is turned off, and the inductor L2 and capacitor C2 form the required frequency band The band-pass filter structure; the signal output by the transmitter TX is matched to the antenna port through the structure formed by the inductor L2, the inductor L1, the capacitor C1, the capacitor C2 and the capacitor C5, and the capacitor C5 is the connection between the drain of the switch S1 and the GND when the switch S1 is turned off. parasitic capacitance. 5. The on-chip integrated circuit transceiver matching network as claimed in claim 1, characterized in that, Replace the connection structure of the other plate of capacitor C2, the other end of inductor L1, and the two plates of capacitor C3 with: The other plate of capacitor C2 and the other end of inductor L1 are both connected to one plate of capacitor C3 at node C; the other plate of capacitor C3 is connected to the primary coil input terminal of the on-chip transformer at node A; When the chip is working in the receiving state or the transmitting state, there are respectively formed a static electricity discharge path with complete DC connection, which is connected from the antenna port to the inductor L1, and then connected to GND. 6. The on-chip integrated circuit transceiver matching network as claimed in claim 5, characterized in that, When the chip is working in the receiving state, the transmitting terminal TX has no output signal, the receiving enable signal RXEN is at high level, and the inductor L2 is connected to GND through the switch S1 with source-drain conduction; the inductor L1, capacitor C1, and capacitor C2 form an input π Type matching network, the antenna signal enters the on-chip receiving circuit through the on-chip input port formed by the capacitor C3 and the on-chip transformer; When the chip is working in the transmitting state, the on-chip transformer is short-circuited to GND; the receiving enable signal RXEN is low, the switch S1 is turned off, the inductor L2 and the capacitor C2 form a band-pass filter structure of the required frequency band; the capacitor C3 is in the The plate on the side of node A is connected to GND, so that capacitor C3, inductor L1, and capacitor C1 form a transmission π-type matching network in the required frequency band; the signal output by the transmitter TX passes through inductor L2, inductor L1, and capacitor C1 The structure formed by , capacitor C2 and capacitor C3 is matched to the antenna port. 7. The on-chip integrated circuit transceiver matching network according to any one of claims 1 to 6, wherein: A switch S2 with an NMOS transistor is further provided, so that the drain end of the switch S2 is connected to the node A, the source end of the switch S2 is connected to GND, and the switch S2 is controlled by a transmission enable signal TXEN connected to its gate; Alternatively, when the chip is working in the transmitting state, if the secondary coil of the on-chip transformer can be short-circuited to the ground, then the switch S2 is not set. 8. The on-chip integrated circuit transceiver matching network as claimed in claim 7, characterized in that, When the chip is working in the receiving state, the transmission enable signal TXEN is at zero level, the switch S2 is turned off, and the parasitic capacitance C4 formed by the drain terminal of node A to GND is connected to GND when the switch S2 is turned off; When the chip works in the transmitting state, the transmitting enable signal TXEN is at a high level, the source and drain of the switch S2 are turned on, and the node A is connected to GND through the switch S2. 9. The on-chip integrated circuit transceiver matching network according to any one of claims 1 to 8, characterized in that being connected to GND means connecting to ground, or connecting to the negative terminal of the chip's radio frequency input and output port, or connecting to The negative terminal of the antenna. 10. An on-chip integrated circuit transceiver matching method suitable for constant envelope nonlinear modulation, using the on-chip integrated circuit transceiver matching network suitable for constant envelope nonlinear modulation described in any one of claims 1-9, characterized in is that Realized by integrated circuit technology, in the transceiver circuit using the constant envelope non-linear modulation communication mode, the transmitting end TX of the on-chip transmitting circuit is connected to the port of the off-chip antenna through the output band-pass filter network; the output band-pass filter network is provided with a first toggle switch connectable to GND; The receiving end RX of the on-chip receiving circuit is connected to the antenna matching network through the on-chip transformer; the antenna matching network is connected to the port of the off-chip antenna, and is provided with a second switch that can be connected to GND; When the chip works in the receiving state, the first switch is closed, so that there is no signal connection between the transmitting terminal TX and the antenna port, and the second switch is turned off, and the signal of the antenna port is sent to the antenna port through the antenna matching network and the on-chip transformer. To the receiving end RX; When the chip works in the transmitting state, the first switch is turned off, so that the signal of the transmitting terminal TX is sent to the antenna port through the output band-pass filter network, and the second switch is closed, so that the on-chip transformer is short-circuited and connected to GND status.