CN108695237B

CN108695237B - Semiconductor device and manufacturing method thereof

Info

Publication number: CN108695237B
Application number: CN201710218249.3A
Authority: CN
Inventors: 邓浩
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-04-05
Filing date: 2017-04-05
Publication date: 2020-12-15
Anticipated expiration: 2037-04-05
Also published as: CN108695237A

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the method comprises the steps of providing a semiconductor substrate; forming an interlayer dielectric layer and a copper interconnection structure positioned in the interlayer dielectric layer on the semiconductor substrate; forming a capping layer on a surface of the copper interconnect structure and the interlayer dielectric layer, wherein the capping layer comprises an ion-doped AlN layer. According to the manufacturing method of the semiconductor device, in the metal interconnection process, the ion-doped AlN layer is formed on the surface of the copper interconnection structure to serve as the covering layer, so that the problems of leakage current and time-dependent breakdown are avoided, the electromigration phenomenon is improved, and the reliability of the semiconductor device is improved.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

With the development of integrated circuits, the feature size is continuously reduced, and the current density introduced by a metal wire is rapidly increased; meanwhile, the increase of chip integration level leads to an increase of power consumption per unit area, and thus, the reliability of metal wiring has been an important issue concerned in IC design and manufacture. In a metal wire, electrons moving in the opposite direction of the electric field exchange momentum with metal ions, resulting in diffusion-dominated mass transport of the metal ions, a phenomenon known as Electromigration (EM). Electromigration is an important metal failure mechanism in the interconnect structure of semiconductor devices. There are two types of failures caused by electromigration, namely open and short circuit of the interconnect. Along with electromigration of Cu ions, atomic loss occurs near a cathode, local tension is gradually increased, and after a critical value is reached, a cavity is formed, so that resistance is increased, and finally, an interconnection line is opened. In the anode atom accumulation region, the local pressure is increased continuously, so that there may be metal protrusion in this region, which may cause a short circuit of the interconnection line if the protruding metal is in contact with the metal interconnection adjacent to it.

Electromigration may have multiple diffusion paths such as surface, interface, grain boundary diffusion, lattice diffusion. Recent studies have shown that electromigration is mainly caused by diffusion at the Cu/capping layer interface and the Cu/barrier layer interface, and the Cu/capping layer interface is the most dominant diffusion path for electromigration, so that the Cu/capping layer interface is crucial for controlling the corresponding electrical properties and reliability performance, and the electromigration characteristics can be improved by improving the interface performance to suppress the diffusion phenomenon at the Cu/capping layer interface. Various interface processing techniques are widely used and studied as a method capable of improving the Cu/capping layer interface.

However, in the process of forming the Cu/cap layer interface according to the prior art, the problems of Cu/cap layer interface interaction, penetration, adhesion fastness, etc. still need to be solved and improved in production practice.

Therefore, in view of the above problems, the present invention provides a new semiconductor device and a method for fabricating the same.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:

providing a semiconductor substrate;

forming an interlayer dielectric layer and a copper interconnection structure positioned in the interlayer dielectric layer on the semiconductor substrate;

forming a capping layer on a surface of the copper interconnect structure and the interlayer dielectric layer, wherein the capping layer comprises an ion-doped AlN layer.

Further, the ions that are doped include Ge.

Further, the capping layer is formed by an atomic deposition method.

Further, the source gas for forming the AlN layer includes AlCH₃。

Further, carry outThe Ge ion doped source gas comprises GeH₄。

Further, the capping layer further includes an undoped AlN layer over the ion-doped AlN layer.

Further wherein the thickness of the ion-doped AlN layer is 1/2-2/3 of the total thickness of the capping layer.

Further, the doping concentration of Ge ions is gradually reduced from bottom to top.

Further, the method also comprises the step of plasma processing the surface of the copper interconnection structure to remove the copper oxide before forming the covering layer.

Further, the method also comprises the step of carrying out annealing treatment on the covering layer after the covering layer is formed.

In addition, the present invention also provides a semiconductor device including:

a semiconductor substrate;

an interlayer dielectric layer formed on a semiconductor substrate and a copper interconnection structure located in the interlayer dielectric layer;

a capping layer formed on surfaces of the copper interconnect structure and the interlayer dielectric layer, wherein the capping layer comprises an ion-doped AlN layer.

Further, the ions that are doped include Ge.

Further, the capping layer further comprises an undoped AlN layer over the ion-doped AlN layer, wherein the ion-doped AlN layer has a thickness 1/2-2/3 of a total thickness of the capping layer.

Further, a CuGe-AlN alloy layer is formed between the copper interconnection structure and the covering layer.

According to the manufacturing method of the semiconductor device, in the metal interconnection process, the ion-doped AlN layer is formed on the surface of the copper interconnection structure to serve as the covering layer, so that the problems of leakage current and time-dependent breakdown are avoided, the electromigration phenomenon is improved, and the reliability of the semiconductor device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.

In the drawings:

fig. 1 is a schematic flow chart of a method of fabricating a semiconductor device according to a first exemplary embodiment of the present invention.

Fig. 2A-2E are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Electromigration (EM) is an important metal failure mechanism in the interconnect structure of semiconductor devices. Electromigration may have multiple diffusion paths such as surface, interface, grain boundary diffusion, lattice diffusion. Recent studies have shown that electromigration is mainly caused by diffusion at the Cu/capping layer interface and the Cu/barrier layer interface, and the Cu/capping layer interface is the most dominant diffusion path for electromigration, so that the Cu/capping layer interface is crucial for controlling the corresponding electrical properties and reliability performance, and the electromigration characteristics can be improved by improving the interface performance to suppress the diffusion phenomenon at the Cu/capping layer interface. Various interface processing techniques are widely used and studied as a method capable of improving the Cu/capping layer interface.

Aluminum nitride (AlN), an emerging material for copper interconnect structures, is effective in improving Electromigration (EM) phenomena while having a higher etch selectivity than conventional etch stop layers. However, in the existing production process, Al precursor is easy to permeate into the interlayer dielectric layer, which causes the problems of leakage current and time dependent breakdown (TDDB), and seriously affects the reliability of the semiconductor device.

Therefore, there is a need for a method for fabricating a semiconductor device, which can effectively avoid electromigration at the Cu/capping layer interface and ensure stable performance of the semiconductor device.

providing a semiconductor substrate;

Wherein the ions that are doped comprise Ge; forming the covering layer by adopting an atomic deposition method; the source gas for forming the AlN layer comprises AlCH₃(ii) a The source gas for the Ge ion doping comprises GeH₄(ii) a The capping layer further comprises an undoped AlN layer located over the ion-doped AlN layer; wherein the thickness of the ion-doped AlN layer is 1/2-2/3 of the total thickness of the covering layer; the doping concentration of Ge ions is gradually reduced from bottom to top; the step of plasma processing the surface of the copper interconnection structure to remove copper oxide is further included before the covering layer is formed; the method also comprises the step of carrying out annealing treatment on the covering layer after the covering layer is formed.

[ example one ]

Reference is now made to fig. 1 and 2A-2E, where fig. 1 is a schematic flow chart of a method of fabricating a semiconductor device in accordance with an exemplary embodiment one of the present invention, and fig. 2A-2E are schematic cross-sectional views of devices respectively obtained by sequentially performing steps in accordance with the method of the exemplary embodiment one of the present invention.

The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:

step S101: providing a semiconductor substrate;

step S102: forming an interlayer dielectric layer and a copper interconnection structure positioned in the interlayer dielectric layer on the semiconductor substrate;

step S103: forming a capping layer on a surface of the copper interconnect structure and the interlayer dielectric layer, wherein the capping layer comprises an ion-doped AlN layer.

Next, a detailed description will be given of a specific embodiment of a method for manufacturing a semiconductor device of the present invention.

First, step S101 is performed, as shown in fig. 2A, providing a semiconductor substrate 200.

Illustratively, the semiconductor substrate 200 in the present invention may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, the material of the semiconductor substrate 200 is monocrystalline silicon. An isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, is also formed in the semiconductor substrate 200, and divides the semiconductor substrate 200 into different active regions, in which various semiconductor devices, such as NMOS and PMOS, etc., can be formed. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawing for simplicity.

An etch stop layer 201, which is made of carbon-containing silicon Nitride (NDC), is also formed on the semiconductor substrate 200, and the preparation method can be Chemical Vapor Deposition (CVD). As an example, in the chemical vapor deposition, the power is 200-400W, the temperature in the cavity is heated to 200-400 ℃, the pressure in the cavity is 2-5 Torr, the gas flow of trimethylsilane (3MS) or tetramethylsilane (4MS) is 200-200 cubic centimeters per minute (sccm), the gas flow of He is 350-450 cubic centimeters per minute (sccm), and NH is added₃The gas flow rate is 200-500 cubic centimeters per minute (sccm), and the deposition time lasts 3 s.

Next, step S102 is performed, as shown in fig. 2B, an interlayer dielectric layer 202 and a copper interconnect structure 203 located in the interlayer dielectric layer 202 are formed on the semiconductor substrate 200.

Illustratively, the material of the interlayer dielectric layer 202 may be a low-k dielectric material (formed as an interlayer dielectric layer) or an ultra-low-k dielectric material (formed as an ultra-interlayer dielectric layer). In general, a low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 4, and an ultra-low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 2. Typically, the material is silicon glass (FSG), silicon oxide (silicon oxide), carbon-containing material, porous material (pore-like material) or the like. As an example, the interlayer dielectric layer 202 is a low-k dielectric material that is a porous material containing a porogen, which may be any suitable pore-generating material, which may be a hydrocarbon, a polymer containing the acrylate family of resists, a fluorinated polymer, or the like. Curing may be performed in a furnace or by other processes, such as ultraviolet curing, rapid thermal curing, flash lamp curing, laser curing, and the like.

Next, the interlayer dielectric layer 202 and the etch stop layer 201 are etched to expose the semiconductor substrate 200, forming a trench. A diffusion barrier layer (not shown) and a copper metal layer 203 are sequentially formed in the trench, wherein the diffusion barrier layer is formed by Physical Vapor Deposition (PVD), and the diffusion barrier layer is formed at a temperature between-40 ℃ and 400 ℃ and a pressure between about 0.1 mTorr and 200 mTorr. The diffusion barrier layer is made of metal or metal compound layer such as tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, alloy thereof or composition thereof. In addition, the diffusion barrier layer may also include multiple layers. Preferably, a cobalt (Co) enhancement layer (not shown) is formed on the diffusion barrier layer, and then a copper seed layer (not shown) is formed. The cobalt enhancement layer can improve electromigration resistance while effectively enhancing copper fill capability in smaller geometry trenches/structures. The copper metal layer 203 is formed on the copper seed layer by electrochemical plating, and a stable plating process can be maintained by the instant analysis of the water bath composition and replenishment of organic and inorganic species, wherein the preferred copper plating chemical additives and current waveforms can accomplish gap filling of 0.07um to 0.1 um.

Then, a Chemical Mechanical Polishing (CMP) process is performed to process the copper layer 203 to remove the excess copper layer until the interlayer dielectric layer 202 is exposed, and the CMP is stopped when the copper layer 203 is flush with the top of the interlayer dielectric layer 202. The surface of the copper metal layer 203 is oxidized to form copper oxide due to air oxidation. Using ammonia (NH)₃) Or nitrogen (N)₂) Plasma treatment of the copper metal layer 203 with ammonia (NH) gas₃) Or nitrogen (N)₂) And reducing the copper oxide in the interconnection structure, and finally removing the copper oxide in the interconnection structure. As an example, ammonia (NH) is used₃) The copper metal layer is processed by plasma, the flow rate of the gas is 200-200 cubic centimeters per minute (sccm), the pressure in the reaction chamber can be 5-20 millitorr (mTorr), the power is 900-1200W, and the processing time of the plasma is 5-20 s.

Next, step S103 is performed, as shown in fig. 2C, a capping layer 204 is formed on the surface of the copper interconnect structure 203 and the interlayer dielectric layer 202, wherein the capping layer includes an ion-doped AlN layer.

Illustratively, the formation process of the capping layer 204 may employ any technique known to those skilled in the art, such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), etc. As an example, the deposition process is preferably performed using Atomic Layer Deposition (ALD). In the ALD process, only a thin film with a single atomic layer thickness is deposited in each growth period, and although the ALD speed is slow, large-area uniform growth and good step coverage capability can be realized, and the content of impurities for forming the thin film is low.

Specifically, the deposition temperature is 350 ℃, the pressure in the chamber is 3Torr, and the flow rate of the reactant gas is controlled to be 200-500 sccm. Firstly, introducing AlCH₃The gas is 0.5-2 s. Then, Ar gas 6s is introduced to flush the reaction chamber and carry away excess reaction gas to isolate the reactants. Then introducing GeH₄Gas 15 s. Then, Ar gas 6s was introduced to isolate the reactants. Then, NH is introduced₃/N₂Gas 20 s. Then, Ar gas 6s was introduced to isolate the reactants. This completes a reaction cycle. By controlling GeH in each reaction period₄The flow rate of the gas or the sputtering time controls the doping concentration of Ge in the grown AlGeN layer 204 a. Illustratively, when GeH is introduced₄The AlGeN layer 204a obtained in this reaction cycle had a thickness of 0.73A with a Ge doping concentration of 8.5 atom% for a gas time of 15 s. AlG for generating target thicknessAfter the eN layer 204a, GeH can be introduced₄The reaction was continued for a gas time of 0s to produce the AlN layer 204 b. Illustratively, AlN layer 204b obtained in one reaction cycle has a thickness of 0.46 angstroms. This cycle is repeated a certain number of times to obtain the AlN layer 204b of the target thickness. Illustratively, the doping concentration of the Ge ions gradually decreases from bottom to top. Illustratively, the ion-doped AlN layer 204a has a thickness 1/2-2/3 of the total thickness of the cap layer 204. As an example, the AlGeN layer 204a has a thickness of about 2/3 a and the AlN layer 204b has a thickness of about 1/3 a.

Next, as shown in fig. 2D, a step of performing an annealing process on the capping layer 204 is further included after forming the capping layer 204. As an example, the annealing temperature is 300 to 400 ℃. After annealing, a CuGe-AlN alloy layer 204c is formed between the copper interconnection metal layer 203 and the capping layer 204, and the bonding strength of the capping layer 204 can be effectively improved by the combination of CuGe-AlN. Meanwhile, compared with the Si doping, Ge doping ions have lower diffusivity relative to copper, and CuGe has lower resistivity, so that the performance of the device is improved. The doping concentration of Ge in the covering layer is gradually reduced from bottom to top, so that the balance between the reduction of resistivity and the improvement of electromigration is realized. According to the method disclosed by the invention, the performance of the copper interconnection structure can be obviously improved.

After the annealing step, as shown in fig. 2E, a step of forming a dielectric cap layer 205 on the cap layer 204 is further included. Illustratively, the material of the dielectric cap layer 205 comprises carbon-doped silicon nitride or silicon nitride, preferably a silicon nitride material. Which can prevent copper from diffusing into the surrounding low-k interlayer dielectric layer, the adhesion, physical properties and electrical properties of the dielectric capping layer are very important for the airtightness, internal stress, elastic modulus, etc. of the underlying low-k interlayer dielectric layer and metal layer and for reliability. As an example, the dielectric capping layer has a compressive stress with a thickness in the range of 100 angstroms to 500 angstroms.

[ example two ]

The structure of the semiconductor device provided by the embodiment of the invention is described below with reference to fig. 2E. The semiconductor device comprises a semiconductor substrate 200, an interlayer dielectric layer 202 formed on the semiconductor substrate 200, a copper interconnection structure 203 positioned in the interlayer dielectric layer 202, and a covering layer 204 formed on the surfaces of the copper interconnection structure 203 and the interlayer dielectric layer 202. Wherein:

the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, the material of the semiconductor substrate 200 is monocrystalline silicon. An isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, is also formed in the semiconductor substrate 200, and divides the semiconductor substrate 200 into different active regions, in which various semiconductor devices, such as NMOS and PMOS, etc., can be formed. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawing for simplicity. An etch stop layer 201, which is made of carbon-containing silicon Nitride (NDC), is also formed on the semiconductor substrate 200.

The material of the interlayer dielectric layer 202 may be a low-k dielectric material (formed as an interlayer dielectric layer) or an ultra-low-k dielectric material (formed as an ultra interlayer dielectric layer). In general, a low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 4, and an ultra-low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 2. As one example, the interlayer dielectric layer 202 is a low-k dielectric material that is a porous material.

The copper interconnect structure 203 is a copper metal layer.

The cap layer 204 includes an ion-doped AlN layer 204 a. The doped ions comprise Ge, the thickness of the AlGeN layer 204a formed by doping the Ge ions is 1/2-2/3 of the total thickness of the covering layer 204, and the doping concentration of the Ge ions is gradually reduced from bottom to top. As an example, the AlGeN layer 204a has a thickness of about 2/3 a and the AlN layer 204b has a thickness of about 1/3 a.

A CuGe-AlN alloy layer 204c is also formed between the copper interconnect structure 203 and the capping layer 204. The bond strength of the cap layer 204 can be effectively improved by the combination of CuGe-AlN. Meanwhile, compared with the Si doping, Ge doping ions have lower diffusivity relative to copper, and CuGe has lower resistivity, so that the performance of the device is improved.

A dielectric cap layer 205 is also formed on the cap layer 204. Illustratively, the material of the dielectric cap layer 205 comprises carbon-doped silicon nitride or silicon nitride, preferably a silicon nitride material.

According to the semiconductor device provided by the invention, in the process of a metal interconnection process, the ion-doped AlN layer is formed on the surface of the copper interconnection structure to serve as the covering layer, so that the problems of leakage current and time-lapse breakdown are avoided, the electromigration phenomenon is improved, and the reliability of the semiconductor device is improved.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:

providing a semiconductor substrate;

forming a covering layer on the surfaces of the copper interconnection structure and the interlayer dielectric layer, wherein the covering layer comprises an ion-doped AlN layer, the doped ions comprise Ge, and the doping concentration of Ge ions is gradually reduced from bottom to top;

and performing annealing treatment on the covering layer to form a CuGe-AlN alloy layer between the copper interconnection structure and the covering layer.

2. The method of claim 1, wherein the capping layer is formed using an atomic deposition process.

3. The method of claim 1, wherein the source gas for forming the AlN layer comprises AlCH₃。

4. The method of claim 1, wherein the source gas for performing the Ge ion doping comprises GeH₄。

5. The method of claim 1, wherein the cap layer further comprises an undoped AlN layer located over the ion-doped AlN layer.

6. The method of claim 5, wherein the ion-doped AlN layer has a thickness of 1/2-2/3 of the total thickness of the covering layer.

7. The method of claim 1, further comprising the step of plasma treating the surface of the copper interconnect structure to remove copper oxide prior to forming the capping layer.

8. A semiconductor device, comprising:

a semiconductor substrate;

the covering layer is formed on the surfaces of the copper interconnection structure and the interlayer dielectric layer, the covering layer comprises an ion-doped AlN layer, the doped ions comprise Ge, and the doping concentration of Ge ions is gradually reduced from bottom to top;

and a CuGe-AlN alloy layer is also formed between the copper interconnection structure and the covering layer.

9. The device of claim 8, wherein the cap layer further comprises an undoped AlN layer located over the ion-doped AlN layer, wherein the ion-doped AlN layer has a thickness 1/2-2/3 of the total thickness of the cap layer.