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CN108696959B - Driver of light emitting diode - Google Patents

Driver of light emitting diode Download PDF

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Publication number
CN108696959B
CN108696959B CN201710230057.4A CN201710230057A CN108696959B CN 108696959 B CN108696959 B CN 108696959B CN 201710230057 A CN201710230057 A CN 201710230057A CN 108696959 B CN108696959 B CN 108696959B
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field effect
electron mobility
current
voltage
layer
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CN108696959A (en
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童建凯
吴长协
谢明勋
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Epistar Corp
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30Driver circuits
    • H05B45/37Converter circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

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Abstract

本发明公开一种发光二极管的驱动器,用以驱动一发光元件,包含有一整流电路、一电流驱动电路,以及一保护电路。整流电路包含一整流二极管,用以接收一交流输入电源并转换成一直流电源,直流电源包含一直流电流及一直流电压。电流驱动电路包含一定电流单元,其中整流电路、电流驱动电路与发光元件三者串联,电流驱动电路用以限制直流电流的大小以驱动发光元件。保护电路包含一保护单元,其中,保护电路跨接电流驱动电路与发光元件,当直流电压大于一定值时,直流电流流向保护电路;其中,整流二极管、定电流单元和保护单元共用一基底。

Figure 201710230057

The invention discloses a driver for a light-emitting diode, which is used for driving a light-emitting element, comprising a rectifier circuit, a current driving circuit, and a protection circuit. The rectifier circuit includes a rectifier diode for receiving an AC input power and converting it into a DC power source. The DC power source includes a DC current and a DC voltage. The current driving circuit includes a certain current unit, wherein the rectifying circuit, the current driving circuit and the light-emitting element are connected in series, and the current driving circuit is used to limit the magnitude of the direct current to drive the light-emitting element. The protection circuit includes a protection unit, wherein the protection circuit is connected across the current driving circuit and the light-emitting element, and when the DC voltage is greater than a certain value, the DC current flows to the protection circuit; wherein the rectifier diode, the constant current unit and the protection unit share a substrate.

Figure 201710230057

Description

发光二极管的驱动器LED driver

技术领域technical field

本发明涉及发光二极管的驱动器,尤其是涉及一种具有保护单元的发光二极管的驱动器。The present invention relates to a driver of a light emitting diode, in particular to a driver of a light emitting diode with a protection unit.

背景技术Background technique

近年来,因为良好的电光转换效率以及较小的产品体积,发光二极管(light-emitting diode)已经渐渐地取代阴极灯管或是钨丝,作为背光或是照明系统的光源。只是,因为发光二极管的电压电流特性(约3伏特,直流电驱动),一般市电的交流输入电源并无法直接驱动发光二极管,而是需要一电源转换器,将交流输入电源转换成适当的直流电源。In recent years, light-emitting diodes (light-emitting diodes) have gradually replaced cathode lamps or tungsten filaments as light sources for backlights or lighting systems due to their good electro-optical conversion efficiency and small product volume. However, because of the voltage and current characteristics of light-emitting diodes (about 3 volts, DC drive), the AC input power of the general mains cannot directly drive the light-emitting diodes, but a power converter is required to convert the AC input power into an appropriate DC power supply. .

照明用电往往占用市电供电非常大的部分。因此针对照明所用的电源转换器,法规上除了要求有非常低的转换损失之外,还必须提供有良好的功率因数(功率因数介于0到1之间)。一电子装置的功率因数愈靠近1,表示该电子装置越接近电阻式负载。Lighting electricity often occupies a very large part of the mains power supply. Therefore, for power converters used in lighting, in addition to very low conversion losses, the regulations must also provide a good power factor (power factor between 0 and 1). The closer the power factor of an electronic device is to 1, the closer the electronic device is to a resistive load.

图1为现有的照明系统10,其中有桥式整流器12、功率因数校正器(power factorcorrector)14、LED驱动电路16、以及一LED 18。功率因数校正器14可以是一个升压电路(booster),LED驱动电路16可以是一降压电路(buck converter)。但是,如升压电路或是降压电路般的切换式电源转换器,不但需要用到体积庞大且昂贵的电感元件,整个系统架构也需要使用非常多的电子零件。因此,采用切换式电源转换器的照明系统,因其生产成本高昂比较没有市场竞争力。FIG. 1 shows a conventional lighting system 10 , which includes a bridge rectifier 12 , a power factor corrector 14 , an LED driver circuit 16 , and an LED 18 . The power factor corrector 14 may be a booster circuit, and the LED driving circuit 16 may be a buck converter. However, switching power converters such as boost circuits or buck circuits require not only bulky and expensive inductive components, but also a large number of electronic components for the entire system architecture. Therefore, lighting systems using switching power converters are relatively uncompetitive in the market due to their high production costs.

发明内容SUMMARY OF THE INVENTION

实施例公开一种驱动器,用以驱动一发光元件,包含有一整流电路以及一电流驱动电路。整流电路包含一整流二极管,电连接至一交流输入电源,用以产生一直流电源,跨于一直流电源线与一接地线之间。电流驱动电路包含一定电流源。该定电流源与该发光元件串接于直流电源线与接地线之间。该定电流源可提供一定电流,驱动该发光元件。整流二极管与定电流源,共同形成于一单一半导体芯片上。The embodiment discloses a driver for driving a light-emitting element, which includes a rectifier circuit and a current driving circuit. The rectifier circuit includes a rectifier diode, which is electrically connected to an AC input power source for generating a DC power source, and spans between the DC power source wire and a ground wire. The current drive circuit includes a certain current source. The constant current source and the light-emitting element are connected in series between the DC power line and the ground line. The constant current source can provide a certain current to drive the light-emitting element. The rectifier diode and the constant current source are jointly formed on a single semiconductor chip.

实施例公开一种驱动器,用以驱动一发光元件,包含有一整流电路、一电流驱动电路,以及一保护电路。整流电路包含一整流二极管,用以接收一交流输入电源并转换成一直流电源,整流电路与该发光元件串联,直流电源用以提供一直流电流及一直流电压。电流驱动电路包含一定电流单元,其中整流电路、电流驱动电路与发光元件三者串联,电流驱动电路用以限制直流电流的大小以驱动发光元件。保护电路包含一保护单元,其中,保护电路跨接电流驱动电路与发光元件,并与整流电路串联,当直流电压大于一定值时,直流电流流向保护电路;其中,整流二极管、定电流单元和保护单元,共同形成于一半导体芯片上。The embodiment discloses a driver for driving a light-emitting element, including a rectifier circuit, a current driving circuit, and a protection circuit. The rectifier circuit includes a rectifier diode for receiving an AC input power and converting it into a DC power source, the rectifier circuit is connected in series with the light-emitting element, and the DC power source is used for providing a DC current and a DC voltage. The current driving circuit includes a certain current unit, wherein the rectifier circuit, the current driving circuit and the light-emitting element are connected in series, and the current driving circuit is used to limit the magnitude of the direct current to drive the light-emitting element. The protection circuit includes a protection unit, wherein the protection circuit is connected across the current drive circuit and the light-emitting element, and is connected in series with the rectifier circuit. When the DC voltage is greater than a certain value, the DC current flows to the protection circuit; wherein the rectifier diode, the constant current unit and the protection circuit Units are collectively formed on a semiconductor chip.

附图说明Description of drawings

图1为现有的照明系统的示意图;1 is a schematic diagram of an existing lighting system;

图2为本申请一实施例的LED驱动器的示意图;FIG. 2 is a schematic diagram of an LED driver according to an embodiment of the application;

图3为三个电压波形的示意图;3 is a schematic diagram of three voltage waveforms;

图4A为一半导体芯片上的一金属层的图案的示意图;4A is a schematic diagram of a pattern of a metal layer on a semiconductor chip;

图4B为将图4A的半导体芯片封装后的一集成电路示意图;4B is a schematic diagram of an integrated circuit after the semiconductor chip of FIG. 4A is packaged;

图5为图4A中的高电子迁移率场效晶体管T1沿着线ST-ST的剖视图;5 is a cross-sectional view of the high electron mobility field effect transistor T1 in FIG. 4A along the line ST-ST;

图6为图4A中的二极管DVF3沿着线SD-SD的剖视图;6 is a cross-sectional view of diode DVF3 in FIG. 4A along line SD-SD;

图7为本申请一实施例的一照明系统的示意图;7 is a schematic diagram of a lighting system according to an embodiment of the application;

图8为本申请另一实施例的LED驱动器的示意图;8 is a schematic diagram of an LED driver according to another embodiment of the present application;

图9A为另一半导体芯片上的一金属层的图案的示意图;9A is a schematic diagram of a pattern of a metal layer on another semiconductor chip;

图9B为将图9A的半导体芯片封装后的一集成电路示意图;9B is a schematic diagram of an integrated circuit after the semiconductor chip of FIG. 9A is packaged;

图10为本申请另一实施例的一照明系统的示意图;10 is a schematic diagram of a lighting system according to another embodiment of the present application;

图11为LED与额外的一稳压电容相并联的电路图;Figure 11 is a circuit diagram of an LED connected in parallel with an additional voltage-stabilizing capacitor;

图12为另一半导体芯片上的一金属层的图案的示意图;12 is a schematic diagram of a pattern of a metal layer on another semiconductor chip;

图13为图4A中的二极管DVF3沿着线SD-SD的依据另一种实施例的芯片剖视图;13 is a cross-sectional view of a chip according to another embodiment of the diode DVF3 of FIG. 4A along the line SD-SD;

图14为可以用来制作图13中的二极管的流程图;Figure 14 is a flow chart that may be used to make the diode of Figure 13;

图15为本申请一实施例的金属氧化物半导体场效晶体管(MOSFET)与高电子迁移率场效晶体管中IDS对VDS关系的示意图;15 is a schematic diagram illustrating the relationship between I DS and V DS in a metal oxide semiconductor field effect transistor (MOSFET) and a high electron mobility field effect transistor according to an embodiment of the present application;

图16为本申请另一实施例的LED驱动器的示意图;16 is a schematic diagram of an LED driver according to another embodiment of the present application;

图17为本申请一实施例的一半导体芯片上的一金属层的图案的示意图;17 is a schematic diagram of a pattern of a metal layer on a semiconductor chip according to an embodiment of the application;

图18为将图17的半导体芯片封装后的一集成电路的示意图;FIG. 18 is a schematic diagram of an integrated circuit after the semiconductor chip of FIG. 17 is packaged;

图19为采用图18中的集成电路实现的一照明系统的示意图;FIG. 19 is a schematic diagram of a lighting system implemented using the integrated circuit in FIG. 18;

图20为本申请一实施例的一LED驱动器的电路设计的示意图;20 is a schematic diagram of a circuit design of an LED driver according to an embodiment of the application;

图21为本申请又一实施例的一LED驱动器,具有多个LED的示意图;21 is a schematic diagram of an LED driver having a plurality of LEDs according to yet another embodiment of the application;

图22为本申请一实施例的一二极管芯片的剖视图;22 is a cross-sectional view of a diode chip according to an embodiment of the application;

图23为本申请另一实施例的LED驱动器的示意图;23 is a schematic diagram of an LED driver according to another embodiment of the present application;

图24为一桥式整流器的示意图;Figure 24 is a schematic diagram of a bridge rectifier;

图25举例显示一半导体芯片,其可以实现图24中的桥式整流器的示意图;FIG. 25 illustrates a schematic diagram of a semiconductor chip that can implement the bridge rectifier in FIG. 24;

图26A、图26B与图26C为半导体芯片808沿着线CSV1-CSV1、CSV2-CSV2与CSV3-CSV3的芯片剖视图;26A, 26B and 26C are chip cross-sectional views of the semiconductor chip 808 along lines CSV1-CSV1, CSV2-CSV2 and CSV3-CSV3;

图27为另一桥式整流器的示意图;Figure 27 is a schematic diagram of another bridge rectifier;

图28举例显示一半导体芯片,其可以实现图27中的桥式整流器的示意图;FIG. 28 illustrates a schematic diagram of a semiconductor chip that can implement the bridge rectifier in FIG. 27;

图29A为在一半导体芯片上的一增强模式高电子迁移率场效晶体管ME与一耗尽模式的高电子迁移率场效晶体管MD的示意图;29A is a schematic diagram of an enhancement mode high electron mobility field effect transistor ME and a depletion mode high electron mobility field effect transistor MD on a semiconductor chip;

图29B为图29A中高电子迁移率场效晶体管MD与ME之间的电连接的示意图;29B is a schematic diagram of the electrical connection between the high electron mobility field effect transistor MD and ME in FIG. 29A;

图30为图29A中,沿着线CSV4-CSV4的芯片剖视图;30 is a cross-sectional view of the chip along the line CSV4-CSV4 in FIG. 29A;

图31为本申请一实施例的一LED驱动器的示意图;31 is a schematic diagram of an LED driver according to an embodiment of the application;

图32为图31中的交流输入电源的电压波形以及流经桥式整流器844的一电流波形的示意图;32 is a schematic diagram of the voltage waveform of the AC input power supply in FIG. 31 and a current waveform flowing through the bridge rectifier 844;

图33为具有正温度系数的一热敏电阻的一LED驱动器的示意图;33 is a schematic diagram of an LED driver with a thermistor having a positive temperature coefficient;

图34为具有负温度系数的一热敏电阻的一LED驱动器的示意图;34 is a schematic diagram of an LED driver with a thermistor having a negative temperature coefficient;

图35为具有热敏电阻的另一LED驱动器的示意图;35 is a schematic diagram of another LED driver with a thermistor;

图36A为本申请一实施例的LED驱动器的示意图;36A is a schematic diagram of an LED driver according to an embodiment of the application;

图36B为本申请另一实施例的LED驱动器的示意图;36B is a schematic diagram of an LED driver according to another embodiment of the present application;

图37为高电子迁移率场效晶体管的电压电流关系图;37 is a voltage-current relationship diagram of a high electron mobility field effect transistor;

图38为本申请另一实施例的LED驱动器的上视图;FIG. 38 is a top view of an LED driver according to another embodiment of the application;

图39为图38中的萧基特二极管、高电子迁移率场效晶体管与保护单元的结构剖面示意图。FIG. 39 is a schematic cross-sectional view of the structure of the Schottky diode, the high electron mobility field effect transistor and the protection unit in FIG. 38 .

符号说明Symbol Description

10照明系统 12桥式整流器10 Lighting System 12 Bridge Rectifier

14功率因数校正器 16LED驱动电路14 power factor corrector 16 LED drive circuit

18、18B、18R LED 19稳压电容18, 18B, 18R LED 19 voltage regulator capacitor

60、60a、60b、60c LED驱动器 62桥式整流器60, 60a, 60b, 60c LED Drivers 62 Bridge Rectifiers

63保护电路 64填谷电路63 Protection circuit 64 Valley filling circuit

66电流驱动电路 67虚线66 Current drive circuit 67 Dotted line

72、74、76电压波形 80半导体芯片72, 74, 76 voltage waveforms 80 semiconductor chips

90a半导体叠层 91、92 基底90a Semiconductor stack 91, 92 Substrate

94缓冲层 95、95a平台区94 buffer layer 95, 95a platform area

96通道层 98高价带间隙层96 channel layer 98 high valence band gap layer

100盖层 102金属层100 cap layer 102 metal layer

102a、102b、102c、102d、102e 金属片102a, 102b, 102c, 102d, 102e Metal sheet

102'a、102'b、102'c、102'd、102'e、102'f 金属片102'a, 102'b, 102'c, 102'd, 102'e, 102'f sheet metal

103、103a、103b、103c绝缘层 104金属层103, 103a, 103b, 103c insulating layer 104 metal layer

104a、104'a、104b、104c、104d、104e、104f、104g、104h 金属片104a, 104'a, 104b, 104c, 104d, 104e, 104f, 104g, 104h Metal Sheet

105护层 120 二极管符号105 Sheath 120 Diode Symbol

130集成电路 140、142、144、146、148步骤130 Integrated circuits 140, 142, 144, 146, 148 steps

150、152曲线 170调整区150, 152 curve 170 adjustment area

200 照明系统 300LED驱动器200 Lighting System 300LED Driver

302电流驱动电路 330 照明系统302 Current Drive Circuit 330 Lighting System

500LED驱动器 502 桥式整流器500LED Driver 502 Bridge Rectifier

504电流驱动电路 518、5181、5182、5183LED504 current drive circuit 518, 5181, 5182, 5183LED

5201、5202、5203、5204LED段 550半导体芯片5201, 5202, 5203, 5204 LED segment 550 semiconductor chip

552集成电路 560照明系统552 Integrated Circuit 560 Lighting System

600LED驱动器 700LED驱动器600LED driver 700LED driver

800 LED驱动器 802 双向可控硅调光器800 LED Driver 802 Triac Dimmer

806 桥式整流器 808 半导体芯片806 Bridge Rectifier 808 Semiconductor Chip

810 桥式整流器 812 半导体芯片810 Bridge Rectifier 812 Semiconductor Chip

840 LED驱动器 848 LED840 LED Driver 848 LED

850 电阻 852 萧特基二极管850 Resistor 852 Schottky Diode

900LED驱动器 902、906热敏电阻900LED driver 902, 906 thermistor

910 LED驱动器 A接点910 LED driver A contact

Aclamp保护单元的阳极 Asbd1~sbd4萧基特二极管的阳极A anode of clamp protection unit A anode of sbd1~sbd4 Schottky diode

AC-source交流输入电源 AC+、AC交流输入接脚AC-source AC input power AC+, AC AC input pins

AC1、AC2交流电源线 ARM1、ARM2上臂AC1, AC2 AC power cord ARM1, ARM2 upper arm

ART、ARB上下两臂 C接点ART, ARB upper and lower arms C contact

Cclamp保护单元的阴极 Csbd1~sbd4萧基特二极管的阴极Cathode of C clamp protection unit C sbd1~sbd4 Cathode of Schottky diode

C1、C2、CF电容 CC1、CC2、CC3、CC4电流开关C1, C2, CF capacitor CC1, CC2, CC3, CC4 current switch

DB1、DB2、DB3、DB4整流二极管 DVF1、DVF2、DVF3二极管DB1, DB2, DB3, DB4 rectifier diodes DVF1, DVF2, DVF3 diodes

D端点 Dclamp保护单元D terminal D clamp protection unit

Dhemt1、Dhemt2漏极 D1、D2驱动接脚D hemt1 , D hemt2 drain D1, D2 drive pins

E接点 F接点E contact F contact

GD、GE、Ghemt1、Ghemt2栅极 GND接地线GD, GE, G hemt1 , G hemt2 gate GND ground wire

GG栅区域 Ic饱和电流I c saturation current in GG gate region

IDS漏源电流 IDC-IN直流电流I DS drain-source current I DC-IN DC current

IC1、IC2分段电路 L接点IC1, IC2 segment circuit L contact

Lbp型阻障层长度L b p-type barrier length

ME、MD高电子迁移率场效晶体管 N接点ME, MD high electron mobility field effect transistor N contact

Pbp型阻障层P b p type barrier layer

PF1、PF2校正接脚PF1, PF2 correction pins

S端点 Shemt1、Shemt2源极S terminal S hemt1 , S hemt2 source

S1、S2 驱动接脚S1, S2 drive pins

SBD1、SBD2、SBD3、SBD4 萧特基二极管SBD1, SBD2, SBD3, SBD4 Schottky diodes

SS 饱和区SS saturation region

TD1、TD2、TSG 接点TD1, TD2, TSG contacts

Tbp 型阻障层厚度T b p type barrier thickness

T1、T2、T3、T4、T5、T6、T7、T8 高电子迁移率场效晶体管T1, T2, T3, T4, T5, T6, T7, T8 High Electron Mobility Field Effect Transistors

TP1、TP2、TP3 时段TP1, TP2, TP3 period

VAC-IN交流电压 VDC-IN直流电压V AC-IN AC voltage V DC-IN DC voltage

VDS漏源电压 Vknee切点电压V DS drain-source voltage V knee cut-point voltage

VPEAK电压峰值 VCC高电压接脚V PEAK voltage peak VCC high voltage pin

VDD直流电源线 VSS低电压接脚VDD DC power line VSS low voltage pin

具体实施方式Detailed ways

在本说明书中,相同的符号除另有说明外通常表示具有相同或是类似的结构、功能、原理的元件,且为业界具有一般知识能力者可以依据本说明书的教导而推知。为说明书的简洁度考量,相同的符号的元件将不再重述。In this specification, unless otherwise specified, the same symbols generally represent elements having the same or similar structures, functions, and principles, and those with ordinary knowledge in the art can infer them based on the teachings of this specification. For the sake of brevity of the description, elements with the same symbols will not be repeated.

在本申请的一实施例中,整个LED照明系统具有简洁的电路设计,主要元件仅有封装有一单一半导体芯片(chip)的一集成电路、两个电容、以及当作光源的一LED。实施例中的LED照明系统可以不需要连接额外的电感元件。因此,LED照明系统的电路成本将会相当的低。此外,实施例中的LED照明系统也提供了相当优良的功率因数,可以符合大多数规范的要求。In an embodiment of the present application, the entire LED lighting system has a simple circuit design, and the main components are only an integrated circuit packaged with a single semiconductor chip (chip), two capacitors, and an LED used as a light source. The LED lighting system of the embodiment may not need to connect additional inductive elements. Therefore, the circuit cost of the LED lighting system will be quite low. In addition, the LED lighting system of the embodiment also provides a relatively good power factor, which can meet the requirements of most specifications.

图2显示一依据本申请一实施例的LED驱动器60,其可用来驱动LED 18。LED 18可以是一高压LED,由许多微型LED(micro LED)串连在一起所构成。举例来说,在一个实施例中,每个微型LED的正向电压约3.4伏特,而LED 18由10多个微LED串联而成,其等效正向电压Vef-led(forward voltage)约50V。FIG. 2 shows an LED driver 60 that can be used to drive the LEDs 18 according to an embodiment of the present application. The LED 18 may be a high voltage LED formed by connecting a number of micro LEDs (micro LEDs) in series. For example, in one embodiment, the forward voltage of each micro-LED is about 3.4 volts, and the LED 18 is formed by connecting more than 10 micro-LEDs in series, and the equivalent forward voltage V ef-led (forward voltage) is about 50V.

LED驱动器60大致有三部分。连接到交流输入电源(AC-source)的第一部分是桥式整流器62。第二部分是填谷电路(valley-fill circuit)64,做为一功率因数校正器,可以改善整个LED驱动器60的功率因数。第三部分有两个高电子迁移率场效晶体管(highelectron mobility transistor,HEMT)T1与T2,作为电流驱动电路66。高电子迁移率场效晶体管T1与T2可以各自作为一定电流源使用或是并联后作为一可以提供更大电流数值的定电流源。以高电子迁移率场效晶体管T1为例,当其漏源电压(drain-to-source voltage,VDS)足够大时,漏源电流(drain-to-source current,IDS),也就是从漏极流到源极的电流,将大约是一常数,几乎不随VDS而变化关,高电子迁移率场效晶体管T1大致提供一定电流,用以驱动LED 18。The LED driver 60 has roughly three parts. The first part connected to the AC input power supply (AC-source) is the bridge rectifier 62 . The second part is a valley-fill circuit 64 , which acts as a power factor corrector and can improve the power factor of the entire LED driver 60 . The third part has two high electron mobility transistors (HEMTs) T1 and T2 as the current driving circuit 66 . The high electron mobility field effect transistors T1 and T2 can each be used as a constant current source or can be connected in parallel as a constant current source that can provide a larger current value. Taking the high electron mobility field effect transistor T1 as an example, when its drain-to-source voltage (V DS ) is large enough, the drain-to-source current (I DS ), that is, from The current flowing from the drain to the source will be approximately constant and will hardly vary with V DS . The high electron mobility field effect transistor T1 provides approximately a certain current to drive the LED 18 .

桥式整流器62包含有四个整流二极管DB1-DB4。以下将说明,这四个整流二极管可以都是萧特基二极管(Schottky Barrier Diode;SBD)。桥式整流器62将交流输入电源整流,用以产生直流电源,跨于直流电源线VDD与接地线GND之间。其中,交流输入电源包含交流电压VAC-IN,而直流电源包含直流电流IDC-IN与直流电压VDC-IN。举例来说,交流输入电源可以是一般110V或220V的交流市电。The bridge rectifier 62 includes four rectifier diodes DB1-DB4. As will be explained below, the four rectifier diodes may all be Schottky Barrier Diodes (SBD). The bridge rectifier 62 rectifies the AC input power to generate the DC power, which spans between the DC power line VDD and the ground line GND. The AC input power source includes an AC voltage V AC-IN , and the DC power source includes a DC current I DC-IN and a DC voltage V DC-IN . For example, the AC input power supply can be general 110V or 220V AC mains.

填谷电路64电连接于直流电源线VDD与接地线GND之间,包含有三个二极管DVF1-DVF3与电容C1、C2。二极管DVF1-DVF3逆向串接于直流电源线VDD与接地线GND之间。在此实施例中,电容C1与C2的电容值大约相等,但本申请不限于此。理论上,电容C1与C2的电容电压VC1与VC2大约可以被充电到直流电压VDC-IN的电压峰值VPEAK的一半(0.5×VPEAK)。而当交流电压VAC-IN的绝对值低于0.5×VPEAK时,电容C1与C2可以对直流电源线VDD与接地线GND放电。只要电容C1与C2够大,填谷电路64可以使直流电压VDC-IN的最小值大约等于0.5VPEAK,提供足够的直流电压VDC-IN使LED 18持续发光。The valley filling circuit 64 is electrically connected between the DC power line VDD and the ground line GND, and includes three diodes DVF1-DVF3 and capacitors C1 and C2. The diodes DVF1-DVF3 are connected in reverse series between the DC power line VDD and the ground line GND. In this embodiment, the capacitance values of the capacitors C1 and C2 are approximately equal, but the present application is not limited thereto. Theoretically, the capacitor voltages VC1 and VC2 of the capacitors C1 and C2 can be charged to about half of the voltage peak value V PEAK of the DC voltage VDC-IN (0.5×V PEAK ). When the absolute value of the AC voltage V AC-IN is lower than 0.5×V PEAK , the capacitors C1 and C2 can discharge the DC power line VDD and the ground line GND. As long as the capacitors C1 and C2 are large enough, the valley filling circuit 64 can make the minimum value of the DC voltage V DC-IN approximately equal to 0.5V PEAK , providing enough DC voltage V DC-IN to keep the LED 18 emitting light.

高电子迁移率场效晶体管T1与T2都是耗尽模式(depletion mode)晶体管,意味着他们的临界电压(threshold voltage,VTH)都是负值。每个高电子迁移率场效晶体管都具有一栅极(gate)以及二通道极,而这二通道极一般又称为源极(source)与漏极(drain)。每个高电子迁移率场效晶体管T1与T2的栅极(gate)与源极(source)相互短路。以高电子迁移率场效晶体管T1为例,当其漏源电压(drain-to-source voltage,VDS)足够大时,漏源电流(drain-to-source current,IDS),也就是从漏极流到源极的电流,将大约是一常数,几乎与VDS无关。所以,不论高电子迁移率场效晶体管T1或T2,都可以大约当作一定电流源,提供稳定的一定电流来驱动LED 18,使LED 18的发光强度维持一定,不会有闪烁问题。在图2中,高电子迁移率场效晶体管T1驱动LED 18,两者一起作为负载(load),串接在直流电源线VDD与接地线GND之间。图2以虚线67连接了高电子迁移率场效晶体管T2与LED 18,表示高电子迁移率场效晶体管T2可以选择性地联合高电子迁移率场效晶体管T1一同驱动LED 18,稍后将细部说明。Both the high electron mobility field effect transistors T1 and T2 are depletion mode transistors, which means that their threshold voltages (threshold voltage, VTH) are both negative. Each high electron mobility field effect transistor has a gate and two channels, and the two channels are commonly referred to as a source and a drain. The gate and source of each of the high electron mobility field effect transistors T1 and T2 are shorted to each other. Taking the high electron mobility field effect transistor T1 as an example, when its drain-to-source voltage (V DS ) is large enough, the drain-to-source current (I DS ), that is, from The drain-to-source current will be approximately constant, almost independent of V DS . Therefore, regardless of whether the high electron mobility field effect transistor T1 or T2 can be used as a constant current source, it can provide a stable constant current to drive the LED 18, so that the luminous intensity of the LED 18 can be maintained constant without flickering. In FIG. 2, the high electron mobility field effect transistor T1 drives the LED 18, and the two together act as a load and are connected in series between the DC power line VDD and the ground line GND. FIG. 2 connects the high electron mobility field effect transistor T2 and the LED 18 with a dotted line 67, indicating that the high electron mobility field effect transistor T2 can selectively drive the LED 18 together with the high electron mobility field effect transistor T1, which will be detailed later. illustrate.

图3显示交流输入电源的交流电压VAC-IN随时间变化的电压波形72、没有填谷电路64时的直流电源的直流电压VDC-IN随时间变化的电压波形74、以及有填谷电路64时的直流电源的直流电压VDC-IN随时间变化的电压波形76。举例来说,交流输入电压VAC-IN是220VAC,为一正弦波,如同图3所示。电压波形74表示为没有填谷电路64时的虚拟结果。如果没有填谷电路64,桥式整流器62将提供简单的全波整流,所以会将电压波形72中电压值为负的部分,转变成正,如同电压波形74所示。填谷电路64会将电压波形74中的波谷填入,或是使电压波形74中的波谷不再那么的深,如同电压波形76所示。为了叙述上的方便,以下说明有时将采用电压波形74来讲解事件发生的时序。举例来说,电压波形74到达波峰时,代表电压波形72(交流输入电压VAC-IN)到达波峰或是波谷时。3 shows the time-varying voltage waveform 72 of the AC voltage V AC-IN of the AC input power supply, the time-varying voltage waveform 74 of the DC voltage V DC-IN of the DC power supply without the valley filling circuit 64 , and the valley filling circuit Time-varying voltage waveform 76 of the DC voltage V DC-IN of the DC power supply at 64 . For example, the AC input voltage V AC-IN is 220VAC, which is a sine wave, as shown in FIG. 3 . The voltage waveform 74 is represented as a virtual result without the valley fill circuit 64 . Without the valley-fill circuit 64, the bridge rectifier 62 would provide simple full-wave rectification, and so would convert the negative voltage portion of the voltage waveform 72 to positive, as shown by the voltage waveform 74. The valley filling circuit 64 will fill in the valleys in the voltage waveform 74 , or make the valleys in the voltage waveform 74 less deep, as shown by the voltage waveform 76 . For the convenience of description, the following description will sometimes use the voltage waveform 74 to explain the timing of event occurrence. For example, when the voltage waveform 74 reaches a peak, it represents when the voltage waveform 72 (the AC input voltage V AC-IN ) reaches a peak or a valley.

时段TP1从电压波形74大于等于电压波形76开始,直到电压波形74随时间上升直至峰值VPEAK结束。在时段TP1中,LED 18发光的电能将直接来自交流输入电源,所以直流电压VDC-IN的电压波形76等于电压波形74。此时,一旦直流电压VDC-IN大于电容电压VC1与VC2两者的和,电容C1与C2将会被交流输入电源所充电。当电压波形74达峰值VPEAK时,电容电压VC1与VC2大约都会是0.5VPEAKPeriod TP1 begins when voltage waveform 74 is greater than or equal to voltage waveform 76 until voltage waveform 74 rises over time until peak V PEAK ends. During time period TP1, the power to illuminate the LED 18 will come directly from the AC input power source, so the voltage waveform 76 of the DC voltage V DC-IN is equal to the voltage waveform 74 . At this time, once the DC voltage V DC-IN is greater than the sum of the capacitor voltages VC1 and VC2, the capacitors C1 and C2 will be charged by the AC input power. When the voltage waveform 74 reaches the peak value V PEAK , the capacitor voltages VC1 and VC2 are both approximately 0.5V PEAK .

时段TP2从电压波形74由达到峰值VPEAK开始,直到电压波形74下降至一半峰值(1/2VPEAK)为止。在时段TP2中,电压波形74随时间开始下降,而LED 18发光的电能将直接来自交流输入电源,所以电压波形76等于电压波形74。因为电容C1与C2没有充放电,电容电压VC1与VC2都将维持在0.5VPEAKPeriod TP2 begins when the voltage waveform 74 reaches the peak value V PEAK until the voltage waveform 74 drops to half the peak value (1/2V PEAK ). During time period TP2, the voltage waveform 74 begins to drop over time, and the power to illuminate the LED 18 will come directly from the AC input power source, so the voltage waveform 76 is equal to the voltage waveform 74. Because the capacitors C1 and C2 are not charged or discharged, the capacitor voltages VC1 and VC2 will both remain at 0.5V PEAK .

时段TP3从电压波形74低于0.5VPEAK后开始,大约就是电压波形74的波谷出现的时间。在时段TP3内,电容C1会通过二极管DVF3放电,来供电给高电子迁移率场效晶体管T1与LED 18。类似的,电容C2会通过二极管DVF1放电,一样供电给高电子迁移率场效晶体管T1与LED 18。电容电压VC1与VC2将随着时间降低,降低的速度视电容C1与C2的电容值而定。时段TP3终止于电压波形74从波谷反弹后而高于电容电压VC1或VC2时。之后由另一个时段TP1接续。如同图3的电压波形76所示,只要电容C1与C2够大,直流电源就可能提供足够的直流电压VDC-IN使LED 18持续发光。Period TP3 begins after the voltage waveform 74 falls below 0.5V PEAK , which is approximately the time when the valley of the voltage waveform 74 occurs. During the period TP3, the capacitor C1 is discharged through the diode DVF3 to supply power to the high electron mobility field effect transistor T1 and the LED 18. Similarly, the capacitor C2 will discharge through the diode DVF1 to supply power to the high electron mobility field effect transistor T1 and the LED 18 as well. The capacitor voltages VC1 and VC2 will decrease with time, and the rate of decrease depends on the capacitance values of the capacitors C1 and C2. Period TP3 ends when voltage waveform 74 is higher than capacitor voltage VC1 or VC2 after bouncing off the valley. It is then continued by another time period TP1. As shown in the voltage waveform 76 of FIG. 3, as long as the capacitors C1 and C2 are large enough, the DC power supply may provide enough DC voltage V DC-IN to keep the LED 18 lit.

只要电容C1与C2够大,填谷电路64所达到的功率因数,可以符合大多数国家的功率因数要求。As long as the capacitors C1 and C2 are large enough, the power factor achieved by the valley filling circuit 64 can meet the power factor requirements of most countries.

在一实施例中,图2中的整流二极管DB1-DB4、二极管DVF1-DVF3、以及高电子迁移率场效晶体管T1与T2,都共同形成于一单一半导体芯片上。图4A显示一半导体芯片80上的一金属层104的图案,并标示图2中的二极管与高电子迁移率场效晶体管在半导体芯片80上的相对位置。半导体芯片80可以是一以氮化镓为导通通道材料(GaN-based)的单晶微波集成电路(monolithic microwave integrated circuit;MMIC)。在图4A中,每个二极管的元件结构大约都相类似,都是一萧特基二极管,而高电子迁移率场效晶体管T1与T2的元件结构也相类似。图5显示了,图4A中的高电子迁移率场效晶体管T1沿着线ST-ST的芯片剖视图;图6显示了,图4A中的二极管DVF3沿着线SD-SD的芯片剖视图。图中其他的二极管与高电子迁移率场效晶体管的元件结构可以类推而得知。In one embodiment, the rectifier diodes DB1-DB4, the diodes DVF1-DVF3, and the high electron mobility field effect transistors T1 and T2 in FIG. 2 are all formed together on a single semiconductor chip. FIG. 4A shows a pattern of a metal layer 104 on a semiconductor chip 80 and indicates the relative positions of the diode and the high electron mobility field effect transistor in FIG. 2 on the semiconductor chip 80 . The semiconductor chip 80 may be a monolithic microwave integrated circuit (MMIC) using gallium nitride as a conduction channel material (GaN-based). In FIG. 4A , the element structure of each diode is approximately similar, that is, a Schottky diode, and the element structures of the high electron mobility field effect transistors T1 and T2 are also similar. FIG. 5 shows a chip cross-sectional view of the high electron mobility field effect transistor T1 in FIG. 4A along the line ST-ST; FIG. 6 shows a chip cross-sectional view of the diode DVF3 in FIG. 4A along the line SD-SD. The element structures of other diodes and high electron mobility field effect transistors in the figure can be obtained by analogy.

图5的例子中,硅基底92上的缓冲层94可以是掺杂有碳(C-doped)的本质(intrinsic)GaN。通道层96可以是本质(intrinsic)GaN,其上形成有一高价带间隙(high-bandgap)层98,其材料可为本质的AlGaN。盖层100可以是本质GaN。盖层100、高价带间隙层98与通道层96被图案化而成为一平台区95(mesa)。二维电子云(2D-electron gas)可以形成于通道层96内邻接于高价带间隙层98的量子阱(quantum well),作为导电通道。图案化(patterned)的金属层102的材料可以是钛、铝或是这两种材料的叠层。在图5中,金属层102在平台区95的上方形成两个金属片(metal strips)102a、102b,分别跟平台区95形成两个欧姆接触(ohmic contact),使得金属片102a、102b分别作为高电子迁移率场效晶体管T1的源极与漏极。金属层104的材料可以是钛、金或是这两种材料的叠层。举例来说,由下而上,金属层104有一镍层(Ni)、一铜层(Cu)以及一铂层(Pt),其中铂层可以增加稍后形成的护层105彼此之间的粘着度(adhesion),防止在焊垫制作工艺时产生剥离的问题。在其他实施例中,金属层104也可以是镍层(Ni)、金层(Au)以及铂层(Pt)的叠层,或者镍层(Ni)、金层(Au)以及钛层(Ti)的叠层。在图5中,图案化的金属层104形成了金属片104a、104b与104c。金属片104b接触了平台区95的中央上方,形成一萧特基接触(schottky contact),作为高电子迁移率场效晶体管T1的栅极。图5中的104a与104c分别接触了102a、102b,提供高电子迁移率场效晶体管T1的源极与漏极到其他电子元件的电连接。请同时参考图5与图4A,可以发现高电子迁移率场效晶体管T1的栅极(金属片104b),通过金属层104,短路到金属片104a,也短路到高电子迁移率场效晶体管T1的源极。图5的右部分则显示了高电子迁移率场效晶体管T1的等效电路图。金属层104上方有护层105,其材料可以是氮氧化硅(siliconoxinitride,SiON)。护层105被图案化,用来形成封装时所需要的焊垫(bonding pad)。举例来说,图5中,左半边护层105没有盖住的部分,可以焊接至低电压接脚VSS(稍后将解释)的焊线(bonding wire);而右半边护层105没有盖住的部分,可以焊接至驱动接脚D1(稍后将解释)的焊线。In the example of FIG. 5 , the buffer layer 94 on the silicon substrate 92 may be C-doped intrinsic GaN. The channel layer 96 may be intrinsic GaN on which a high-bandgap layer 98 is formed, and the material may be intrinsic AlGaN. The capping layer 100 may be intrinsic GaN. The cap layer 100 , the high valence bandgap layer 98 and the channel layer 96 are patterned to form a mesa 95 (mesa). A two-dimensional electron gas (2D-electron gas) may be formed in a quantum well in the channel layer 96 adjacent to the high-valence bandgap layer 98 as a conductive channel. The material of the patterned metal layer 102 may be titanium, aluminum, or a laminate of these two materials. In FIG. 5 , the metal layer 102 forms two metal strips 102 a and 102 b above the mesa region 95 , and forms two ohmic contacts with the mesa region 95 respectively, so that the metal strips 102 a and 102 b serve as two ohmic contacts respectively. The source and drain of the high electron mobility field effect transistor T1. The material of the metal layer 104 may be titanium, gold or a laminate of these two materials. For example, from bottom to top, the metal layer 104 has a nickel layer (Ni), a copper layer (Cu), and a platinum layer (Pt), wherein the platinum layer can increase the adhesion of the protective layers 105 formed later to each other. Adhesion to prevent peeling problems during the pad fabrication process. In other embodiments, the metal layer 104 may also be a stack of nickel (Ni), gold (Au) and platinum (Pt) layers, or a nickel (Ni), gold (Au) and titanium (Ti) layer ) stack. In FIG. 5, the patterned metal layer 104 forms metal sheets 104a, 104b and 104c. The metal sheet 104b contacts the upper center of the mesa region 95 to form a schottky contact, which serves as the gate of the high electron mobility field effect transistor T1. 104a and 104c in FIG. 5 are in contact with 102a and 102b, respectively, to provide electrical connection between the source and drain of the high electron mobility field effect transistor T1 to other electronic components. Please refer to FIG. 5 and FIG. 4A at the same time, it can be found that the gate (metal sheet 104b) of the high electron mobility field effect transistor T1 is short-circuited to the metal sheet 104a through the metal layer 104, and is also short-circuited to the high electron mobility field effect transistor T1 the source. The right part of FIG. 5 shows the equivalent circuit diagram of the high electron mobility field effect transistor T1. There is a protective layer 105 above the metal layer 104, and the material thereof may be silicon oxynitride (SiON). The protective layer 105 is patterned to form bonding pads required for packaging. For example, in FIG. 5, the left half of the protective layer 105 does not cover the part, which can be soldered to the bonding wire of the low voltage pin VSS (which will be explained later); and the right half of the protective layer 105 is not covered. , which can be soldered to the bond wire of the drive pin D1 (explained later).

为简洁的缘故,图6与图5相同或类似的部分不再累述。图6中,金属层102在平台区95的上方形成两个金属片102c、102d,图案化的金属层104则形成了金属片104d、104e与104f。与图5相类似的,金属片104e可作为一高电子迁移率场效晶体管的栅极。虽然金属片102d可以作为一高电子迁移率场效晶体管的一源极,但金属片102d上没有接触到金属层104。在另一实施例中,金属片102d可以省略而不形成。金属片104f接触平台区95的一部分上表面与一侧壁,形成另一个萧特基接触,可以作为一萧特基二极管,其阴极等效上短路到图6的高电子迁移率场效晶体管的源极。请同时参考图6与图4A。金属片104e,通过金属层104,短路到金属片104f,其为萧特基二极管的阳极。图6的右部分显示了左半部的等效电路连接图,电路行为上等效为一个二极管。图6的右部分同时显示一特别的二极管符号120,来代表图6中的等效电路。二极管符号120也使用于图2中,表示整流二极管DB1-DB4与二极管DVF1-DVF3,每个都是由一高电子迁移率场效晶体管与一萧特基二极管所复合而成的二极管。For the sake of brevity, the same or similar parts of FIG. 6 as those of FIG. 5 are not repeated. In FIG. 6 , the metal layer 102 forms two metal sheets 102 c and 102 d above the platform region 95 , and the patterned metal layer 104 forms the metal sheets 104 d , 104 e and 104 f . Similar to FIG. 5, the metal sheet 104e can be used as the gate of a high electron mobility field effect transistor. Although the metal sheet 102d can be used as a source of a high electron mobility field effect transistor, the metal sheet 102d is not in contact with the metal layer 104 . In another embodiment, the metal sheet 102d may be omitted and not formed. The metal sheet 104f contacts a part of the upper surface and a side wall of the platform region 95 to form another Schottky contact, which can be used as a Schottky diode, the cathode of which is equivalently short-circuited to the high electron mobility field effect transistor of FIG. 6 . source. Please refer to FIG. 6 and FIG. 4A at the same time. Metal sheet 104e, through metal layer 104, is shorted to metal sheet 104f, which is the anode of the Schottky diode. The right part of Figure 6 shows the equivalent circuit connection diagram of the left half, which behaves as a diode. The right part of FIG. 6 also shows a special diode symbol 120 to represent the equivalent circuit in FIG. 6 . Diode symbol 120 is also used in FIG. 2 to represent rectifier diodes DB1-DB4 and diodes DVF1-DVF3, each of which is a composite diode of a high electron mobility field effect transistor and a Schottky diode.

图4B显示将半导体芯片80封装后的一集成电路130,其只有8个接脚(pin),分别是:高电压接脚VCC、校正接脚PF1与PF2、低电压接脚VSS、交流输入接脚AC+与AC-、驱动接脚D1与D2。请参阅图4A,其中也显示了每个接脚,通过焊线(bonding wire),电性短路到由金属层104图案化后所形成的金属片,而这些金属片也提供了半导体芯片80中电子元件相对应的输入或输出端点相互连接。举例来说,驱动接脚D1电连接到高电子迁移率场效晶体管T1的漏极,校正接脚PF1电连接到二极管DVF3的阴极。FIG. 4B shows an integrated circuit 130 after the semiconductor chip 80 is packaged, which has only 8 pins, which are: a high-voltage pin VCC, calibration pins PF1 and PF2, a low-voltage pin VSS, and an AC input pin Pins AC+ and AC-, drive pins D1 and D2. Please refer to FIG. 4A , which also shows that each pin is electrically shorted by a bonding wire to a metal sheet patterned by the metal layer 104 , and these metal sheets are also provided in the semiconductor chip 80 . The corresponding input or output terminals of the electronic components are connected to each other. For example, the drive pin D1 is electrically connected to the drain of the high electron mobility field effect transistor T1, and the correction pin PF1 is electrically connected to the cathode of the diode DVF3.

图7显示依据本申请所实施的一照明系统200。集成电路130固定在印刷电路板202上。通过印刷电路202上的金属线,电容C1电连接于高电压接脚VCC与校正接脚PF1之间,电容C2电连接于低电压接脚VSS与校正接脚PF2之间,LED 18电连接于高电压接脚VCC与驱动接脚D1之间,交流输入接脚AC+与AC-电连接到交流输入电源(交流电压VAC-IN)。通过先前的解说可以了解,图7的照明系统200很简洁的,仅仅用了4个电子零件(两个电容C1与C2、集成电路130与LED 18),就实现了图2中的LED驱动器60。没有昂贵且体积庞大的电感元件,照明系统200成本得以降低,且整个产品体积也可以缩小。FIG. 7 shows a lighting system 200 implemented in accordance with the present application. The integrated circuit 130 is mounted on the printed circuit board 202 . Through the metal wires on the printed circuit 202, the capacitor C1 is electrically connected between the high-voltage pin VCC and the calibration pin PF1, the capacitor C2 is electrically connected between the low-voltage pin VSS and the calibration pin PF2, and the LED 18 is electrically connected to the Between the high voltage pin VCC and the driving pin D1, the AC input pins AC+ and AC- are electrically connected to the AC input power supply (the AC voltage V AC-IN ). It can be understood from the previous explanation that the lighting system 200 in FIG. 7 is very simple, and only uses four electronic components (two capacitors C1 and C2, the integrated circuit 130 and the LED 18) to realize the LED driver 60 in FIG. 2 . . Without expensive and bulky inductive components, the cost of the lighting system 200 can be reduced, and the overall product volume can also be reduced.

图7中,集成电路130的驱动接脚D2(电连接到高电子迁移率场效晶体管T2的漏极),可以视交流电压VAC-IN不同,而决定是否电连接至LED 18。换言之,集成电路130可以选择性地用单一个高电子迁移率场效晶体管(T1),或是用两个高电子迁移率场效晶体管(T1与T2)并联来驱动LED 18发光。举例来说,假定集成电路130中的高电子迁移率场效晶体管T1与T2元件大小都一样,个别可提供大约一样的1u单位定电流。当图7的照明系统200运用于交流输入电源为110VAC时,可以选用正向电压(forward voltage)为50V的LED作为LED18,并且连接驱动接脚D1以及D2一起到LED 18,LED 18此时所消耗的功率约2u×50(=100u)。而当图7的照明系统200运用于交流输入电源为220VAC时,可以选用正向电压为100V的LED作为LED 18,并且单单连接驱动接脚D1到LED 18,并保持驱动接脚D2浮动空接,LED18此时所消耗的功率约1u×100(=100u)。如此,尽管交流输入电源的交流电压VAC-IN不一样,只要选用正向电压不同的LED,LED 18消耗的功率可以大约相同(都大约是100u),那照明系统200所产生的照明亮度就大约也会是相同。换言之,集成电路130不只是适用于220VAC的交流输入电源,也可适用于110VAC的交流输入电源。这对于照明系统200的制造商而言是非常方便的,可以节省照明系统200的零件库存管理成本。In FIG. 7 , the driving pin D2 of the integrated circuit 130 (electrically connected to the drain of the high electron mobility field effect transistor T2 ) can be electrically connected to the LED 18 depending on the AC voltage V AC-IN . In other words, the integrated circuit 130 can selectively use a single high electron mobility field effect transistor (T1), or use two high electron mobility field effect transistors (T1 and T2) in parallel to drive the LED 18 to emit light. For example, assuming that the high electron mobility field effect transistors T1 and T2 in the integrated circuit 130 have the same size, each can provide about the same constant current of 1u. When the lighting system 200 of FIG. 7 is applied to an AC input power supply of 110VAC, an LED with a forward voltage of 50V can be selected as the LED 18, and the driving pins D1 and D2 are connected to the LED 18. At this time, the LED 18 is The power consumed is about 2u×50 (=100u). When the lighting system 200 of FIG. 7 is applied to an AC input power supply of 220VAC, an LED with a forward voltage of 100V can be selected as the LED 18 , and the driving pin D1 is connected to the LED 18 only, and the driving pin D2 is left floating and free. , the power consumed by the LED18 at this time is about 1u×100 (=100u). In this way, although the AC voltage V AC-IN of the AC input power supply is different, as long as LEDs with different forward voltages are selected, the power consumed by the LEDs 18 can be approximately the same (all are approximately 100u), and the illumination brightness generated by the lighting system 200 is equal to It will be about the same. In other words, the integrated circuit 130 is not only suitable for the AC input power of 220VAC, but also suitable for the AC input power of 110VAC. This is very convenient for the manufacturer of the lighting system 200 , and can save the cost of managing the parts inventory of the lighting system 200 .

在图2中,电流驱动电路66连接于LED 18与接地线GND之间,但本申请并不限于此。图8显示另一依据本申请所实施的LED驱动器300,用来驱动LED 18。在图8中,电流驱动电路302具有高电子迁移率场效晶体管T3与T4,高电子迁移率场效晶体管T3与T4的漏极一起电连接到直流电源线VDD,LED 18电连接于接地线GND与电流驱动电路302之间。图9A显示一半导体芯片310上的金属层140的图案,并标示图8中的二极管与高电子迁移率场效晶体管的相对位置。图5也可代表图9A中的高电子迁移率场效晶体管T3沿着线ST-ST的芯片剖视图;图6也可代表图9A中的二极管DVF3沿着线SD-SD的芯片剖视图。图9B显示将半导体芯片310封装后的一集成电路320,其只有8个接脚(pin),分别是:高电压接脚VCC、校正接脚PF1与PF2、低电压接脚VSS、交流输入接脚AC+与AC-、驱动接脚S1与S2。图10显示依据本申请所实施的另一照明系统330,其实现了图8中的LED驱动器300。图8、图9A、图9B与图10,可以参照先前图2、图4A、图4B与图7以及相关的解说,而得知其原理、操作、以及优点,为简洁故,不再累述。In FIG. 2, the current driving circuit 66 is connected between the LED 18 and the ground line GND, but the present application is not limited thereto. FIG. 8 shows another LED driver 300 implemented in accordance with the present application for driving the LEDs 18 . In FIG. 8, the current driving circuit 302 has high electron mobility field effect transistors T3 and T4, the drains of the high electron mobility field effect transistors T3 and T4 are electrically connected to the DC power line VDD together, and the LED 18 is electrically connected to the ground line Between GND and the current drive circuit 302 . FIG. 9A shows the pattern of the metal layer 140 on a semiconductor chip 310 and indicates the relative positions of the diode and the high electron mobility field effect transistor in FIG. 8 . 5 may also represent a chip cross-sectional view of the high electron mobility field effect transistor T3 in FIG. 9A along the line ST-ST; FIG. 6 may also represent a chip cross-sectional view of the diode DVF3 in FIG. 9A along the line SD-SD. FIG. 9B shows an integrated circuit 320 after the semiconductor chip 310 is packaged, which has only 8 pins, which are: high voltage pin VCC, calibration pins PF1 and PF2, low voltage pin VSS, and AC input pin Pins AC+ and AC-, drive pins S1 and S2. FIG. 10 shows another lighting system 330 implemented in accordance with the present application, which implements the LED driver 300 of FIG. 8 . Fig. 8, Fig. 9A, Fig. 9B and Fig. 10, you can refer to the previous Fig. 2, Fig. 4A, Fig. 4B and Fig. 7 and the related explanations to know the principle, operation, and advantages. .

如同图11的实施例所示,额外的一稳压电容19可以与LED 18并联。稳压电容19可以降低LED 18的跨压VLED的变化,甚至增加LED 18在交流输入电源的一周期时间内的工作周期(duty cycle)或发光时间,减少LED 18闪烁(flickering)的可能性。As shown in the embodiment of FIG. 11 , an additional stabilizing capacitor 19 can be connected in parallel with the LED 18 . The voltage stabilizing capacitor 19 can reduce the variation of the voltage VLED of the LED 18, and even increase the duty cycle or light-emitting time of the LED 18 within one cycle of the AC input power supply, thereby reducing the possibility of flickering of the LED 18.

图4A中的图案仅仅是作为一个例子,本申请并不限于此。图12显示另一半导体芯片上的一金属层104的图案。图12大致类似于图4A,为简洁的缘故,彼此相同或类似的部分不再累述。在图4A中,位于每个二极管中间位置的一栅极,都只有通过一个图案化后金属层104的一上臂ARM1连接到其阳极(譬如图6中的金属片104f);位于每个高电子迁移率场效晶体管中间位置的一栅极,也都是通过一个图案化后金属层104的一上臂ARM2连接到其源极(譬如图5中的金属片104a)。然而,在图12中,如同例示的栅区域GG,每个二极管中间位置的栅极,通过图案化后金属层104的上下两臂ART与ARB连接到其阳极;而位于每个高电子迁移率场效晶体管中间位置的一栅极,也都是通过图案化后金属层104的上下两臂连接到其源极。与图4A的设计相较之下,图12中的二极管的上下两臂结构在制作上比较对称,在显影、曝光、外延、蚀刻等制作工艺的过程中比较不易被上下两臂之间的结构压缩空间,(上下两臂的)宽度会比较一致、结构比较不易有破损或者变形;而图4A的结构因为仅有单臂,在制作时容易在制作其他部分时容易造成整个臂宽度不一致的情况,而这种情况也容易导致大电流或者大电压的聚集而造成击穿。因此图12的上下两臂的结构因为整个结构宽度较为一致,也不易受到其他结构影响而变形,使得图12的结构具有较高的击穿电压耐受能力。The pattern in FIG. 4A is only an example, and the present application is not limited thereto. FIG. 12 shows a pattern of a metal layer 104 on another semiconductor chip. FIG. 12 is substantially similar to FIG. 4A, and for the sake of brevity, parts that are the same or similar to each other are not repeated. In FIG. 4A, a gate located in the middle of each diode is only connected to its anode through an upper arm ARM1 of a patterned metal layer 104 (such as the metal sheet 104f in FIG. 6); located in each high electron A gate in the middle of the mobility field effect transistor is also connected to its source through an upper arm ARM2 of a patterned metal layer 104 (eg, the metal sheet 104a in FIG. 5 ). However, in FIG. 12, like the gate region GG illustrated, the gate at the middle position of each diode is connected to its anode through the upper and lower arms ART and ARB of the patterned metal layer 104; A gate in the middle of the field effect transistor is also connected to its source through the upper and lower arms of the patterned metal layer 104 . Compared with the design of FIG. 4A , the structure of the upper and lower arms of the diode in FIG. 12 is relatively symmetrical in fabrication, and is less likely to be affected by the structure between the upper and lower arms during the development, exposure, epitaxy, etching and other fabrication processes. Compressed space, the width (the upper and lower arms) will be more consistent, and the structure is less likely to be damaged or deformed; while the structure in Figure 4A has only a single arm, it is easy to cause the whole arm width to be inconsistent when making other parts. , and this situation is also likely to lead to the accumulation of large current or large voltage and cause breakdown. Therefore, the structures of the upper and lower arms of FIG. 12 are not easily deformed by other structures because the width of the entire structure is relatively consistent, so that the structure of FIG. 12 has a higher breakdown voltage withstand capability.

图5与图6中的剖视图也并非用来限制本申请的保护范围。举例来说,如图13显示图4A中的二极管DVF3沿着线SD-SD依据另一种实施例的芯片剖视图。图13与图6,为简洁的缘故,彼此相同或类似的部分不再累述。与图6不同的,图13中的金属片104e与盖层100之间夹有一绝缘层103,其材料譬如说是氧化硅。绝缘层103的存在也可以增强二极管的击穿电压耐受能力。The cross-sectional views in FIGS. 5 and 6 are not intended to limit the protection scope of the present application. For example, FIG. 13 shows a chip cross-sectional view of the diode DVF3 in FIG. 4A along the line SD-SD according to another embodiment. 13 and FIG. 6, for the sake of brevity, the parts that are the same or similar to each other will not be described again. Different from FIG. 6 , an insulating layer 103 is sandwiched between the metal sheet 104e and the cap layer 100 in FIG. 13 , the material of which is, for example, silicon oxide. The presence of the insulating layer 103 can also enhance the breakdown voltage withstand capability of the diode.

图14显示用来制作图13中的二极管的流程图。步骤140先形成平台区。举例来说,先在缓冲层94上分别形成通道层96、高价带间隙层98、与盖层100。然后以感应式耦合等离子体蚀刻等方式图案化这三层而完成平台区95。步骤142形成欧姆接触。举例来说,分别沉积钛/铝/钛/金做为金属层102,之后对金属层102图案化,形成金属片102a、102b等。步骤144形成绝缘层103。举例来说,先沉积一二氧化硅层,然后将其图案化,剩下的二氧化硅层便成为绝缘层103。步骤146形成萧特基接触与图案化。举例来说,步骤146先依序沉积镍/金/铂作为金属层104,然后对金属层104图案化形成金属片104a、104b、104c等。金属层104与金属层102之间为欧姆接触,但金属层104与平台区95之间则为萧特基接触。步骤148形成护层105,并对之图案化,以形成焊垫开孔。当然,图14的流程图也适用于制作图12中的高电子迁移率场效晶体管。而通过适当的调整,图14中的流程图,也可以用来制作如图4A中的二极管与高电子迁移率场效晶体管,例如省略步骤144,或者加入其他制作工艺。FIG. 14 shows a flow chart for making the diode of FIG. 13 . Step 140 firstly forms a platform area. For example, the channel layer 96 , the high-valence band gap layer 98 , and the cap layer 100 are respectively formed on the buffer layer 94 first. The three layers are then patterned by inductively coupled plasma etching or the like to complete the mesa region 95 . Step 142 forms an ohmic contact. For example, titanium/aluminum/titanium/gold are respectively deposited as the metal layer 102, and then the metal layer 102 is patterned to form metal sheets 102a, 102b, and the like. Step 144 forms the insulating layer 103 . For example, a silicon dioxide layer is first deposited and then patterned, and the remaining silicon dioxide layer becomes the insulating layer 103 . Step 146 forms Schottky contacts and patterning. For example, in step 146, nickel/gold/platinum is sequentially deposited as the metal layer 104, and then the metal layer 104 is patterned to form metal sheets 104a, 104b, 104c, and the like. There is an ohmic contact between the metal layer 104 and the metal layer 102 , but a Schottky contact between the metal layer 104 and the mesa region 95 . Step 148 forms the capping layer 105 and pattern it to form pad openings. Of course, the flow chart of FIG. 14 is also suitable for fabricating the high electron mobility field effect transistor in FIG. 12 . With proper adjustment, the flowchart in FIG. 14 can also be used to fabricate the diode and the high electron mobility field effect transistor in FIG. 4A , for example, step 144 is omitted, or other fabrication processes are added.

虽然图2与图5中的高电子迁移率场效晶体管T1与T2可以视为定电流源,但是其可能不是一个完全理想的电流源。高电子迁移率场效晶体管T1与T2的漏源电流(IDS),在饱和区时,可能依然跟漏源电压(VDS)有些许相关。图15显示了金属氧化物半导体场效晶体管(MOSFET)与高电子迁移率场效晶体管中,IDS对VDS关系。曲线150与152分别是针对以硅为基材的一金属氧化物半导体场效晶体管(MOSFET)以及一高电子迁移率场效晶体管。从曲线150可以发现,在金属氧化物半导体场效晶体管中,IDS与VDS大约都是正相关,也就是VDS越大,IDS越大。但是高电子迁移率场效晶体管则不同。从曲线152可以发现,在高电子迁移率场效晶体管中,当VDS超过一特定值时,IDS与之的关系,会从正相关变成负相关。而这个特定值可以通过制作工艺上的参数,来加以设定。这高电子迁移率场效晶体管的特性有一个特别的好处,当VDS因为市电电压不稳而突然飙高时,IDS反而会下降,可能可以降低消耗于高电子迁移率场效晶体管的电功率,所以避免高电子迁移率场效晶体管被烧毁。Although the high electron mobility field effect transistors T1 and T2 in FIGS. 2 and 5 can be regarded as constant current sources, they may not be completely ideal current sources. The drain-source current (I DS ) of the high electron mobility field effect transistors T1 and T2 may still be somewhat related to the drain-source voltage (V DS ) in the saturation region. Figure 15 shows I DS versus V DS for metal oxide semiconductor field effect transistors (MOSFETs) and high electron mobility field effect transistors. Curves 150 and 152 are for a silicon-based metal oxide semiconductor field effect transistor (MOSFET) and a high electron mobility field effect transistor, respectively. It can be found from the curve 150 that in the MOSFET, I DS and V DS are approximately both positively correlated, that is, the greater the V DS , the greater the I DS . But high electron mobility field effect transistors are different. It can be found from the curve 152 that in the high electron mobility field effect transistor, when V DS exceeds a certain value, the relationship between I DS and it will change from positive correlation to negative correlation. And this specific value can be set through the parameters of the manufacturing process. The characteristics of this high electron mobility field effect transistor have a special advantage. When the V DS suddenly rises due to the unstable mains voltage, the I DS will drop instead, which may reduce the consumption of the high electron mobility field effect transistor. electrical power, so avoid high electron mobility field effect transistors from being burned out.

在先前数个实施例中,LED驱动器有一填谷电路,但本申请并不限于此。图16显示了另一LED驱动器500,用以驱动LED 518,其包含了数个LED段5201、5202、5203串接在一起。LED驱动器500中并没有填谷电路。LED驱动器500中的桥式整流器502与电流驱动电路504可以一起整合在一半导体芯片上,封装成一集成电路。图17显示一半导体芯片550上的一金属层104的图案,并标示图16中的二极管与高电子迁移率场效晶体管在半导体芯片550上的相对位置。半导体芯片550整合了LED驱动器500中的桥式整流器502与电流驱动电路504。图18显示将半导体芯片550封装后的一集成电路552。图19显示采用图18中的集成电路552实现LED驱动器500的一照明系统560。图16至图19可以通过先前的教导而了解,故其细节不在此累述。从图19可以发现整个照明系统560采用了非常少量的电子零件(一电容CF、集成电路552与LED 518)。照明系统560成本将得以降低,且整个产品也更加精简。In the previous embodiments, the LED driver has a valley filling circuit, but the present application is not limited to this. FIG. 16 shows another LED driver 500 for driving an LED 518, which includes several LED segments 5201, 5202, 5203 connected in series. There is no valley filling circuit in the LED driver 500 . The bridge rectifier 502 and the current driving circuit 504 in the LED driver 500 can be integrated together on a semiconductor chip and packaged into an integrated circuit. FIG. 17 shows a pattern of a metal layer 104 on a semiconductor chip 550 , and indicates the relative positions of the diode and the high electron mobility field effect transistor in FIG. 16 on the semiconductor chip 550 . The semiconductor chip 550 integrates the bridge rectifier 502 and the current driving circuit 504 in the LED driver 500 . FIG. 18 shows an integrated circuit 552 after the semiconductor chip 550 is packaged. FIG. 19 shows a lighting system 560 implementing the LED driver 500 using the integrated circuit 552 of FIG. 18 . Figures 16-19 can be learned from the previous teachings, so their details are not repeated here. It can be seen from FIG. 19 that the entire lighting system 560 uses a very small number of electronic components (a capacitor CF, the integrated circuit 552 and the LED 518). The cost of the lighting system 560 will be reduced and the overall product will be more streamlined.

图16与图19并非用来限制集成电路552的应用。图20举例一LED驱动器600,可用以说明包含桥式整流器502与电流驱动电路504的集成电路的另一应用。在图20中,电流驱动电路504中的HMET T1与T2可以选择性地用来驱动LED 518,其包含了数个LED段5201、5202、5203。LED驱动器600另有分段电路IC1与IC2,其可以依据直流电压VDC-IN的高低而成为短路或是开路。举例来说,当直流电压VDC-IN比LED段5203的正向电压略高时,分段电路IC1与IC2都是短路电路,所以LED段5203发光,而LED段5201、5202不发光;当直流电压VDC-IN增加到超过LED段5202与5203的正向电压总和时,分段电路IC1为短路电路,分段电路IC2为开路电路,所以LED段5202与5203发光,而LED段5201不发光;当直流电压VDC-IN再增加到超过LED段5201、5202与5203的正向电压总和时,分段电路IC1也跟着变成开路电路,所以LED段5201、5202与5203都发光。使得LED驱动器600的电光转换效率更好,功率因数与总谐波失真率都能得到良好的控制。16 and 19 are not intended to limit the application of the integrated circuit 552 . FIG. 20 illustrates an LED driver 600 that can be used to illustrate another application of an integrated circuit including a bridge rectifier 502 and a current driver circuit 504 . In FIG. 20 , the HMETs T1 and T2 in the current drive circuit 504 can be selectively used to drive the LED 518 , which includes several LED segments 5201 , 5202 , 5203 . The LED driver 600 further has segmented circuits IC1 and IC2, which can be short-circuited or open-circuited according to the level of the DC voltage V DC-IN . For example, when the DC voltage V DC-IN is slightly higher than the forward voltage of the LED segment 5203, the segment circuits IC1 and IC2 are both short circuits, so the LED segment 5203 emits light, while the LED segments 5201 and 5202 do not emit light; when When the DC voltage V DC-IN increases beyond the sum of the forward voltages of LED segments 5202 and 5203, segment circuit IC1 is a short circuit and segment circuit IC2 is an open circuit, so LED segments 5202 and 5203 emit light, while LED segment 5201 does not. Lighting; when the DC voltage V DC-IN increases to exceed the sum of the forward voltages of the LED segments 5201, 5202 and 5203, the segment circuit IC1 also becomes an open circuit, so the LED segments 5201, 5202 and 5203 all emit light. Therefore, the electro-optical conversion efficiency of the LED driver 600 is better, and the power factor and the total harmonic distortion rate can be well controlled.

依据本申请所实施的一集成电路并不限于只是整合了一桥式整流器与一电流驱动电路。先前所述的集成电路130与552仅仅作为例子。举例来说,依据本申请所实施的一集成电路除了有桥式整流器与电流驱动电路之外,还整合有一些二极管或高电子迁移率场效晶体管,可用于图20中的分段电路IC1与IC2中。An integrated circuit implemented according to the present application is not limited to only integrating a bridge rectifier and a current driving circuit. The previously described integrated circuits 130 and 552 are by way of example only. For example, in addition to the bridge rectifier and the current driving circuit, an integrated circuit implemented according to the present application also integrates some diodes or high electron mobility field effect transistors, which can be used for the segmented circuits IC1 and IC1 in FIG. 20 . IC2.

本申请所实施的集成电路并不只限于耗尽模式的高电子迁移率场效晶体管。在一些实施例中,集成电路包含有增强型模式(enhancement-mode)高电子迁移率场效晶体管,其导通电流可以通过提供适当的栅电压来加以控制,由此改变所驱动的LED段所发出的光强度。例如在图20中利用分段电路IC1与IC2调整启动的LED段5201、5202、5203的同时,可以调整增强型模式高电子迁移率场效晶体管的栅电压以改变高电子迁移率场效晶体管输入到LED段5201、5202、5203的电流,进而改变LED段5201、5202、5203所发出的光强度。The integrated circuits implemented in this application are not limited to depletion mode high electron mobility field effect transistors. In some embodiments, the integrated circuit includes enhancement-mode high electron mobility field effect transistors, the on-current of which can be controlled by supplying an appropriate gate voltage, thereby changing the amount of LED segments being driven. The intensity of light emitted. For example, while the activated LED segments 5201, 5202, 5203 are adjusted using segment circuits IC1 and IC2 in FIG. 20, the gate voltage of the enhancement mode high electron mobility field effect transistor can be adjusted to change the high electron mobility field effect transistor input. The current to the LED segments 5201, 5202, 5203 changes the light intensity emitted by the LED segments 5201, 5202, 5203.

尽管先前所揭示的LED驱动器或是照明系统,每个都是用以驱动单一LED 518,但本申请并不限于此。在一些实施例中,可以有两个或是以上的LED,以不同的电流,分别的被驱动。图21举例一LED驱动器700,其中电流驱动电路504中的高电子迁移率场效晶体管T1与T2,分别驱动LED 18R与18B。举例来说,高电子迁移率场效晶体管T1所提供的驱动电流小于高电子迁移率场效晶体管T2所提供的驱动电流,而LED 18R大致为红光LED,而LED 18B大致为蓝光LED。Although the previously disclosed LED drivers or lighting systems are each used to drive a single LED 518, the present application is not so limited. In some embodiments, two or more LEDs may be driven separately at different currents. FIG. 21 illustrates an LED driver 700 in which the high electron mobility field effect transistors T1 and T2 in the current driving circuit 504 drive the LEDs 18R and 18B, respectively. For example, the driving current provided by the high electron mobility field effect transistor T1 is smaller than the driving current provided by the high electron mobility field effect transistor T2, and the LED 18R is substantially a red LED, and the LED 18B is substantially a blue LED.

图6与图13中的二极管,分别都形成于单一平台区95上,但本申请并不限于此。图22显示另一种实施例中,一二极管的芯片剖视图。图22中与图6以及图13彼此相同或类似的部分,为简洁的缘故,不再累述。图22中有两个平台区95与95a。金属片102e于平台区95a上,形成一欧姆接触;而金属片102d则在于平台区95上,形成另一欧姆接触。金属片102d与102e通过金属片104g,彼此短路电连接。金属片104f作为二极管的一阳极,金属片104d则作为二极管的一阴极。图22中的结构,可以增强二极管的击穿电压耐受能力。The diodes in FIG. 6 and FIG. 13 are respectively formed on a single mesa region 95, but the present application is not limited thereto. FIG. 22 shows a chip cross-sectional view of a diode in another embodiment. Parts in FIG. 22 that are the same as or similar to those in FIG. 6 and FIG. 13 will not be repeated for the sake of brevity. In Figure 22 there are two land areas 95 and 95a. The metal sheet 102e forms an ohmic contact on the mesa region 95a, and the metal sheet 102d forms another ohmic contact on the mesa region 95. The metal sheets 102d and 102e are electrically short-circuited to each other through the metal sheet 104g. The metal piece 104f serves as an anode of the diode, and the metal piece 104d serves as a cathode of the diode. The structure in Figure 22 can enhance the breakdown voltage withstand capability of the diode.

先前所教导的电流驱动电路66、302与504,都用来驱动发光二极管(LED),但本申请并不限于此。图23显示依据本申请另一实施例的LED驱动器800,其与图16相似,彼此之间相同之处,可以参考先前的说明而了解,为简洁的缘故,不再说明。与图16的LED驱动器500不同的,图23中的LED驱动器800多了一双向可控硅调光器(TRIAC dimmer)802,而且电流驱动电路804中的高电子迁移率场效晶体管T1直接连接于直流电源线VDD与接地线GND之间,没有驱动任何LED。当一双向可控硅调光器关闭,大约呈现开路时,需要有一定量的维持电流(holding current),才可以避免误动作发生。在图23中,高电子迁移率场效晶体管T1可以提供双向可控硅调光器802所需要的维持电流。设计上来说,高电子迁移率场效晶体管T2可以提供相对的大电流,使LED 518发光;而高电子迁移率场效晶体管T1可以提供相对的小电流,当LED 518不发光时,当作双向可控硅调光器802所需要的维持电流。The previously taught current drive circuits 66, 302 and 504 are used to drive light emitting diodes (LEDs), but the present application is not so limited. FIG. 23 shows an LED driver 800 according to another embodiment of the present application, which is similar to FIG. 16 , and the similarities with each other can be understood with reference to the previous description, and are not described again for the sake of brevity. Different from the LED driver 500 in FIG. 16 , the LED driver 800 in FIG. 23 has an additional TRIAC dimmer 802, and the high electron mobility field effect transistor T1 in the current driving circuit 804 is directly connected Between the DC power line VDD and the ground line GND, no LED is driven. When a triac dimmer is turned off and appears to be an open circuit, a certain amount of holding current is required to avoid malfunction. In FIG. 23 , the high electron mobility field effect transistor T1 can provide the holding current required by the triac dimmer 802 . In terms of design, the high electron mobility field effect transistor T2 can provide a relatively large current to make the LED 518 emit light; while the high electron mobility field effect transistor T1 can provide a relatively small current, when the LED 518 does not emit light, it is used as a bidirectional The holding current required by the thyristor dimmer 802.

先前实施例中的二极管都是以图6中的二极管符号120表示,其是由一高电子迁移率场效晶体管与一萧特基二极管所复合而成的二极管。但是本申请并不限于此。所有实施例中的二极管,可以全部或是部分替换成其他种二极管。举例来说,图24显示了一桥式整流器806,其以四个萧特基二极管SBD1、SBD2、SBD3、SBD4所构成。The diodes in the previous embodiments are represented by diode symbols 120 in FIG. 6 , which are diodes formed by a combination of a high electron mobility field effect transistor and a Schottky diode. However, the present application is not limited to this. The diodes in all the embodiments can be replaced in whole or in part with other kinds of diodes. For example, FIG. 24 shows a bridge rectifier 806 composed of four Schottky diodes SBD1, SBD2, SBD3, SBD4.

图25举例显示一半导体芯片808上的金属层104与平台区95的图案,其可以实现图24中的桥式整流器806。图26A、图26B与图26C显示半导体芯片808沿着线CSV1-CSV1、CSV2-CSV2与CSV3-CSV3的芯片剖视图。举例来说,图24中的萧基特二极管SBD1连接于交流电源线AC1与接地线GND之间。图25与图26A中显示具有一多指状结构(multi-finger structure)的高电子迁移率场效晶体管。高电子迁移率场效晶体管的栅端做为萧基特二极管SBD1的阳极,高电子迁移率场效晶体管的通道端做为萧基特二极管SBD1的阴极。等效上,萧基特二极管SBD1由许多的小萧基特二极管并联所构成。多指状结构的高电子迁移率场效晶体管可以在有限的芯片面积中,提供较大的驱动电流。FIG. 25 illustrates, by way of example, the pattern of the metal layer 104 and the mesa 95 on a semiconductor chip 808, which can implement the bridge rectifier 806 of FIG. 24. FIG. 26A, 26B, and 26C show chip cross-sectional views of the semiconductor chip 808 along lines CSV1-CSV1, CSV2-CSV2, and CSV3-CSV3. For example, the Schottky diode SBD1 in FIG. 24 is connected between the AC power line AC1 and the ground line GND. 25 and 26A show high electron mobility field effect transistors having a multi-finger structure. The gate terminal of the high electron mobility field effect transistor is used as the anode of the Schottky diode SBD1, and the channel terminal of the high electron mobility field effect transistor is used as the cathode of the Schottky diode SBD1. Equivalently, the Schottky diode SBD1 consists of many small Schottky diodes in parallel. The high electron mobility field effect transistor with multi-finger structure can provide larger driving current in a limited chip area.

在先前的实施例中,每一个二极管,也可以用数个二极管串联来实施,如同图27所举例的。图27显示了另一桥式整流器810。举例来说,在桥式整流器810的交流电源线AC1与接地线GND之间,具有两个串接的萧基特二极管。图28举例显示一半导体芯片812上的金属层104与平台区95的图案,其可以实现图27中的桥式整流器810。图26A、图26B与图26C也可以用以显示半导体芯片812沿着线CSV1-CSV1、CSV2-CSV2与CSV3-CSV3的芯片剖视图。In the previous embodiment, each diode can also be implemented with several diodes connected in series, as exemplified in FIG. 27 . FIG. 27 shows another bridge rectifier 810 . For example, between the AC power line AC1 of the bridge rectifier 810 and the ground line GND, there are two Schottky diodes connected in series. FIG. 28 illustrates, by way of example, the pattern of the metal layer 104 and the mesa region 95 on a semiconductor chip 812, which can implement the bridge rectifier 810 of FIG. 27 . 26A, 26B and 26C can also be used to show chip cross-sectional views of the semiconductor chip 812 along the lines CSV1-CSV1, CSV2-CSV2 and CSV3-CSV3.

如同先前所述的,在本申请的实施例的半导体芯片中,并不限于只能有耗尽模式的高电子迁移率场效晶体管与萧基特二极管,也可以包含有增强模式(enhancement mode,E-mode)的高电子迁移率场效晶体管。图29A显示在一半导体芯片上的一增强模式高电子迁移率场效晶体管ME与一耗尽模式的高电子迁移率场效晶体管MD,两者的金属层104与平台区95的图案。图29B则显示图29A中高电子迁移率场效晶体管MD与ME之间的电连接。图30则显示图29A中,沿着线CSV4-CSV4的芯片剖视图。如同图30所示的,左半边为一增强模式高电子迁移率场效晶体管ME,其中作为栅极GE的金属片104h与盖层100之间夹有一绝缘层103。盖层100与高价带间隙层98在金属片104h下方的部分,形成有一调整区170。举例来说,调整区170可以将氟离子局部地注入盖层100与高价带间隙层98而形成。相较于图22左半部的耗尽模式高电子迁移率场效晶体管MD,图30左半边的增强模式高电子迁移率场效晶体管ME多了调整区170以及绝缘层103,两者都可以用来调整或增加一高电子迁移率场效晶体管的临界电压值Vt(threshold voltage)。As mentioned above, the semiconductor chips of the embodiments of the present application are not limited to the high electron mobility field effect transistors and Schottky diodes that can only have depletion mode, but can also include enhancement mode (enhancement mode, E-mode) high electron mobility field effect transistor. FIG. 29A shows the pattern of the metal layer 104 and the mesa 95 of an enhancement mode high electron mobility field effect transistor ME and a depletion mode high electron mobility field effect transistor MD on a semiconductor chip. FIG. 29B shows the electrical connection between the high electron mobility field effect transistor MD and ME in FIG. 29A. FIG. 30 shows a cross-sectional view of the chip along the line CSV4-CSV4 in FIG. 29A. As shown in FIG. 30 , the left half is an enhancement mode high electron mobility field effect transistor ME, wherein an insulating layer 103 is sandwiched between the metal sheet 104h serving as the gate GE and the cap layer 100 . An adjustment region 170 is formed at the portion of the cap layer 100 and the high-valence bandgap layer 98 below the metal sheet 104h. For example, the adjustment region 170 may be formed by locally implanting fluorine ions into the cap layer 100 and the high-valence bandgap layer 98 . Compared with the depletion mode high electron mobility field effect transistor MD in the left half of FIG. 22 , the enhancement mode high electron mobility field effect transistor ME in the left half of FIG. Used to adjust or increase the threshold voltage Vt (threshold voltage) of a high electron mobility field effect transistor.

如同图29A、图29B与图30所示,耗尽模式高电子迁移率场效晶体管MD的栅极GD,通过金属层104的电连接,短路到增强模式高电子迁移率场效晶体管ME的端点S。As shown in FIGS. 29A , 29B and 30 , the gate GD of the depletion mode high electron mobility field effect transistor MD is short-circuited to the terminal of the enhancement mode high electron mobility field effect transistor ME through the electrical connection of the metal layer 104 S.

图29B中的电路,当高电子迁移率场效晶体管ME关闭(开路)时,高电子迁移率场效晶体管ME与高电子迁移率场效晶体管MD一起,可以承担分散从端点D到端点S之间的跨压,所以可以有相当好的耐压能力。当高电子迁移率场效晶体管ME开启(导通)时,高电子迁移率场效晶体管MD可以作为一个定电流源,限制端点D到端点S之间的最大电流量。In the circuit of FIG. 29B, when the high electron mobility field effect transistor ME is turned off (open circuit), the high electron mobility field effect transistor ME together with the high electron mobility field effect transistor MD can undertake to disperse the distance from the terminal D to the terminal S Therefore, it can have quite good pressure resistance. When the high electron mobility field effect transistor ME is turned on (conducted), the high electron mobility field effect transistor MD can act as a constant current source, limiting the maximum amount of current between the terminal D and the terminal S.

图29A与图29B中的增强模式高电子迁移率场效晶体管也可以作为一半导体芯片中的主动开关。图31显示依据本申请一实施例的一LED驱动器840的电路设计,其具有增强模式高电子迁移率场效晶体管与耗尽模式高电子迁移率场效晶体管。除了一些萧基特二极管与电阻外,LED驱动器840还包含有电流开关CC1、CC2、CC3,以及耗尽模式高电子迁移率场效晶体管T8,彼此的电连接如图31所示。在一半导体芯片上,电流开关CC1、CC2、CC3可以以图29A与图30中的元件结构而实现。在一实施例中,电流开关CC1、CC2、CC3以及耗尽模式高电子迁移率场效晶体管T8,可以导通的最大电流,分别是电流值I1、I2、I3与I4,且I1<I2<I3<I4。每个电流开关CC1、CC2、CC3都有一个控制端(也就是一增强模式高电子迁移率场效晶体管的栅端),通过一个相对应的电阻,共同连接到萧基特二极管852,其具有另一端连接到接地线GND。The enhancement mode high electron mobility field effect transistor in FIGS. 29A and 29B can also be used as an active switch in a semiconductor chip. FIG. 31 shows a circuit design of an LED driver 840 according to an embodiment of the present application, which has an enhancement mode high electron mobility field effect transistor and a depletion mode high electron mobility field effect transistor. In addition to some Schottky diodes and resistors, the LED driver 840 also includes current switches CC1 , CC2 , CC3 , and a depletion mode high electron mobility field effect transistor T8 , the electrical connections of which are shown in FIG. 31 . On a semiconductor chip, the current switches CC1 , CC2 , and CC3 can be implemented with the device structures shown in FIGS. 29A and 30 . In one embodiment, the current switches CC1 , CC2 , CC3 and the depletion mode high electron mobility field effect transistor T8 , the maximum currents that can be turned on are the current values I1 , I2 , I3 and I4 respectively, and I1<I2< I3<I4. Each of the current switches CC1, CC2, CC3 has a control terminal (that is, the gate terminal of an enhancement mode high electron mobility field effect transistor), which is commonly connected to the Schottky diode 852 through a corresponding resistor, which has The other end is connected to the ground wire GND.

图32显示了图31中的交流输入电源的电压波形以及流经桥式整流器844的一电流波形。随着直流电源线VDD到接地线GND之间的跨压从0V开始逐渐升高,电流开关CC1、CC2、CC3会全部开启。此时,只有LED段5201发光,LED段5202、5203、5204都不发光,流经LED段5201的驱动电流被电流开关CC1所限制,最大为电流值I1。随着直流电源线VDD到接地线GND之间的跨压继续升高,电流开关CC1关闭而LED段5202加入发光,此时,流经LED段5201与5202的驱动电流被电流开关CC2所限制,最大为电流值I2。当直流电源线VDD到接地线GND之间的跨压继续升高后,电流开关CC2关闭而LED段5203加入发光,此时,流经LED段5201、5202、5203的驱动电流被电流开关CC3所限制,最大为电流值I3。当直流电源线VDD到接地线GND之间的跨压超过一定程度时,电流开关CC1、CC2、CC3会全部关闭,LED段5201、5202、5203、5204全部都发光。此时,流经LED段5201、5202、5203、5204的驱动电流被耗尽模式高电子迁移率场效晶体管T8所限制,最大为电流值I4。当直流电源线VDD到接地线GND之间的跨压从最高点慢慢下降时,电流开关CC3、CC2、CC1会依序渐渐开启导通。从图32可以发现,图31的LED驱动器840不只是有良好的功率因数(power factor),而且会有相当低的总谐波失真率(total harmonic distortion,THD)。FIG. 32 shows the voltage waveform of the AC input power supply in FIG. 31 and a current waveform flowing through the bridge rectifier 844 . As the voltage across the DC power line VDD to the ground line GND gradually increases from 0V, the current switches CC1, CC2, and CC3 are all turned on. At this time, only the LED segment 5201 emits light, and the LED segments 5202, 5203, and 5204 do not emit light. The driving current flowing through the LED segment 5201 is limited by the current switch CC1, and the maximum is the current value I1. As the cross-voltage between the DC power line VDD and the ground line GND continues to increase, the current switch CC1 is turned off and the LED segment 5202 emits light. At this time, the driving current flowing through the LED segments 5201 and 5202 is limited by the current switch CC2. The maximum is the current value I2. When the cross-voltage between the DC power line VDD and the ground line GND continues to rise, the current switch CC2 is turned off and the LED segment 5203 lights up. Limit, the maximum is the current value I3. When the cross-voltage between the DC power line VDD and the ground line GND exceeds a certain level, the current switches CC1, CC2, and CC3 will all be turned off, and the LED segments 5201, 5202, 5203, and 5204 will all light up. At this time, the driving current flowing through the LED segments 5201 , 5202 , 5203 , and 5204 is limited by the depletion mode high electron mobility field effect transistor T8 , and the maximum is the current value I4 . When the cross-voltage between the DC power line VDD and the ground line GND gradually decreases from the highest point, the current switches CC3, CC2, and CC1 will gradually turn on and conduct in sequence. It can be found from FIG. 32 that the LED driver 840 of FIG. 31 not only has a good power factor, but also has a relatively low total harmonic distortion (THD).

在图31中,对应每个电流开关CC3、CC2、CC1,都有两个反向串接的萧基特二极管,连接于每个电流开关的一控制端与一高压端之间。而在另一个实施例中,这些萧基特二极管(图31中总共有6个)可以省略不做,降低成本。In FIG. 31, corresponding to each current switch CC3, CC2, CC1, there are two Schottky diodes connected in reverse series, connected between a control terminal and a high voltage terminal of each current switch. In another embodiment, these Schottky diodes (there are 6 in total in FIG. 31 ) can be omitted to reduce cost.

连接于电阻850与接地线GND之间的萧基特二极管852,可以用来限定电流开关CC3、CC2、CC1的控制端的最高电压。当突波高压出现在直流电源线VDD上时,萧基特二极管852可以防止一增强模式高电子迁移率场效晶体管因过高栅电压而导致的毁损。The Schottky diode 852 connected between the resistor 850 and the ground line GND can be used to limit the maximum voltage of the control terminals of the current switches CC3, CC2, CC1. The Schottky diode 852 can prevent an enhancement mode high electron mobility field effect transistor from being damaged due to a high gate voltage when a high voltage surge occurs on the DC power line VDD.

图31中的LED驱动器840中,所有的萧基特二极管以及高电子迁移率场效晶体管,都可以整合于一以氮化镓为导通通道材料(GaN-based)的单晶微波集成电路。举例来说,萧基特二极管可以用图6或是图26A中的元件结构来实现,而增强模式高电子迁移率场效晶体管与耗尽模式高电子迁移率场效晶体管可以分别用图30中的左半部与右半部的元件结构来实现。换言之,实现LED驱动器840时,可能只需要一单晶微波集成电路、一些电阻元件、一LED 848以及一印刷电路板(printed circuit board,PCB)而已,成本非常低廉。In the LED driver 840 shown in FIG. 31, all Schottky diodes and high electron mobility field effect transistors can be integrated into a single crystal microwave integrated circuit with GaN-based conduction channel material. For example, the Schottky diode can be implemented with the device structure shown in FIG. 6 or FIG. 26A , and the enhancement mode high electron mobility field effect transistor and the depletion mode high electron mobility field effect transistor can be implemented with the device structure shown in FIG. 30 , respectively. The component structure of the left half and the right half is realized. In other words, when implementing the LED driver 840, only a single crystal microwave integrated circuit, some resistance elements, an LED 848 and a printed circuit board (PCB) may be required, and the cost is very low.

随着环境温度的升高,以定电流驱动的一LED,其发光亮度可能会减弱。为了弥补高温所导致的亮度衰减,所以在本申请的一些实施例中,可以用正温度系数或是负温度系数的热敏电阻,来调整对LED的驱动电流。As the ambient temperature increases, the luminous brightness of an LED driven by a constant current may decrease. In order to compensate for the brightness attenuation caused by high temperature, in some embodiments of the present application, a thermistor with a positive temperature coefficient or a negative temperature coefficient can be used to adjust the driving current to the LED.

图33显示了具有正温度系数的一热敏电阻的一LED驱动器900,其中,热敏电阻902的两端,分别连接到电流开关CC4内的增强模式高电子迁移率场效晶体管ME1的一栅端与一通道端。耗尽模式高电子迁移率场效晶体管T5作为一定电流源,大约提供一定电流流经正温度系数热敏电阻902,增强模式高电子迁移率场效晶体管ME1操作于线性区。当环境温度增加时,热敏电阻902的电阻上升,因此,电流开关CC4的控制栅的电压也变高,增加了流经LED 518的电流。如此,可以使LED 518的发光量,大约不随着温度变化而改变。FIG. 33 shows an LED driver 900 with a thermistor having a positive temperature coefficient, wherein the two ends of the thermistor 902 are respectively connected to a gate of the enhancement mode high electron mobility field effect transistor ME1 in the current switch CC4 end and a channel end. The depletion mode high electron mobility field effect transistor T5 is used as a certain current source to provide a certain current to flow through the positive temperature coefficient thermistor 902, and the enhancement mode high electron mobility field effect transistor ME1 operates in the linear region. As the ambient temperature increases, the resistance of the thermistor 902 rises and, therefore, the voltage on the control gate of the current switch CC4 also rises, increasing the current through the LED 518. In this way, the amount of light emitted by the LED 518 can be kept approximately unchanged with temperature.

图34显示了具有负温度系数的一热敏电阻的一LED驱动器906,其中,耗尽模式高电子迁移率场效晶体管T6可作为一定电流源,其所提供的定电流大致由其源极电压所决定。当环境温度增加时,热敏电阻906的电阻下降,因此,耗尽模式高电子迁移率场效晶体管T6的源极电压变低,耗尽模式高电子迁移率场效晶体管T6的栅对源(gate to source)电压增加,因此增加了流经LED 518的电流。如此,可以使LED 518的发光量,大约不随着温度变化而改变。FIG. 34 shows an LED driver 906 with a thermistor having a negative temperature coefficient, wherein the depletion mode high electron mobility field effect transistor T6 can be used as a constant current source, which provides a constant current approximately determined by its source voltage decided. When the ambient temperature increases, the resistance of the thermistor 906 decreases, therefore, the source voltage of the depletion-mode high electron mobility field effect transistor T6 becomes lower, and the gate-to-source ( gate to source) voltage increases, thus increasing the current through LED 518. In this way, the amount of light emitted by the LED 518 can be kept approximately unchanged with temperature.

依据本申请所实施的LED驱动器,并不限于只能有一个LED或是只能有一个热敏电阻。图35显示了LED驱动器910,其具有LED 5181、5182与5183。类似图33所教导,流经LED5181的驱动电流,受热敏电阻902控制,随着温度增加而增加。类似图34所教导的,流经LED5182的驱动电流,受热敏电阻906控制,随着温度增加而增加。而流经LED 5183的驱动电流,受耗尽模式高电子迁移率场效晶体管T7所控制,大致不随温度而变化。在一实施例中,LED5183是一蓝光LED,而LED 5181或5182是一红光LED。The LED driver implemented according to the present application is not limited to having only one LED or only one thermistor. FIG. 35 shows LED driver 910 with LEDs 5181, 5182 and 5183. Similar to what is taught in Figure 33, the drive current through LED 5181, controlled by thermistor 902, increases with increasing temperature. Similar to what is taught in Figure 34, the drive current through LED 5182, controlled by thermistor 906, increases with increasing temperature. The driving current flowing through the LED 5183 is controlled by the depletion mode high electron mobility field effect transistor T7, and is substantially invariant with temperature. In one embodiment, LED 5183 is a blue LED and LED 5181 or 5182 is a red LED.

图36A显示一依据本申请一实施例的LED驱动器60a,其可用来驱动发光元件,此发光元件可以是图2中的由多个为LED串联而成的LED 18,LED 18的等效正向电压Vef-led依实际需求可介于50V至140V之间。类似于图2中的LED驱动器60,本实施例的LED驱动器60a也大致包含三部分,第一部分是与LED 18及交流输入电源AC-source电连接的桥式整流器62;第二部分是跨接于桥式整流器62以及LED 18之间的保护电路63;第三部分为跨接于LED 18和桥式整流器62之间的电流驱动电路66,其包含两个高电子迁移率场效晶体管T1、T2。其中,桥式整流器62作为整流电路,用以将交流输入电源(AC-source)转换成一直流电源(DC-source)。此直流电源包含直流电流IDC-IN及直流电压VDC-IN提供至LED 18。高电子迁移率场效晶体管T1、T2用来限制直流电流IDC-IN的大小以大致提供一定电流来驱动LED 18。保护电路63包含保护单元Dclamp,保护电路63跨接电流驱动电路66与LED 18,并与整流电路(桥式整流器62)串联,当直流电压VDC-IN大于一定值时,直流电流IDC-IN流向保护电路63。本实施例与前述实施例的差别在于:本实施例着重于元件的保护,故利用保护电路63取代前述实施例中的填谷电路64。然而本申请不以上述为限,在其他实施例中,LED驱动器可同时包含保护电路与填谷电路。请参考图36B,图36B显示一依据本申请另一实施例的LED驱动器60b,LED驱动器60b大致包含四部分,第一部分是与LED 18及交流输入电源AC-source电连接的桥式整流器62;第二部分是跨接于桥式整流器62以及LED 18之间的保护电路63;第三部分为跨接于LED18和桥式整流器62之间的电流驱动电路66;第四部分为填谷电路64。简单来说,相较于LED驱动器60a,LED驱动器60b还包括一分别与保护电路63、电流驱动电路66并联的填谷电路64。FIG. 36A shows an LED driver 60a according to an embodiment of the present application, which can be used to drive a light-emitting element. The light-emitting element may be the LED 18 in FIG. 2 that is formed by connecting a plurality of LEDs in series. The equivalent forward direction of the LED 18 is The voltage V ef-led can be between 50V and 140V according to actual needs. Similar to the LED driver 60 in FIG. 2 , the LED driver 60 a of this embodiment also roughly includes three parts. The first part is a bridge rectifier 62 electrically connected to the LED 18 and the AC input power source AC-source; the second part is a bridge rectifier 62 . A protection circuit 63 between the bridge rectifier 62 and the LED 18; the third part is a current drive circuit 66 connected across the LED 18 and the bridge rectifier 62, which includes two high electron mobility field effect transistors T1, T2. Among them, the bridge rectifier 62 is used as a rectifying circuit for converting an alternating current input power (AC-source) into a direct current power (DC-source). The DC power source includes a DC current I DC-IN and a DC voltage V DC-IN provided to the LED 18 . The high electron mobility field effect transistors T1 and T2 are used to limit the magnitude of the DC current I DC-IN to provide approximately a certain current to drive the LED 18 . The protection circuit 63 includes a protection unit D clamp . The protection circuit 63 is connected across the current driving circuit 66 and the LED 18, and is connected in series with the rectifier circuit (bridge rectifier 62). When the DC voltage V DC-IN is greater than a certain value, the DC current I DC -IN flows to the protection circuit 63 . The difference between this embodiment and the previous embodiment is that this embodiment focuses on the protection of components, so the protection circuit 63 is used to replace the valley filling circuit 64 in the previous embodiment. However, the present application is not limited to the above, and in other embodiments, the LED driver may include a protection circuit and a valley filling circuit at the same time. Please refer to FIG. 36B. FIG. 36B shows an LED driver 60b according to another embodiment of the present application. The LED driver 60b roughly includes four parts. The first part is a bridge rectifier 62 electrically connected to the LED 18 and the AC input power source AC-source; The second part is the protection circuit 63 connected across the bridge rectifier 62 and the LED 18; the third part is the current drive circuit 66 connected across the LED18 and the bridge rectifier 62; the fourth part is the valley filling circuit 64 . In short, compared with the LED driver 60a, the LED driver 60b further includes a valley filling circuit 64 connected in parallel with the protection circuit 63 and the current driving circuit 66, respectively.

在图36A的LED驱动器60a中,桥式整流器62通过接点N、L与交流输入电源AC-source连接,并且桥式整流器62还通过接点C、A与LED 18串联。桥式整流器62包含四个整流二极管DB1-DB4,其作用为将交流输入电源AC-source转换成直流电源,其中交流输入电源(AC-source)与直流电源(DC-source)的电压波形图,请分别参考图3的电压波形72、74。此直流电源可提供直流电流IDC-IN及直流电压VDC-IN至LED 18。举例来说,交流输入电源AC-source可以是一般110V交流市电或220V的交流市电。In the LED driver 60a of FIG. 36A, the bridge rectifier 62 is connected to the AC input power source AC-source through the contacts N, L, and the bridge rectifier 62 is also connected in series with the LED 18 through the contacts C, A. The bridge rectifier 62 includes four rectifier diodes DB1-DB4, which are used to convert the AC input power AC-source into DC power, wherein the voltage waveforms of the AC input power (AC-source) and the DC power supply (DC-source), Please refer to the voltage waveforms 72 and 74 of FIG. 3 , respectively. The DC power supply can provide the DC current I DC-IN and the DC voltage V DC-IN to the LED 18 . For example, the AC input power AC-source may be a general 110V AC mains or a 220V AC mains.

请参考图36A,电流驱动电路66与LED 18串联,由电流驱动电路66限制直流电流IDC-IN的大小以大致提供一定电流至LED 18。电流驱动电路66中的高电子迁移率场效晶体管T1与T2如前所述可为耗尽模式(depletion mode)晶体管,意味着他们的临界电压(threshold voltage,VTH)都是负值,且各具有一栅极以及源极与漏极。在本实施例中,每个高电子迁移率场效晶体管T1与T2的栅极与源极连接。此外,一如前文所述(请参考本案“具体实施方式”中的第七段),高电子迁移率场效晶体管T1、T2,还可以各自作为一定电流源使用或是并联后作为一可以提供更大电流数值的定电流源,在图36A中,类似于图2同样以虚线67连接高电子迁移率场效晶体管T2与LED 18,由此表示高电子迁移率场效晶体管T2可以选择性地联合高电子迁移率场效晶体管T1一同驱动LED 18。为更进一步了解高电子迁移率场效晶体管的特性,以高电子迁移率场效晶体管T1为例,请参考图37,图37为高电子迁移率场效晶体管T1的电压电流关系图。由图37可知,当高电子迁移率场效晶体管T1的漏源电压VDS大于高电子迁移率场效晶体管T1的切入电压Vknee(knee voltage)时,此时,高电子迁移率场效晶体管T1操作在饱和区SS中,高电子迁移率场效晶体管T1的漏源电流IDS大约是一常数IC,一般称的为饱和电流。其中,高电子迁移率场效晶体管T1的漏源电压VDS的大小约莫为直流电压VDC-IN减去LED 18的等效正向电压Vef-led(本实施例中,设定为50V),再减去单颗整流二极管的电压VDBi(约1.5V),其中i=1,2,3,4,即VDS=VDC-IN-Vef-led-VDBiReferring to FIG. 36A , the current driving circuit 66 is connected in series with the LED 18 , and the magnitude of the DC current I DC-IN is limited by the current driving circuit 66 to provide a certain current to the LED 18 approximately. The high electron mobility field effect transistors T1 and T2 in the current driving circuit 66 can be depletion mode transistors as described above, which means that their threshold voltages (V TH ) are both negative, and Each has a gate, source and drain. In this embodiment, the gate and source of each of the high electron mobility field effect transistors T1 and T2 are connected. In addition, as mentioned above (please refer to the seventh paragraph in the "Detailed Description of Embodiments" of this case), the high electron mobility field effect transistors T1 and T2 can also be used as a certain current source respectively or can be used in parallel to provide A constant current source with a larger current value, in FIG. 36A , similar to FIG. 2 , the high electron mobility field effect transistor T2 and the LED 18 are also connected by a dotted line 67 , thus indicating that the high electron mobility field effect transistor T2 can be selectively The LED 18 is driven together with the high electron mobility field effect transistor T1. To further understand the characteristics of the high electron mobility field effect transistor, take the high electron mobility field effect transistor T1 as an example, please refer to FIG. 37 , which is a voltage-current relationship diagram of the high electron mobility field effect transistor T1 . It can be seen from FIG. 37 that when the drain-source voltage V DS of the high electron mobility field effect transistor T1 is greater than the cut-in voltage V knee (knee voltage) of the high electron mobility field effect transistor T1, at this time, the high electron mobility field effect transistor T1 operates in the saturation region SS, and the drain-source current I DS of the high electron mobility field effect transistor T1 is about a constant I C , which is generally called the saturation current. The magnitude of the drain-source voltage V DS of the high electron mobility field effect transistor T1 is approximately equal to the DC voltage V DC-IN minus the equivalent forward voltage V ef-led of the LED 18 (in this embodiment, it is set to 50V ), and then subtract the voltage V DBi (about 1.5V) of a single rectifier diode, where i=1, 2, 3, 4, that is, V DS =V DC-IN -V ef-led -V DBi .

保护电路63跨接电流驱动电路66与LED 18,并反向连接整流电路(桥式整流器62)。保护电路63包含保护单元Dclamp,主要是用来保护电流驱动电路66,亦即保护高电子迁移率场效晶体管T1、T2。以高电子迁移率场效晶体管T1为例,为了达到上述用来有效保护高电子迁移率场效晶体管T1的目的,本实施例所选用的保护单元Dclamp其反向导通电压Vclamp会小于高电子迁移率场效晶体管T1的击穿电压Vbreak。举例来说,当高电子迁移率场效晶体管T1的击穿电压Vbreak为600V,可选用反向导通电压Vclamp为560V的保护单元Dclamp。在本实施例中,保护单元Dclamp例如为钳位二极管,作为保护单元Dclamp的钳位二极管的特性在于其反向导通电压Vclamp(数十伏特到数百伏特不等)较顺向导通电压(约数伏特)高出许多,且其在反向导通时,保护单元Dclamp的电阻极小。当有突波出现而导致直流电压VDC-IN超过保护单元Dclamp的反向导通电压Vclamp(VDC-IN>Vclamp)时,保护单元Dclamp导通,此时因其反向导通的电阻极小,故大部分的直流电流IDC-IN会流向保护单元Dclamp,加以本实施例选用的保护单元Dclamp的反向导通电压Vclamp小于高电子迁移率场效晶体管T1的击穿电压Vbreak,故可以有效避免高电子迁移率场效晶体管T1、T2因直流电压VDC-IN过大而导致漏源电压VDS超过其击穿电压Vbreak,进而短路的状况产生。此外,本实施例的保护单元Dclamp的反向导通电压Vclamp会较LED18的等效正向电压Vef-led高,一般而言在没有突波的情况下,直流电压VDC-IN会小于保护单元Dclamp的反向导通电压Vclamp,此时保护单元Dclamp不导通,直流电流IDC-IN会流向LED 18,而不影响LED 18的作动。The protection circuit 63 is connected across the current drive circuit 66 and the LED 18, and the rectifier circuit (bridge rectifier 62) is connected in reverse. The protection circuit 63 includes a protection unit D clamp , which is mainly used to protect the current driving circuit 66 , that is, to protect the high electron mobility field effect transistors T1 and T2 . Taking the high electron mobility field effect transistor T1 as an example, in order to achieve the above purpose of effectively protecting the high electron mobility field effect transistor T1, the reverse conduction voltage V clamp of the protection unit D clamp selected in this embodiment will be less than high. The breakdown voltage V break of the electron mobility field effect transistor T1 . For example, when the breakdown voltage V break of the high electron mobility field effect transistor T1 is 600V, a protection unit D clamp with a reverse conduction voltage V clamp of 560V can be selected. In this embodiment, the protection unit D clamp is, for example, a clamp diode, and the characteristic of the clamp diode as the protection unit D clamp is that its reverse conduction voltage V clamp (ranging from tens of volts to hundreds of volts) is more conductive than forward conduction The voltage (on the order of a few volts) is much higher, and when it conducts in reverse, the resistance of the protection unit D clamp is extremely small. When a surge occurs and the DC voltage V DC-IN exceeds the reverse conduction voltage V clamp of the protection unit D clamp ( V DC-IN >V clamp ), the protection unit D clamp is turned on. The resistance is extremely small, so most of the DC current I DC-IN will flow to the protection unit D clamp , and the reverse conduction voltage V clamp of the protection unit D clamp selected in this embodiment is smaller than the strike of the high electron mobility field effect transistor T1 The breakdown voltage V break can effectively prevent the high electron mobility field effect transistors T1 and T2 from being short-circuited due to the excessive DC voltage V DC-IN causing the drain-source voltage V DS to exceed the breakdown voltage V break . In addition, the reverse conduction voltage V clamp of the protection unit D clamp of this embodiment is higher than the equivalent forward voltage V ef-led of the LED 18. Generally speaking, in the absence of a surge, the DC voltage V DC-IN will be When the reverse conduction voltage V clamp of the protection unit D clamp is smaller than the reverse conduction voltage V clamp of the protection unit D clamp , the protection unit D clamp is not conductive at this time, and the DC current I DC-IN will flow to the LED 18 without affecting the operation of the LED 18 .

为简要说明LED驱动器60a的作动原理,以下的作动原理是针对仅以高电子迁移率场效晶体管T1来驱动LED 18为例,即虚线67未连接高电子迁移率场效晶体管T2与LED 18,高电子迁移率场效晶体管T1未与高电子迁移率场效晶体管T2并联的情况。如上所述,在直流电压VDC-IN小于保护单元Dclamp反向导通电压Vclamp的情况下,保护单元Dclamp不导通。在桥式整流器62将交流输入电源AC-source转换成直流电源后,直流电源会提供直流电流IDC-IN及直流电压VDC-IN至LED 18。由于LED 18与高电子迁移率场效晶体管T1电连接的关系,流向至LED 18的直流电流IDC-IN其大小将会被高电子迁移率场效晶体管T1所限制。以下在LED 18被导通(直流电压VDC-IN大于等效正向电压Vef-led),且高电子迁移率场效晶体管T1的漏源电压VDS大于高电子迁移率场效晶体管T1的切入电压Vknee(knee voltage)的情况进行讨论。在上述的情况下,因为高电子迁移率场效晶体管T1操作于饱和区SS(如图37所示)中,其漏源电流IDS大约是一常数IC(称的为饱和电流)。根据克希荷夫电流定律可以得知,漏源电流IDS的大小会等于流经LED 18的直流电流IDC-IN的大小(Ic=IDC-IN),所以可将高电子迁移率场效晶体管T1当作一定电流源,用以限制直流电流IDC-IN的大小以提供稳定的一定电流来驱动LED 18,使LED 18的发光强度维持一定。以实际的数值来说明上述的情况,在本实施例中,单颗整流二极管的电压VDBi约1.5V、LED 18的等效正向电压Vef-led约50V、高电子迁移率场效晶体管T1的击穿电压Vbreak及切入电压Vknee约分别为600V、5V,其饱和电流Ic约110mA。上述有关于高电子迁移率场效晶体管T1的数值描述,仍然遵守图37的曲线特性,上述数值仅为一实施态样,并非用来限制本发明。当直流电压VDC-IN介于60V~110V时,漏源电压VDS的大小约莫在8V~55V之间(VDS=V1st-Vef-led-VDBi),大于切入电压Vknee。此时高电子迁移率场效晶体管T1的漏源电压VDS处于饱和区SS中(5V~700V之间),故可限制直流电流IDC-IN的大小,由此提供LED 18一定电流Ic=110mA。另一方面,当一突波出现时,若此突波所对应的直流电压VDC-IN大于保护单元Dclamp反向导通电压Vclamp 560V,则保护单元Dclamp导通,电流大部分流向保护单元Dclamp,以达到保护高电子迁移率场效晶体管T1的效果,避免高电子迁移率场效晶体管T1短路。In order to briefly explain the operation principle of the LED driver 60a, the following operation principle is for the example of driving the LED 18 only with the high electron mobility field effect transistor T1, that is, the dotted line 67 does not connect the high electron mobility field effect transistor T2 and the LED. 18. The case where the high electron mobility field effect transistor T1 is not connected in parallel with the high electron mobility field effect transistor T2. As described above, when the direct current voltage V DC-IN is lower than the reverse conduction voltage V clamp of the protection unit D clamp , the protection unit D clamp is not turned on. After the bridge rectifier 62 converts the AC input power AC-source into a DC power source, the DC power source provides the DC current I DC-IN and the DC voltage V DC-IN to the LED 18 . Due to the electrical connection between the LED 18 and the high electron mobility field effect transistor T1, the magnitude of the DC current I DC-IN flowing to the LED 18 will be limited by the high electron mobility field effect transistor T1. After the LED 18 is turned on (the DC voltage V DC-IN is greater than the equivalent forward voltage V ef-led ), and the drain-source voltage V DS of the high electron mobility field effect transistor T1 is greater than the high electron mobility field effect transistor T1 The case of the cut-in voltage V knee (knee voltage) is discussed. In the above case, since the high electron mobility field effect transistor T1 operates in the saturation region SS (as shown in FIG. 37 ), its drain-source current I DS is about a constant IC (called saturation current). According to Kirchhoff's current law, it can be known that the magnitude of the drain-source current I DS will be equal to the magnitude of the DC current I DC-IN flowing through the LED 18 (Ic=I DC-IN ), so the high electron mobility field can be The effective transistor T1 is used as a constant current source to limit the magnitude of the DC current I DC-IN to provide a stable constant current to drive the LED 18, so that the luminous intensity of the LED 18 is maintained constant. The above situation is illustrated with actual values. In this embodiment, the voltage V DBi of a single rectifier diode is about 1.5V, the equivalent forward voltage V ef-led of the LED 18 is about 50V, and the high electron mobility field effect transistor The breakdown voltage V break and cut-in voltage V knee of T1 are about 600V and 5V, respectively, and the saturation current Ic is about 110mA. The above numerical description about the high electron mobility field effect transistor T1 still follows the curve characteristics of FIG. 37 , and the above numerical value is only an embodiment, and is not intended to limit the present invention. When the DC voltage V DC-IN is between 60V and 110V, the drain-source voltage V DS is approximately between 8V and 55V (V DS =V 1st -V ef-led -V DBi ), which is greater than the cut-in voltage V knee . At this time, the drain-source voltage V DS of the high electron mobility field effect transistor T1 is in the saturation region SS (between 5V and 700V), so the magnitude of the DC current I DC-IN can be limited, thereby providing the LED 18 with a certain current Ic= 110mA. On the other hand, when a surge occurs, if the DC voltage V DC-IN corresponding to the surge is greater than the reverse conduction voltage V clamp of the protection unit D clamp by 560V, the protection unit D clamp is turned on, and most of the current flows to the protection unit The unit D clamp can achieve the effect of protecting the high electron mobility field effect transistor T1 and avoid short circuit of the high electron mobility field effect transistor T1 .

为了简化上述LED驱动器60a的制作流程,在本申请的一实施例中,图36A中的整流二极管DB1-DB4、高电子迁移率场效晶体管T1、T2,以及保护单元Dclamp,还可共同形成于一基底91上。图38显示LED驱动器60c的上视图。在图38中,LED驱动器60c包含桥式整流器62、保护电路63与电流驱动电路66。在本实施例中,电流趋动电路包含两高电子迁移率场效晶体管T1、T2,而保护电路63包含保护单元Dclamp。其中,桥式整流器62、两高电子迁移率场效晶体管T1、T2和保护单元Dclamp共用基底91。换言之,LED驱动器60c为一单石结构(monolithicstructure),由单一半导体芯片经由不同制作工艺形成LED驱动器60c的各单元。桥式整流器62、两高电子迁移率场效晶体管T1、T2,以及保护单元Dclamp的电连接方式与图36A相同,还请参考图36A与前述的说明。在本实施例中,桥式整流器62的四个整流二极管是利用四个多指状结构的萧特基二极管SBD1、SBD2、SBD3、SBD4所构成且阵列于基底91上,两高电子迁移率场效晶体管T1、T2例如为多指状结构的高电子迁移率场效晶体管,而保护单元Dclamp例如为多指状结构的钳位二极管。其中,桥式整流器62利用接点N、L与一交流输入电源(未绘示)电连接,并且跨接交流输入电源于与一发光元件(未绘示)之间。等效上,桥式整流器62中的萧基特二极管SBD1、SBD2、SBD3、SBD4分别由许多的小萧基特二极管并联所构成。多指状结构的高电子迁移率场效晶体管可以在有限的芯片面积中,提供较大的驱动电流。在一实施例中,每一个萧基特二极管SBD1、SBD2、SBD3、SBD4也可如图27所示的由多个二极管串联而成。在另一实施例中,高电子迁移率场效晶体管T1、T2不限于都为耗尽模式,其中之一可为增强模式(enhancement mode,E-mode)另一为耗尽模式,其详细说明请参考图29A、图29B、图30。在又一实施例中,LED驱动器60c的高电子迁移率场效晶体管T1/T2还可以连接一热敏电阻,其详细说明请参考图33至图35的说明,在此不再重述。In order to simplify the manufacturing process of the above LED driver 60a, in an embodiment of the present application, the rectifier diodes DB1-DB4, the high electron mobility field effect transistors T1, T2, and the protection unit D clamp in FIG. 36A can also be formed together on a substrate 91 . Figure 38 shows a top view of the LED driver 60c. In FIG. 38 , the LED driver 60 c includes a bridge rectifier 62 , a protection circuit 63 and a current drive circuit 66 . In this embodiment, the current driving circuit includes two high electron mobility field effect transistors T1 and T2, and the protection circuit 63 includes a protection unit D clamp . The bridge rectifier 62 , the two high electron mobility field effect transistors T1 and T2 and the protection unit D clamp share the substrate 91 . In other words, the LED driver 60c is a monolithic structure, and each unit of the LED driver 60c is formed from a single semiconductor chip through different fabrication processes. The electrical connection of the bridge rectifier 62 , the two high electron mobility field effect transistors T1 and T2 , and the protection unit D clamp is the same as that in FIG. 36A . Please refer to FIG. 36A and the above description. In this embodiment, the four rectifier diodes of the bridge rectifier 62 are composed of four Schottky diodes SBD1 , SBD2 , SBD3 , and SBD4 with a multi-finger structure and are arrayed on the substrate 91 . The two high electron mobility field The effect transistors T1 and T2 are, for example, high electron mobility field effect transistors with a multi-finger structure, and the protection unit D clamp is, for example, a clamping diode with a multi-finger structure. The bridge rectifier 62 is electrically connected to an AC input power source (not shown) using the contacts N and L, and is connected across the AC input power source and a light-emitting element (not shown). Equivalently, the Schottky diodes SBD1 , SBD2 , SBD3 , and SBD4 in the bridge rectifier 62 are respectively composed of many small Schottky diodes in parallel. The high electron mobility field effect transistor with multi-finger structure can provide larger driving current in a limited chip area. In one embodiment, each of the Schottky diodes SBD1 , SBD2 , SBD3 , and SBD4 can also be formed by connecting a plurality of diodes in series as shown in FIG. 27 . In another embodiment, the high electron mobility field effect transistors T1 and T2 are not limited to be in depletion mode, and one of them can be an enhancement mode (E-mode) and the other is a depletion mode, which is described in detail. Please refer to FIG. 29A , FIG. 29B , and FIG. 30 . In yet another embodiment, the high electron mobility field effect transistors T1/T2 of the LED driver 60c may also be connected to a thermistor. Please refer to the descriptions of FIGS. 33 to 35 for detailed descriptions, which will not be repeated here.

请同时参考图38与图39。图39表示图38中的萧基特二极管SBD1、高电子迁移率场效晶体管T1与保护单元Dclamp的结构剖面示意图。如上文以及图38所示,LED驱动器60c,包含由四个阵列的萧基特二极管SBD1、SBD2、SBD3、SBD4所构成的桥式整流器62,两个高电子迁移率场效晶体管T1、T2与保护单元Dclamp,以及多个接点A、C、E、F、N、L、TD1、TD2、TSG。其中阳极Asbd1~sbd4与阴极Csbd1~sbd4分别形成在萧基特二极管SBD1、SBD2、SBD3、SBD4上;漏极Dhemt1、Dhemt2、栅极Ghemt1、Ghemt2、源极Shemt1、Shemt2分别形成在高电子迁移率场效晶体管T1、T2上;阳极Aclamp与阴极Cclamp分别形成在保护单元Dclamp上。萧基特二极管SBD1、SBD2、SBD3、SBD4和高电子迁移率场效晶体管T1、T2和保护单元Dclamp与多个接点A、C、E、F、N、L、TD1、TD2、TSG共同形成于基底91上。在本实施例中,由于萧基特二极管SBD1、SBD2、SBD3、SBD4四者的结构相同,且高电子迁移率场效晶体管T1、T2两者的结构相同,为简化说明,在图39中分别以萧基特二极管SBD1以及高电子迁移率场效晶体管T1为例来说明结构,图39仅供结构说明的示意图,并非实际结构尺寸及布局。如图39所示,位于基底91上的萧基特二极管SBD1包含半导体叠层90a,以及位于半导体叠层90a上的绝缘层103a、103b和阳极Asbd1与阴极Csbd1,其中阳极Asbd1与阴极Csbd1会分别与接点A、N连接;位于基底91上的高电子迁移率场效晶体管T1包含半导体叠层90a,以及位于半导体叠层90a上的绝缘层103a、103b和源极Shemt1、漏极Dhemt1、栅极Ghemt1,其中源极Shemt1与栅极Ghemt1会与接点TSG连接,而漏极Dhemt1会与接点TD1连接;位于基底91上的保护单元Dclamp包含半导体叠层90a,以及位于半导体叠层90a上的绝缘层103a、103b和阳极Aclamp与阴极Cclamp,其中阳极Aclamp与阴极Cclamp会分别与接点E、F连接。Please refer to Figure 38 and Figure 39 at the same time. FIG. 39 is a schematic cross-sectional view of the structure of the Schottky diode SBD1 , the high electron mobility field effect transistor T1 and the protection unit D clamp in FIG. 38 . As shown above and in FIG. 38, the LED driver 60c includes a bridge rectifier 62 formed by four arrays of Schottky diodes SBD1, SBD2, SBD3, SBD4, two high electron mobility field effect transistors T1, T2 and Protection unit D clamp , and multiple contacts A, C, E, F, N, L, TD1, TD2, TSG. The anodes A sbd1-sbd4 and the cathodes C sbd1-sbd4 are respectively formed on the Schottky diodes SBD1, SBD2, SBD3, SBD4; the drains D hemt1 , D hemt2 , the gates G hemt1 , G hemt2 , the sources S hemt1 , S The hemt2 is formed on the high electron mobility field effect transistors T1 and T2 respectively; the anode A clamp and the cathode C clamp are respectively formed on the protection unit D clamp . Schottky diodes SBD1, SBD2, SBD3, SBD4, high electron mobility field effect transistors T1, T2 and protection unit D clamp are formed together with multiple contacts A, C, E, F, N, L, TD1, TD2, TSG on the base 91 . In this embodiment, since the structures of the Schottky diodes SBD1, SBD2, SBD3, and SBD4 are the same, and the structures of the high electron mobility field effect transistors T1 and T2 are the same, in order to simplify the description, in FIG. Taking the Schottky diode SBD1 and the high electron mobility field effect transistor T1 as examples to illustrate the structure, FIG. 39 is only a schematic diagram for the structure description, not the actual structure size and layout. As shown in FIG. 39, the Schottky diode SBD1 on the substrate 91 includes a semiconductor stack 90a, and insulating layers 103a, 103b on the semiconductor stack 90a, an anode Asbd1 and a cathode Csbd1 , wherein the anode Asbd1 and the cathode are C sbd1 is connected to the contacts A and N, respectively; the high electron mobility field effect transistor T1 on the substrate 91 includes the semiconductor stack 90a, the insulating layers 103a, 103b on the semiconductor stack 90a, the source S hemt1 , the drain The electrode D hemt1 and the gate G hemt1 , wherein the source S hemt1 and the gate G hemt1 are connected to the contact TSG, and the drain D hemt1 is connected to the contact TD1; the protection unit D clamp located on the substrate 91 includes a semiconductor stack 90a , and the insulating layers 103a and 103b on the semiconductor stack 90a and the anode A clamp and the cathode C clamp , wherein the anode A clamp and the cathode C clamp are connected to the contacts E and F, respectively.

本实施例的萧基特二极管SBD1、高电子迁移率场效晶体管T1与保护单元Dclamp共用基底91,且个别具有相同的半导体叠层90a,因此在制作本实施例的萧基特二极管SBD1、高电子迁移率场效晶体管T1与保护单元Dclamp的时候,可同时制作三者的半导体叠层90a,并且还可将此三者的半导体叠层90a制作于于同一基底91上,由此简化制作流程。在本实施例中,在形成本实施例的半导体叠层90a之前,首先提供基底91,基底91厚度约为175~1500μm。基底91本身的材料可包含半导体材料、氧化物材料以及/或者金属材料。上述的半导体材料例如可以包含硅(Si)、碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)、氮化铝(AlN)等;上述的氧化物材料例如可以包含蓝宝石(sapphire);上述的金属材料例如可以包含铜(Cu)、钼(Mo)。另外,当以导电性来区分时,基底91本身可为导电基板或者是绝缘基板,上述的导电基板包含硅(Si)基板、氮化镓(GaN)基板、砷化镓(GaAs)等基板,而上述的绝缘基板则包含蓝宝石(sapphire)基板、绝缘硅(Silicon on insulator,SOI)基板、氮化铝(AlN)等基板。此外,基底91可选择性的掺杂物质于其中,以改变其导电性,以形成导电基板或不导电基板,以硅(Si)基板而言,可通过掺杂硼(B)、砷(As)、或磷(P)使其具有导电性。The Schottky diode SBD1, the high electron mobility field effect transistor T1 and the protection unit D clamp of the present embodiment share the substrate 91, and each have the same semiconductor stack 90a. Therefore, in the fabrication of the Schottky diode SBD1, When the high electron mobility field effect transistor T1 and the protection unit D clamp are used, the three semiconductor stacks 90a can be fabricated at the same time, and the three semiconductor stacks 90a can also be fabricated on the same substrate 91, which simplifies production process. In this embodiment, before forming the semiconductor stack 90a of this embodiment, a substrate 91 is provided first, and the thickness of the substrate 91 is about 175-1500 μm. The material of the substrate 91 itself may include semiconductor material, oxide material and/or metal material. The above-mentioned semiconductor material can include, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), etc.; the above-mentioned oxide material can include, for example, sapphire ( sapphire); the above-mentioned metal material may contain copper (Cu), molybdenum (Mo), for example. In addition, when distinguished by electrical conductivity, the base 91 itself may be a conductive substrate or an insulating substrate, and the above-mentioned conductive substrates include substrates such as silicon (Si) substrates, gallium nitride (GaN) substrates, and gallium arsenide (GaAs) substrates. The above-mentioned insulating substrates include sapphire (sapphire) substrates, silicon on insulator (SOI) substrates, aluminum nitride (AlN) and other substrates. In addition, the substrate 91 can be selectively doped with substances therein to change its conductivity to form a conductive substrate or a non-conductive substrate. For a silicon (Si) substrate, boron (B), arsenic (As) can be doped with ), or phosphorus (P) to make it conductive.

在提供基底91之后,将半导体叠层90a形成在基底91之上。半导体叠层90a包含缓冲层94、通道层96、高价带间隙层98与盖层100,半导体叠层90a的各层可通过外延成长方式形成于基底91之上。此外,在形成缓冲层94之前,还可以选择性地形成核层(未绘示)于基底91上,成核层的厚度约为20nm~200nm,通过成核层可让后续形于其上的缓冲层94与通道层96、高价带间隙层98与盖层100的外延品质较佳。成核层例如是三五族半导体材料,包括氮化铝(AlN)、氮化镓(GaN)、或氮化铝镓(AlGaN)等材料。半导体叠层90a可以通过外延的方式成长于基底91上,外延方式包含但不限于金属有机物化学气相外延法(metal-organicchemical vapor deposition,MOCVD)或分子束外延法(molecular-beam epitaxy,MBE),然而本申请不以外延的方式为限,亦即本申请基底91不限于成长基底。在其他实施例中,半导体叠层90a可以先外延成长于其他的成长基底上,再将半导体叠层90a与基底91结合,基底91包含金属、介电材料、绝缘材料或复合材料。结合方式包含胶合、焊接、热压等等。或者,将外延形成在一成长基底上的半导体叠层90a与基底91直接对位接合,然后再完全或部分移除此成长基底,使半导体叠层90a位于基底91上。或者,将半导体叠层90a先外延成长于其他的成长基底,然后将此成长基底减薄,接着将减薄后的成长基底连同其上的半导体叠层90a与基底91结合,而使半导体叠层90a形成在由减薄的成长基底与基底91所构成的复合基底上。After the substrate 91 is provided, the semiconductor stack 90a is formed over the substrate 91 . The semiconductor stack 90 a includes a buffer layer 94 , a channel layer 96 , a high-valence band gap layer 98 and a cap layer 100 , and each layer of the semiconductor stack 90 a may be formed on the substrate 91 by epitaxial growth. In addition, before the buffer layer 94 is formed, a nucleation layer (not shown) can also be selectively formed on the substrate 91. The thickness of the nucleation layer is about 20 nm to 200 nm. The epitaxial quality of the buffer layer 94 , the channel layer 96 , the high-valence bandgap layer 98 and the cap layer 100 is good. The nucleation layer is, for example, a Group III and V semiconductor material, including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The semiconductor stack 90a can be grown on the substrate 91 by means of epitaxy, including but not limited to metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). However, the present application is not limited to an epitaxial manner, that is, the substrate 91 of the present application is not limited to a growth substrate. In other embodiments, the semiconductor stack 90a can be epitaxially grown on other growth substrates, and then the semiconductor stack 90a is combined with the substrate 91, and the substrate 91 includes metal, dielectric material, insulating material or composite material. The bonding methods include gluing, welding, hot pressing and so on. Alternatively, the semiconductor stack 90 a epitaxially formed on a growth substrate is directly aligned and bonded to the substrate 91 , and then the growth substrate is completely or partially removed so that the semiconductor stack 90 a is located on the substrate 91 . Alternatively, the semiconductor stack 90a is first epitaxially grown on another growth substrate, then the growth substrate is thinned, and then the thinned growth substrate and the semiconductor stack 90a thereon are combined with the substrate 91 to make the semiconductor stack 90a is formed on a composite substrate consisting of a thinned growth substrate and substrate 91 .

在成核层形成之后,形成缓冲层94于其上,缓冲层94可以是如前所述的掺杂有碳(C-doped)的本质GaN。缓冲层94用以让后续形成于其上的通道层96与高价带间隙层98之外延品质较佳,其厚度约为1μm~10μm。缓冲层94可以是单层或是多层,当缓冲层94为多层时,可包括超晶格叠层(super lattice multilayer)或两层以上材料各不相同的叠层。单层或多层缓冲层94的材料可包括三五族半导体材料,例如氮化铝(AlN)、氮化镓(GaN)、或氮化铝镓(AlGaN)等材料,并且可掺杂其他元素,例如碳或是铁,于其中,掺杂浓度可为依成长方向渐变或固定。此外,当缓冲层94为超晶格叠层时,其可由两层具不同材料交互堆叠的多层外延层所构成,其材料可为三五族半导体材料,例如是由氮化铝层(AlN)与氮化镓铝层(AlGaN)所构成,氮化铝层与氮化镓层两层相加的约为2nm~30nm,整体厚度约为1μm~5μm。After the nucleation layer is formed, a buffer layer 94 is formed thereon. The buffer layer 94 may be C-doped intrinsic GaN as previously described. The buffer layer 94 is used for the channel layer 96 and the high-valence bandgap layer 98 formed thereon to have better epitaxial quality, and its thickness is about 1 μm˜10 μm. The buffer layer 94 may be a single layer or a multi-layer, and when the buffer layer 94 is a multi-layer, it may include a super lattice multilayer or two or more layers with different materials. The material of the single-layer or multi-layer buffer layer 94 may include Group III and V semiconductor materials, such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN) and other materials, and may be doped with other elements , such as carbon or iron, in which the doping concentration can be graded or fixed according to the growth direction. In addition, when the buffer layer 94 is a superlattice stack, it can be composed of two multi-layer epitaxial layers with different materials alternately stacked, and its material can be a Group III or V semiconductor material, such as an aluminum nitride layer (AlN ) and an aluminum gallium nitride layer (AlGaN), the sum of the two layers of the aluminum nitride layer and the gallium nitride layer is about 2 nm to 30 nm, and the overall thickness is about 1 μm to 5 μm.

在缓冲层94形成之后,以外延方式形成通道层96以及高价带间隙层98于缓冲层94之上。通道层96厚度范围在50~300nm,形成于缓冲层94上,并具有一第一能隙。高价带间隙层98厚度范围在20~50nm,形成在通道层96上,并具有一第二能隙,第二能隙较第一能隙高,高价带间隙层98的晶格常数比通道层96小。在本实施例中,通道层96包含氮化铟镓(InxGa(1-x)N),0≤x<1,高价带间隙层98的材料为氮化铝镓(AlyGa(1-y)N),y介于0.1至0.3之间,通道层96及高价带间隙层98可为本质半导体;在其他实施例中,高价带间隙层98的材料可为氮化铝铟镓(AlwInzGa(1-z)N),0<w<1,0≤z<1。如前所述,二维电子云可以形成在通道层96内邻接于通道层96与高价带间隙层98的接面,作为导电通道。详细而言,二维电子云的形成是由于能带因受到高价带间隙层98的自发性极化(spontaneous polarization),以及受到来自于通道层96及高价带间隙层98因晶格常数不匹配而形成压电极化(piezoelectricpolarization)的影响而弯曲,使得部分能带位于费米能阶之下,而在通道层96及高价带间隙层98间的接面处会形成二维电子云。After the buffer layer 94 is formed, the channel layer 96 and the high-valence bandgap layer 98 are formed on the buffer layer 94 by epitaxy. The channel layer 96 has a thickness in the range of 50-300 nm, is formed on the buffer layer 94, and has a first energy gap. The high-valence band gap layer 98 has a thickness ranging from 20 to 50 nm, is formed on the channel layer 96, and has a second energy gap, the second energy gap is higher than the first energy gap, and the lattice constant of the high-valence band gap layer 98 is higher than that of the channel layer. 96 small. In this embodiment, the channel layer 96 includes indium gallium nitride (In x Ga (1-x) N), 0≤x<1, and the material of the high-valence band gap layer 98 is aluminum gallium nitride (A y Ga ( 1-x) N) -y) N), y is between 0.1 and 0.3, the channel layer 96 and the high-valence bandgap layer 98 can be intrinsic semiconductors; in other embodiments, the material of the high-valence bandgap layer 98 can be aluminum indium gallium nitride ( Al w In z Ga (1-z) N), 0<w<1, 0≤z<1. As previously discussed, a two-dimensional electron cloud may be formed within channel layer 96 adjacent to the junction of channel layer 96 and high valence bandgap layer 98 as a conductive channel. In detail, the formation of the two-dimensional electron cloud is due to the spontaneous polarization of the energy band by the high-valence bandgap layer 98 and the mismatch of lattice constants from the channel layer 96 and the high-valence bandgap layer 98 The piezoelectric polarization (piezoelectric polarization) is formed to bend, so that part of the energy band is located below the Fermi level, and a two-dimensional electron cloud is formed at the junction between the channel layer 96 and the high-valence band gap layer 98 .

在形成高价带间隙层98于通道层96之后,还可以参考图14步骤140的方式,利用感应式耦合等离子体蚀刻等方式图案化缓冲层94、通道层96与高价带间隙层98、盖层100而完成平台区95。由于在此步骤之前,萧基特二极管SBD1、高电子迁移率场效晶体管T1的半导体叠层90a与保护单元Dclamp的半导体叠层90a为彼此连接在一起,经由此步骤萧基特二极管SBD1的半导体叠层90a、高电子迁移率场效晶体管T1的半导体叠层90a与保护单元Dclamp的半导体叠层90a可彼此分离,进而达到各半导体叠层90a间电性绝缘的目的。然而本申请不以上述为限,可视制作工艺的需求,调整平台区95的形成时机与形成方式,举例而言于其他实施例中,当缓冲层94为一高阻值层时,在形成平台区95时,不需要完全蚀刻缓冲层94,只需蚀刻位于缓冲层94上的通道层96与高价带间隙层98、盖层100就能达到使各半导体叠层90a间彼此电性绝缘的目的。换言之,在上述的情况下,缓冲层94可完全或者部分被保留,萧基特二极管SBD1、高电子迁移率场效晶体管T1与保护单元Dclamp在共用缓冲层94的情况下,各半导体叠层90a仍然可以彼此电性隔绝。After the high-valence bandgap layer 98 is formed on the channel layer 96 , the buffer layer 94 , the channel layer 96 , the high-valence bandgap layer 98 , and the cap layer may be patterned by means of inductively coupled plasma etching or the like with reference to step 140 in FIG. 14 . 100 to complete the platform area 95. Before this step, the Schottky diode SBD1, the semiconductor stack 90a of the high electron mobility field effect transistor T1, and the semiconductor stack 90a of the protection unit D clamp are connected to each other. The semiconductor stack 90a, the semiconductor stack 90a of the high electron mobility field effect transistor T1 and the semiconductor stack 90a of the protection unit D clamp can be separated from each other, thereby achieving the purpose of electrical insulation between the semiconductor stacks 90a. However, the present application is not limited to the above, and the formation timing and formation method of the platform region 95 may be adjusted according to the requirements of the manufacturing process. For example, in other embodiments, when the buffer layer 94 is a high-resistance layer, the When the mesa region 95 is used, it is not necessary to completely etch the buffer layer 94, and only the channel layer 96, the high-valence bandgap layer 98, and the cap layer 100 on the buffer layer 94 can be etched to achieve electrical insulation between the semiconductor stacks 90a. Purpose. In other words, in the above case, the buffer layer 94 can be completely or partially retained, and the Schottky diode SBD1 , the high electron mobility field effect transistor T1 and the protection unit D clamp share the buffer layer 94 . 90a can still be electrically isolated from each other.

在本实施例中,为了使在直流电压VDC-IN小于保护单元Dclamp反向导通电压Vclamp的情况下,保护单元Dclamp不导通,在形成高价带间隙层98于通道层96上之后,还进一步形成p型阻障层Pb于保护单元Dclamp的高价带间隙层98之中,利用p型阻障层Pb使其下方位于通道层96内的二维电子云完全空乏,由此达到上述在直流电压VDC-IN小于保护单元Dclamp反向导通电压Vclamp的情况下,保护单元Dclamp不导通的目的。本实施例是以对保护单元Dclamp的高价带间隙层98进行掺杂以形成p型阻障层Pb为例。当p型阻障层Pb层形成在高价带间隙层98中时,p型阻障层Pb会改变费米能阶的位置,使得p型阻障层Pb所在位置的费米能阶远离导电带往价带的方向移动,一旦p型阻障层Pb所在位置的费米能阶位于导电带的下方时,则其下方位于通道层96内的二维电子云完全空乏。一般而言p型阻障层Pb的掺杂浓度会与载流子浓度正相关,而p型阻障层Pb的载流子浓度与厚度会分别与二维电子云的浓度负相关,对于p型阻障层Pb层形成在高价带间隙层98层的情况来说,p型阻障层Pb层的载流子浓度越高或p型阻障层Pb层的厚度Tb越厚,则p型阻障层Pb所在位置的费米能阶会越往价带的方向移动,而使得其下方的二维电子云的浓度越低。在本实施例中,可通过让p型阻障层Pb的厚度Tb大于或等于高价带间隙层98的厚度,使得p型阻障层Pb所在位置的费米能阶都位于导带下方而不与导带重叠,从而使得p型阻障层Pb下方的二维电子云完全空乏,或者通过调高p型阻障层Pb的载流子浓度使得p型阻障层Pb所在位置的导带与费米能阶不重叠,从而使得p型阻障层Pb下方的二维电子云完全空乏。换句话说,p型阻障层Pb的载流子浓度与厚度Tb会影响p型阻障层Pb的极性大小,进而改变p型阻障层Pb的能带位置,使得费米能阶与价带之间的距离随之改变,由此p型阻障层Pb下方二维电子云浓度也随之改变。In this embodiment, in order to prevent the protection unit D clamp from conducting when the DC voltage V DC-IN is lower than the reverse conduction voltage V clamp of the protection unit D clamp , a high valence band gap layer 98 is formed on the channel layer 96 . After that, a p-type barrier layer Pb is further formed in the high-valence band gap layer 98 of the protection unit D clamp , and the p-type barrier layer Pb is used to completely deplete the two-dimensional electron cloud in the channel layer 96 under the p-type barrier layer. The above-mentioned purpose of preventing the protection unit D clamp from being turned on is achieved when the DC voltage V DC-IN is less than the reverse conduction voltage V clamp of the protection unit D clamp . In this embodiment, the p-type barrier layer Pb is formed by doping the high-valence band gap layer 98 of the protection unit D clamp as an example. When the p-type barrier layer Pb layer is formed in the high valence band gap layer 98, the p-type barrier layer Pb will change the position of the Fermi level, so that the Fermi level where the p-type barrier layer Pb is located is far away from the conduction band Moving in the direction of the valence band, once the Fermi level of the p-type barrier layer Pb is located below the conduction band, the two-dimensional electron cloud in the channel layer 96 below it is completely depleted. Generally speaking, the doping concentration of the p-type barrier layer Pb is positively correlated with the carrier concentration, while the carrier concentration and thickness of the p-type barrier layer Pb are negatively correlated with the concentration of the two-dimensional electron cloud, respectively. In the case where the Pb layer of the p-type barrier layer is formed on the high-valence band gap layer 98, the higher the carrier concentration of the p-type barrier layer Pb layer or the thicker the thickness Tb of the p-type barrier layer Pb layer, the higher the p-type barrier layer Pb layer. The Fermi level at the position of the barrier layer Pb will move to the direction of the valence band, so that the concentration of the two-dimensional electron cloud below it will be lower. In this embodiment, by making the thickness Tb of the p-type barrier layer Pb greater than or equal to the thickness of the high-valence band gap layer 98 , the Fermi levels at the position of the p-type barrier layer Pb are all located below the conduction band without It overlaps with the conduction band, so that the two-dimensional electron cloud under the p-type barrier layer Pb is completely depleted, or by increasing the carrier concentration of the p-type barrier layer Pb, the conduction band at the position of the p-type barrier layer Pb is different from that of the p-type barrier layer Pb. The Fermi levels do not overlap, so that the 2D electron cloud under the p-type barrier Pb is completely depleted. In other words, the carrier concentration and thickness Tb of the p-type barrier layer Pb will affect the polarity of the p-type barrier layer Pb, and then change the energy band position of the p-type barrier layer Pb, so that the Fermi level and the The distance between the valence bands changes accordingly, and the concentration of the two-dimensional electron cloud under the p-type barrier layer Pb also changes accordingly.

此外,p型阻障层Pb的载流子浓度与长度Lb还会影响p型阻障层Pb与通道层96间的空乏区宽度。由于保护单元Dclamp的反向导通电压Vclamp的大小会同时受到二维电子云的浓度和p型阻障层Pb与通道层96间的空乏区宽度的影响,故还可通过调整p型阻障层Pb的载流子浓度、长度Lb、厚度Tb改变反向导通电压Vclamp的大小。详细而言,保护单元Dclamp的反向导通电压Vclamp会与p型阻障层Pb的载流子浓度负相关,而与p型阻障层Pb的长度Lb正相关,载流子浓度越低或长度Lb越长则保护单元Dclamp的空乏区越宽,因此其反向导通电压Vclamp越高,此处所提及的空乏区意谓靠近p型阻障层Pb与通道层96接面处,没有可移动载流子的区域。在经由适当的调整p型阻障层Pb的载流子浓度与p型阻障层Pb的长度Lb下,保护单元Dclamp的反向导通电压Vclamp可以满足小于高电子迁移率场效晶体管T1击穿电压Vbreak的需求。综合来说,由于本实施例p型阻障层Pb能改变其下方二维电子云的浓度,也能调整保护单元Dclamp的反向导通电压Vclamp,故适当的调整p型阻障层Pb的载流子浓度与长度Lb,可以同时达到保护单元Dclamp的反向导通电压Vclamp小于高电子迁移率场效晶体管T1击穿电压Vbreak,以及当直流电压VDC-IN小于保护单元Dclamp反向导通电压Vclamp的情况下,保护单元Dclamp不导通的目的。本申请不以上述方法为限,亦可通过其他方式来达成上述的目的,举例而言于其他实施例中,也可将p型阻障层Pb另外形成于保护单元Dclamp的高价带间隙层98之上(未绘示),如同上述的原理,当p型阻障层Pb层形成在高价带间隙层98上时,p型阻障层Pb会改变费米能阶的位置,使得p型阻障层Pb所在位置的费米能阶远离导电带往价带的方向移动,一旦p型阻障层Pb所在位置的费米能阶位于导电带的下方时,则其下方位于通道层96内的二维电子云完全空乏。一般而言p型阻障层Pb的掺杂浓度会与载流子浓度正相关,而p型阻障层Pb的载流子浓度会分别影响二维电子云的浓度。特别说明的是,在p型阻障层Pb层形成在高价带间隙层98上时,p型阻障层Pb层的厚度与二维电子云的浓度较无关联,主要会通过调整p型阻障层Pb的载流子浓度使p型阻障层Pb下方位于通道层96中的二维电子云完全空乏,并通过调整p型阻障层Pb的载流子浓度、厚度Tb与长度Lb来改变能保护单元Dclamp的反向导通电压Vclamp的大小,其原理如上所述,在此不再赘述。In addition, the carrier concentration and length Lb of the p-type barrier layer Pb also affect the width of the depletion region between the p-type barrier layer Pb and the channel layer 96 . Since the reverse conduction voltage V clamp of the protection unit D clamp is affected by the concentration of the two-dimensional electron cloud and the width of the depletion region between the p-type barrier layer Pb and the channel layer 96, the p-type resistance can also be adjusted by adjusting the The carrier concentration, length Lb, and thickness Tb of the barrier layer Pb change the magnitude of the reverse conduction voltage V clamp . In detail, the reverse conduction voltage V clamp of the protection unit D clamp is negatively correlated with the carrier concentration of the p-type barrier layer Pb, and positively correlated with the length Lb of the p-type barrier layer Pb. The lower or the longer the length Lb, the wider the depletion region of the protection unit D clamp , so the reverse conduction voltage V clamp is higher. The depletion region mentioned here means that the depletion region is close to the p-type barrier layer Pb and is connected to the channel layer 96. At the surface, there is no region of mobile carriers. By properly adjusting the carrier concentration of the p-type barrier layer Pb and the length Lb of the p-type barrier layer Pb, the reverse conduction voltage V clamp of the protection unit D clamp can be smaller than that of the high electron mobility field effect transistor T1 Breakdown voltage V break requirement. To sum up, since the p-type barrier layer Pb in this embodiment can change the concentration of the two-dimensional electron cloud below it, and can also adjust the reverse conduction voltage V clamp of the protection unit D clamp , the p-type barrier layer Pb can be adjusted appropriately The carrier concentration and length Lb can be achieved at the same time when the reverse conduction voltage Vclamp of the protection unit D clamp is smaller than the breakdown voltage V break of the high electron mobility field effect transistor T1, and when the DC voltage V DC-IN is smaller than the protection unit D clamp In the case of the reverse conduction voltage V clamp , the purpose of the protection unit D clamp not to conduct conduction. The present application is not limited to the above-mentioned method, and other methods can also be used to achieve the above-mentioned purpose. For example, in other embodiments, the p-type barrier layer Pb can also be additionally formed on the high-valence band gap layer of the protection unit D clamp . Above 98 (not shown), as the above-mentioned principle, when the p-type barrier layer Pb layer is formed on the high-valence band gap layer 98, the p-type barrier layer Pb will change the position of the Fermi level, so that the p-type barrier layer Pb will change the position of the Fermi level. The Fermi energy level at the position of the barrier layer Pb moves away from the conduction band to the direction of the valence band. Once the Fermi energy level at the position of the p-type barrier layer Pb is located below the conduction band, the lower part is located in the channel layer 96 The 2D electron cloud is completely depleted. Generally speaking, the doping concentration of the p-type barrier layer Pb is positively correlated with the carrier concentration, and the carrier concentration of the p-type barrier layer Pb affects the concentration of the two-dimensional electron cloud respectively. It is particularly noted that when the p-type barrier layer Pb layer is formed on the high-valence band gap layer 98, the thickness of the p-type barrier layer Pb layer is relatively independent of the concentration of the two-dimensional electron cloud, and is mainly adjusted by adjusting the p-type barrier layer. The carrier concentration of the barrier layer Pb makes the two-dimensional electron cloud located in the channel layer 96 under the p-type barrier layer Pb completely depleted, and is adjusted by adjusting the carrier concentration, thickness Tb and length Lb of the p-type barrier layer Pb. The principle of changing the magnitude of the reverse conduction voltage V clamp capable of protecting the unit D clamp is as described above and will not be repeated here.

在完成平台区95后,还可以参考图14步骤144的方式,利用外延成长或是溅镀的方式以及搭配图案化的流程,在一道制作工艺中将绝缘层103a分别成长于萧基特二极管SBD1的高价带间隙层98上方、高电子迁移率场效晶体管T1的高价带间隙层98上方,以及保护单元Dclamp的高价带间隙层98上方,举例来说可以用金属有机物化学气相外延法(metal-organic chemical vapor deposition,MOCVD)或分子束外延法(molecular-beamepitaxy,MBE)等方式外延成长绝缘层103a。在本实施例中,绝缘层103a大致覆盖高价带间隙层98的表面,其作用为改善表面漏电流,以及保护高价带间隙层98的表面。绝缘层103a可以是绝缘材料或高阻值材料,包含氮化物绝缘材料,如氮化硅(SiNx),氧化物绝缘材料,如二氧化硅(SiO2),或是p型的三五族半导体,如p型氮化镓层(p-GaN)。After the platform region 95 is completed, referring to step 144 in FIG. 14, the insulating layer 103a can be grown on the Schottky diode SBD1 in one manufacturing process by epitaxial growth or sputtering and patterning process. Above the high valence band gap layer 98 of the high electron mobility field effect transistor T1, and above the high valence band gap layer 98 of the protection unit D clamp , for example, metal organic chemical vapor phase epitaxy (metal -organic chemical vapor deposition, MOCVD) or molecular beam epitaxy (molecular-beamepitaxy, MBE) and other methods to epitaxially grow the insulating layer 103a. In this embodiment, the insulating layer 103 a substantially covers the surface of the high-valence bandgap layer 98 , which functions to improve the surface leakage current and protect the surface of the high-valence bandgap layer 98 . The insulating layer 103a may be an insulating material or a high-resistance material, including a nitride insulating material, such as silicon nitride (SiN x ), an oxide insulating material, such as silicon dioxide (SiO 2 ), or a p-type III-V group Semiconductors, such as p-type gallium nitride layers (p-GaN).

然而本申请不以上述为限,也可以其他具有相同特性的材料取代之,另外,绝缘层103a的位置也不限于本申请的揭露内容。However, the present application is not limited to the above, and other materials with the same characteristics can also be substituted for it. In addition, the position of the insulating layer 103a is not limited to the disclosure of the present application.

在绝缘层103a制作完毕制后,在同一道制作工艺中(请参考图14步骤142),分别于萧基特二极管SBD1及高电子迁移率场效晶体管T1和保护单元Dclamp的绝缘层103b上方沉积金属层(未绘示),并将金属层图案化以形成多个金属片102’a、102’b、102’c、102’d、102’e。在本实施例中,可以通过选择适当的金属层材料(如钛/铝/钛/金),以及/或者通过制作工艺(如,热退火)以使多个金属片102’a、102’b、102’c、102’d、102’e、102’f和高价带间隙层98之间形成欧姆接触。其中,金属片102’a、102’b作为萧基特二极管SBD1的阳极Asbd1与阴极Csbd1;金属片102’c、102’d作为高电子迁移率场效晶体管T1的源极Shemt1与漏极Dhemt1;金属片102’e、102’f作为保护单元Dclamp的阳极Aclamp与阴极Cclamp。在多个电极Asbd1、Csbd1、Shemt1、Dhemt1、Aclamp、Cclamp制作完毕后,可参考图14步骤146,在高电子迁移率场效晶体管T1上方沉积金属层(未绘示),并将金属层图案化以形成金属片104’a。在本实施例中,可以通过选择适当的金属层材料(如镍/金/铂),以使金属片104’a和高价带间隙层98之间形成萧特基接触。其中,金属片104’a作为高电子迁移率场效晶体管T1的栅极Ghemt1After the insulating layer 103a is fabricated, in the same fabrication process (please refer to step 142 in FIG. 14 ), the insulating layers 103b of the Schottky diode SBD1, the high electron mobility field effect transistor T1 and the protection unit D clamp are respectively placed over the insulating layer 103b. A metal layer (not shown) is deposited and patterned to form a plurality of metal sheets 102'a, 102'b, 102'c, 102'd, 102'e. In this embodiment, the plurality of metal sheets 102'a, 102'b may be formed by selecting an appropriate metal layer material (eg, titanium/aluminum/titanium/gold) and/or by a fabrication process (eg, thermal annealing). Ohmic contacts are formed between , 102 ′ c , 102 ′ d , 102 ′ e , 102 ′ f and the high valence band gap layer 98 . The metal sheets 102'a and 102'b are used as the anode A sbd1 and the cathode C sbd1 of the Schottky diode SBD1; the metal sheets 102'c and 102'd are used as the source electrodes S hemt1 and C sbd1 of the high electron mobility field effect transistor T1. The drain D hemt1 ; the metal sheets 102'e and 102'f serve as the anode A clamp and the cathode C clamp of the protection unit D clamp . After the multiple electrodes Asbd1 , C sbd1 , Shemt1 , D hemt1 , A clamp and C clamp are fabricated, referring to step 146 in FIG. 14 , a metal layer (not shown) is deposited over the high electron mobility field effect transistor T1 , and patterning the metal layer to form a metal sheet 104'a. In this embodiment, a Schottky contact can be formed between the metal sheet 104 ′ a and the high-valence bandgap layer 98 by selecting an appropriate metal layer material (eg, nickel/gold/platinum). The metal sheet 104'a is used as the gate G hemt1 of the high electron mobility field effect transistor T1.

在形成上述的栅极Ghemt1之后,还可以进一步形成绝缘层103b以覆盖高价带间隙层98,以防止高价带间隙层98因水气而劣化,造成电性上的影响。而在本实施例中,绝缘层103b的材料请参考先前对于绝缘层103a的叙述,在此不再赘述。另外,为了使上述电极便于与外界电连接,在绝缘层103b制作完成之后,还可分别于基底91上形成如图38所示的多个接点C、N、L、A、TD1、TD2、TSG、E、F。其中接点C、N、L、A用来与萧基特二极管SBD1、SBD2、SBD3、SBD4的阳极Asbd1~sbd4与阴极Csbd1~sbd4连接(详细连接方式请参考下文);接点TD1、TD2分别用来与高电子迁移率场效晶体管T1、T2的漏极Dhemt1、Dhemt2连接;接点TSG与高电子迁移率场效晶体管T1的源极Shemt1和栅极Ghemt1,以及高电子迁移率场效晶体管T2的源极Shemt2和栅极Ghemt2连接;接点E与接点F分别与保护单元Dclamp的阳极Aclamp与阴极Cclamp连接。在图39中仅列举与萧基特二极管SBD1、高电子迁移率场效晶体管T1和保护单元Dclamp相关的接点A、N、TD1、TSG、E、F。其中,接点A与接点N分别萧基特二极管SBD1的阳极Asbd1与阴极Csbd1连接;接点TSG与高电子迁移率场效晶体管T1的源极Shemt1和栅极Ghemt1连接,接点TD1与高电子迁移率场效晶体管T1的漏极Dhemt1连接;接点E与接点F分别与保护单元Dclamp的阳极Aclamp与阴极Cclamp连接。萧基特二极管SBD2、SBD3、SBD4以及高电子迁移率场效晶体管T2的结构与形成方式,与萧基特二极管SBD1以及高电子迁移率场效晶体管T1的结构和形成方式相同,请参考上述有关于萧基特二极管SBD1以及高电子迁移率场效晶体管T1的说明,在此不再赘述。After the above-mentioned gate G hemt1 is formed, an insulating layer 103b may be further formed to cover the high-valence bandgap layer 98 to prevent the high-valence bandgap layer 98 from deteriorating due to moisture, which may affect electrical properties. In this embodiment, for the material of the insulating layer 103b, please refer to the previous description of the insulating layer 103a, which will not be repeated here. In addition, in order to facilitate the electrical connection between the above-mentioned electrodes and the outside world, after the insulating layer 103b is fabricated, a plurality of contacts C, N, L, A, TD1, TD2, TSG as shown in FIG. 38 can be formed on the substrate 91 respectively. , E, F. The contacts C, N, L, and A are used to connect the anodes A sbd1 to sbd4 of Schottky diodes SBD1, SBD2, SBD3, and SBD4 with the cathodes C sbd1 to sbd4 (for detailed connection methods, please refer to the following); contacts TD1 and TD2 are respectively Used to connect with the drains D hemt1 and D hemt2 of the high electron mobility field effect transistors T1 and T2; the contact TSG is connected to the source S hemt1 and the gate G hemt1 of the high electron mobility field effect transistor T1, and the high electron mobility The source S hemt2 and the gate G hemt2 of the field effect transistor T2 are connected; the contacts E and F are respectively connected to the anode A clamp and the cathode C clamp of the protection unit D clamp . In FIG. 39, only the contacts A, N, TD1, TSG, E, and F related to the Schottky diode SBD1, the high electron mobility field effect transistor T1, and the protection unit D clamp are listed. Among them, the contact point A and the contact point N are respectively connected with the anode A sbd1 and the cathode C sbd1 of the Schottky diode SBD1; the contact TSG is connected with the source S hemt1 and the gate G hemt1 of the high electron mobility field effect transistor T1, and the contact TD1 is connected with the high The drain D hemt1 of the electron mobility field effect transistor T1 is connected; the contact point E and the contact point F are respectively connected to the anode A clamp and the cathode C clamp of the protection unit D clamp . The structure and formation of the Schottky diodes SBD2, SBD3, SBD4 and the high electron mobility field effect transistor T2 are the same as those of the Schottky diode SBD1 and the high electron mobility field effect transistor T1. Please refer to the above The description of the Schottky diode SBD1 and the high electron mobility field effect transistor T1 will not be repeated here.

在本申请中,为了实现图36A的电连接关系,如图38所示,接点A除了连接萧基特二极管SBD1的阳极Asbd1外,还会连接萧基特二极管SBD2的阳极Asbd2;接点N除了连接萧基特二极管SBD1的阴极Csbd1外,还会连接萧基特二极管SBD4的阳极Asbd4;接点L连接萧基特二极管SBD3的阳极Asbd3与萧基特二极管SBD2的阴极Csbd2;接点C连接萧基特二极管SBD3的阴极Csbd3与萧基特二极管SBD4的阴极Csbd4;接点TSG除了连接高电子迁移率场效晶体管T1的源极Shemt1和栅极Ghemt1外,还与高电子迁移率场效晶体管T2的源极Shemt2和栅极Ghemt2连接;接点TD1与高电子迁移率场效晶体管T1的漏极Dhemt1连接;接点TD2与高电子迁移率场效晶体管T2的漏极Dhemt2连接;接点E与接点F则如上所述地分别与保护单元Dclamp的阳极Aclamp与阴极Cclamp连接。In this application, in order to realize the electrical connection relationship in FIG. 36A, as shown in FIG. 38, the contact point A is connected to the anode Asbd2 of the Schottky diode SBD2 in addition to the anode Asbd1 of the Schottky diode SBD1 ; the contact point N In addition to connecting the cathode C sbd1 of the Schottky diode SBD1, the anode A sbd4 of the Schottky diode SBD4 will also be connected; the contact point L connects the anode A sbd3 of the Schottky diode SBD3 and the cathode C sbd2 of the Schottky diode SBD2; the contact point C connects the cathode C sbd3 of the Schottky diode SBD3 and the cathode C sbd4 of the Schottky diode SBD4 ; the contact TSG not only connects the source S hemt1 and the gate G hemt1 of the high electron mobility field effect transistor T1, but also connects with the high electron The source S hemt2 and the gate G hemt2 of the mobility field effect transistor T2 are connected; the contact TD1 is connected with the drain D hemt1 of the high electron mobility field effect transistor T1; the contact TD2 is connected with the drain of the high electron mobility field effect transistor T2 D hemt2 is connected; the contacts E and F are respectively connected to the anode A clamp and the cathode C clamp of the protection unit D clamp as described above.

在上述多个接点A、C、E、F、L、N、TD1、TD2、TSG形成之后,还可以选择性的形成绝缘层103c于平台区95的侧面与多个接点A、C、E、F、L、N、TD1、TD2、TSG的表面上,以防止元件因水气而劣化的情况产生,并视情况裸露接点A、C、E、F、L、N、TD1、TD2、TSG的部分表面,以供电连接用。在上述的绝缘层完成之后,即完成本申请的LED驱动器60c。在实际运作时,请参考图36A与图38,将交流输入电源AC-source的一端与桥式整流器62的接点L电连接,而将交流输入电源AC-source的另一端与桥式整流器62的接点N电连接;将LED 18的一端与电流驱动电路66的接点TD1与接点TD2电连接,且将LED 18的另一端与桥式整流器62的接点C电连接;将电流驱动电路66的接点TSG与桥式整流器62的接点A电连接;将保护电路63的接点E与桥式整流器62的接点A连接;将保护电路63的接点F与桥式整流器62的接点C连接。After the above-mentioned multiple contacts A, C, E, F, L, N, TD1, TD2, and TSG are formed, an insulating layer 103c can also be selectively formed on the side surface of the mesa region 95 and the multiple contacts A, C, E, On the surface of F, L, N, TD1, TD2, TSG, to prevent the deterioration of components due to moisture, and expose contacts A, C, E, F, L, N, TD1, TD2, TSG as appropriate Part of the surface is used for power connection. After the above-mentioned insulating layer is completed, the LED driver 60c of the present application is completed. In actual operation, please refer to FIGS. 36A and 38 , one end of the AC input power source AC-source is electrically connected to the contact L of the bridge rectifier 62 , and the other end of the AC input power source AC-source is electrically connected to the bridge rectifier 62 . The contact point N is electrically connected; one end of the LED 18 is electrically connected to the contact points TD1 and TD2 of the current drive circuit 66, and the other end of the LED 18 is electrically connected to the contact point C of the bridge rectifier 62; the contact point TSG of the current drive circuit 66 is electrically connected It is electrically connected to the contact point A of the bridge rectifier 62 ; the contact point E of the protection circuit 63 is connected to the contact point A of the bridge rectifier 62 ; the contact point F of the protection circuit 63 is connected to the contact point C of the bridge rectifier 62 .

综上所述,本申请的一实施例的LED驱动器包含一填谷电路,可使直流电源的最小值电压维持在电压峰值的一半,由此足以提供足够的电压使发光元件持续发光。本申请的另一实施例的LED驱动器包含一保护单元,可避免因突波而造成LED驱动器中的电流驱动电路的高电子迁移率场效晶体管崩坏,进而达到保护发光元件的功效。本申请的再一实施例的LED驱动器包含一填谷电路与一保护单元,而可达成足以提供足够的电压使发光元件持续发光并保护发光元件的功效。以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。To sum up, the LED driver of an embodiment of the present application includes a valley filling circuit, which can maintain the minimum voltage of the DC power supply at half of the peak voltage, thereby providing sufficient voltage to keep the light-emitting element emitting light. The LED driver of another embodiment of the present application includes a protection unit, which can prevent the high electron mobility field effect transistor of the current driving circuit in the LED driver from breaking down due to surge, thereby achieving the effect of protecting the light-emitting element. The LED driver of another embodiment of the present application includes a valley-fill circuit and a protection unit, and can achieve the effect of providing sufficient voltage to keep the light-emitting element emitting light and protecting the light-emitting element. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (9)

1.一种驱动器,用以驱动一发光元件,包含有:1. A driver for driving a light-emitting element, comprising: 整流电路,包含一整流二极管,用以接收一交流输入电源并转换成一直流电源,该直流电源包含一直流电流及一直流电压;a rectifier circuit, comprising a rectifier diode for receiving an AC input power and converting it into a DC power supply, the DC power supply comprising a DC current and a DC voltage; 电流驱动电路,包含定电流单元,其中该整流电路、该电流驱动电路与该发光元件三者串联,该电流驱动电路用以限制该直流电流的大小以驱动该发光元件;以及a current driving circuit, comprising a constant current unit, wherein the rectifier circuit, the current driving circuit and the light-emitting element are connected in series, and the current driving circuit is used to limit the magnitude of the direct current to drive the light-emitting element; and 保护电路,包含保护单元,其中,该保护电路跨接该电流驱动电路与该发光元件,当该直流电压大于一定值时,该直流电流流向该保护电路;a protection circuit, including a protection unit, wherein the protection circuit bridges the current driving circuit and the light-emitting element, and when the DC voltage is greater than a certain value, the DC current flows to the protection circuit; 其中,该整流二极管、该定电流单元和该保护单元共用一基底;Wherein, the rectifier diode, the constant current unit and the protection unit share a substrate; 其中,该整流二极管、该定电流单元和该保护单元分别包含半导体叠层,该些半导体叠层的结构及构成材料相同。Wherein, the rectifier diode, the constant current unit and the protection unit respectively comprise semiconductor stacks, and the structures and constituent materials of the semiconductor stacks are the same. 2.如权利要求1所述的驱动器,其中该些半导体叠层外延形成于该基底上。2. The driver of claim 1, wherein the semiconductor stacks are epitaxially formed on the substrate. 3.如权利要求2所述的驱动器,其中,该些半导体叠层分别包含位于该基底上的缓冲层、位于该缓冲层上的通道层、位于该通道层上的高价带间隙层。3. The driver of claim 2, wherein the semiconductor stacks respectively comprise a buffer layer on the substrate, a channel layer on the buffer layer, and a high valence bandgap layer on the channel layer. 4.如权利要求3所述的驱动器,其中,该保护单元还包含位于该通道层之上的p型阻障层。4. The driver of claim 3, wherein the protection unit further comprises a p-type barrier layer over the channel layer. 5.如权利要求4所述的驱动器,其中,该p型阻障层的厚度大于该高价带间隙层。5. The driver of claim 4, wherein the p-type barrier layer is thicker than the high valence bandgap layer. 6.如权利要求3所述的驱动器,其中,该保护单元为钳位二极管。6. The driver of claim 3, wherein the protection unit is a clamping diode. 7.如权利要求1所述的驱动器,其中,该定电流单元、该保护单元或该整流二极管为一多指状结构的高电子迁移率场效晶体管。7 . The driver of claim 1 , wherein the constant current unit, the protection unit or the rectifier diode is a high electron mobility field effect transistor with a multi-finger structure. 8 . 8.如权利要求1所述的驱动器,其中,该整流二极管的数目为多个,该定电流单元的数目为多个。8 . The driver of claim 1 , wherein the number of the rectifier diodes is plural, and the number of the constant current unit is plural. 9 . 9.如权利要求8所述的驱动器,其中,该多个整流二极管阵列排列。9. The driver of claim 8, wherein the plurality of rectifier diodes are arranged in an array.
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