CN108766490A - A kind of element circuit and design method of dynamic memory - Google Patents
A kind of element circuit and design method of dynamic memory Download PDFInfo
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- CN108766490A CN108766490A CN201810548266.8A CN201810548266A CN108766490A CN 108766490 A CN108766490 A CN 108766490A CN 201810548266 A CN201810548266 A CN 201810548266A CN 108766490 A CN108766490 A CN 108766490A
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- 230000015654 memory Effects 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 114
- 230000000737 periodic effect Effects 0.000 claims abstract description 16
- 230000014759 maintenance of location Effects 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims description 45
- 230000005611 electricity Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses a kind of element circuit of dynamic memory and design methods,Including the first circuit of multiple storages,The first circuit of storage includes storage member and ON-OFF control circuit,Storage member is capacitance,The ON-OFF control circuit includes switching circuit and control circuit,The signal input of the first circuit of switching circuit control storage,The control circuit receives the signal of switching circuit and carries out information storage to control storage member,High potential one end of the storage member is connected with the switching circuit input terminal of next storage member,Form the first circuit series connection of several storages,Switching circuit one is opened,The signal of a upper storage unit is transferred to the first circuit of next storage,First circuit will be stored from the beginning into line label,The switching circuit control terminal that odd column is stored to first input terminal is connected to same conducting wire A,The switching circuit control terminal that even column is stored to first input terminal is connected to same conducting wire B,To A,B conducting wires are passed through periodic electric signal successively,So that signal carries out transfer storage.
Description
Technical field
The present invention relates to a kind of dynamic memories, and in particular to a kind of element circuit and design method of dynamic memory.
Background technology
Memory is in modern information technologies for protecting stored memory device.The major function of memory is storage journey
Sequence and various memory datas, and can in computer operational process high speed, be automatically completed the accesses of program or data.Storage
Device is the equipment with " memory " function, it stores information using the physical device of stable state there are two types of having.These devices
Also referred to as memory cell.Data are indicated using the only binary system of two numbers " 0 " and " 1 " in a computer.Memory cell
Two kinds of stable states be expressed as " 0 " and " 1 ".Constitute memory storage medium, storage member, it can store one two into
Code processed.A storage unit is formed by several storage members, then forms a memory by many storage units again.Generally
The random access memory (RAM) that computer system uses can point dynamic random access memory (DRAM) and static random access memory
(SRAM) two kinds, difference is that DRAM needs by memorizer control circuit just maintain number to memory refress by some cycles
According to preservation, the data of SRAM do not need refresh process then, and during powering on, data will not lose.
Invention content
The present invention provides a kind of element circuit of dynamic memory and design method, it can be achieved that dynamic data storage, line
Road is simply easily integrated, and storage speed is fast.
The present invention is achieved through the following technical solutions：
A kind of element circuit of dynamic memory, including the first circuit of multiple storages, the first circuit of the storage includes that N ditches are enhanced
The drain electrode of MOS field effect transistor M1, the MOS field effect transistor M1 are the data input pin of the first circuit of storage, and the source electrode of MOS field effect transistor M1 connects NPN type three
The base stage of pole pipe, the collector of the triode connect the grid of resistance and the enhanced MOS field effect transistor M2 of P ditches, the resistance simultaneously
DC power anode is connected with the source electrode of MOS field effect transistor M2, the drain electrode of MOS field effect transistor M2 connects capacitance, the hair of the capacitance and triode
Emitter-base bandgap grading connects the cathode of DC power supply, while the drain electrode of MOS field effect transistor M2 is also as the data output end for storing first circuit；The number
It is connected with the data input pin of the first circuit of next storage according to output end, the first circuit series connection of several storages is formed, by storage member
For circuit from first into line label, the first circuit of first storage is U1, and the first circuit of second storage is U2, and n-th is storage member
Circuit is Un, therefore, the storage member circuit for forming odd bits label be U2, U4 of U1, U3, U (2n+1) and even bit label,
U (2n), the first circuit U 1 of odd bits label storage, U3, U (2n+1) MOS field effect transistor M1 Gate bond wires A, the even number
The first circuit U 2 of position label storage, U4, U (2n) MOS field effect transistor M1 Gate bond wires B, when work, be passed through successively to A, B conducting wire
Periodic electric signal.When A conducting wires are powered, data enter from the MOS field effect transistor M1 of first storage member circuit U 1, and triode is led
Logical, resistive voltage increases, and MOS field effect transistor M2 is opened, and capacitance charges, and A conducting wires stop being powered, and B conducting wires are powered, second storage
The MOS field effect transistor of first circuit U 2 is opened, and the capacitance of first storage member circuit U 1 discharges, and first circuit is then stored with first
Same process so that the capacitor charging of the first circuit of second storage, thus repeatedly, data volume is stored in each storage circuit
In, when work, it is identical as the signal frequency that AB conducting wires are passed through that data input frequency, is supplied to AB to lead therefore it may only be necessary to improve
The signal frequency of line can improve storage speed, and circuit is simply easily integrated, and read or write speed is fast.
Further, periodic electric signal is the electric signal that sinusoidal ac is divided into upper half period and lower half period,
The upper half periodic electric signal of sinusoidal ac is connect with conducting wire A, the lower half periodic electric signal of sinusoidal ac and conducting wire B are connected
It connects, A, B guide roller conductance electricity, the frequency for reading in data is identical as simple alternating current electric frequency.
Further, sinusoidal ac be with diode one-way guide flow it is positive and negative it is electrically separated come out.
Further, the source electrode of the substrate connection MOS field effect transistor M1 of MOS field effect transistor M1, the substrate connection field effect of the MOS field effect transistor M2
The source electrode of pipe M2.Substrate is connected with source electrode, is mainly used as switching circuit.
A kind of design method of the element circuit of dynamic memory, including the first circuit of multiple storages, the first circuit packet of the storage
Storage member and ON-OFF control circuit are included, the storage member is capacitance, and the ON-OFF control circuit includes switching circuit and control
Circuit processed, the signal input of the first circuit of switching circuit control storage, the control circuit receive the signal of switching circuit from
And control storage member and carry out information storage, high potential one end of the storage member and the switching circuit of next storage member are inputted
End is connected, and forms the first circuit series connection of several storages, and switching circuit one is opened, the signal of a upper storage unit is transferred to down
Odd column is stored the switching circuit control terminal of first input terminal by the first circuit of one storage by the first circuit of storage from the beginning into line label
It is connected to same conducting wire A, the switching circuit control terminal that even column is stored to first input terminal is connected to same conducting wire B, to A, B conducting wire
It is passed through periodic electric signal successively so that signal carries out transfer storage.
The present invention has the advantage that and advantageous effect：
1, data input frequency of the present invention is identical as the signal frequency that AB conducting wires are passed through, therefore it may only be necessary to improve offer
Storage speed can be improved to the signal frequency of AB conducting wires, read or write speed is fast；
2, circuit of the present invention is simply easily integrated.
Description of the drawings
Attached drawing described herein is used for providing further understanding the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings：
Fig. 1 is the circuit diagram of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation are only used for explaining the present invention, do not make
For limitation of the invention.
Embodiment 1
As shown in Figure 1, a kind of element circuit of dynamic memory, including the first circuit of multiple storages, the first circuit packet of the storage
The drain electrode for including N ditches enhanced MOS field effect transistor M1, the MOS field effect transistor M1 is the data input pin of the first circuit of storage, the source electrode of MOS field effect transistor M1
The base stage of NPN type triode is connected, the collector of the triode connects the grid of resistance and the enhanced MOS field effect transistor M2 of P ditches simultaneously
Pole, the resistance and the source electrode of MOS field effect transistor M2 connect DC power anode, and the drain electrode of MOS field effect transistor M2 connects capacitance, the capacitance and
The cathode of the emitter connection DC power supply of triode, while the drain electrode of the MOS field effect transistor M2 also data output as the first circuit of storage
End；The data output end is connected with the data input pin of the first circuit of next storage, forms the first circuit series connection of several storages,
Will the first circuit of storage from first into line label, the first circuit of first storage is U1, and the first circuit of second storage is U2, n-th
It is Un for the first circuit of storage, therefore, the storage member circuit for forming odd bits label is U1, U3, U (2n+1) and even bit label
U2, U4, U (2n), the first circuit U 1 of odd bits label storage, U3, U (2n+1) MOS field effect transistor M1 Gate bond wires A,
The first circuit U 2 of even bit label storage, U4, U (2n) MOS field effect transistor M1 Gate bond wires B, when work, to A, B conducting wire
It is passed through periodic electric signal successively；Periodic electric signal is the electricity that sinusoidal ac is divided into upper half period and lower half period
The upper half periodic electric signal of sinusoidal ac is connect by signal with conducting wire A, by the lower half periodic electric signal of sinusoidal ac with lead
Line B connections, A, B guide roller conductance electricity, the frequency for reading in data are identical as simple alternating current electric frequency；Sinusoidal ac is with two poles
Pipe one-way guide flow it is positive and negative it is electrically separated out；The source electrode of the substrate connection MOS field effect transistor M1 of MOS field effect transistor M1, the lining of the MOS field effect transistor M2
Bottom connects the source electrode of MOS field effect transistor M2.When implementation, sinusoidal ac is separated into upper half period and lower half by positive and negative diode
The electric signal in upper half period is led to and gives conducting wire A by the electric signal of phase, and the electricity in lower half period is led to and gives conducting wire B, when A, B conducting wire period
It is powered, when A conducting wires are powered, data enter from the MOS field effect transistor M1 of first storage member circuit U 1, triode ON, resistive voltage
It increases, MOS field effect transistor M2 openings, capacitance charges, and A conducting wires stop being powered, and B conducting wires are powered, the field of second storage member circuit U 2
It imitates pipe to open, the capacitance of first storage member circuit U 1 discharges, and then process same as the first circuit of first storage, makes
Second first circuit of storage capacitor charging, thus repeatedly, data are just stored in each first circuit of storage, in capacitor
Information be transferred in another capacitance, the frequency of its transfer velocity and sinusoidal ac determines, when work, data input frequency
Rate is identical as the signal frequency that AB conducting wires are passed through, and is supplied to the signal frequency of AB conducting wires that can carry therefore it may only be necessary to improve
High storage speed, when simple alternating current is electrically turn off, all MOS field effect transistors will close, and data will be stored in capacitance and will not move
It is dynamic.
A kind of design method of the element circuit of dynamic memory, described includes the first circuit of multiple storages, the storage member electricity
Road includes storage member and ON-OFF control circuit, and storage member is capacitance, the ON-OFF control circuit include switching circuit with
And control circuit, the signal input of the first circuit of switching circuit control storage, the control circuit receive the letter of switching circuit
Number to control storage member carry out information storage, by it is described storage member high potential one end with it is next storage member switching circuit
Input terminal is connected, and forms the first circuit series connection of several storages, and switching circuit one is opened, the signal of a upper storage unit is shifted
Odd column is stored to the switching circuit control of first input terminal to the first circuit of next storage by the first circuit of storage from the beginning into line label
End processed is connected to same conducting wire A, and the switching circuit control terminal that even column is stored to first input terminal is connected to same conducting wire B, to A, B
Conducting wire is passed through periodic electric signal successively so that signal carries out transfer storage.
Above-described specific implementation mode has carried out further the purpose of the present invention, technical solution and advantageous effect
It is described in detail, it should be understood that the foregoing is merely the specific implementation mode of the present invention, is not intended to limit the present invention
Protection domain, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (5)
1. a kind of element circuit of dynamic memory, which is characterized in that including the first circuit of multiple storages, the first circuit of the storage includes
The drain electrode of N ditches enhanced MOS field effect transistor M1, the MOS field effect transistor M1 are the data input pin of the first circuit of storage, and the source electrode of MOS field effect transistor M1 connects
The base stage of NPN type triode is connect, the collector of the triode connects the grid of resistance and the enhanced MOS field effect transistor M2 of P ditches simultaneously
Pole, the resistance and the source electrode of MOS field effect transistor M2 connect DC power anode, and the drain electrode of MOS field effect transistor M2 connects capacitance, the capacitance and
The cathode of the emitter connection DC power supply of triode, while the drain electrode of the MOS field effect transistor M2 also data output as the first circuit of storage
End；The data output end is connected with the data input pin of the first circuit of next storage, forms the first circuit series connection of several storages,
Will the first circuit of storage from first into line label, the first circuit of first storage is U1, and the first circuit of second storage is U2, n-th
It is Un for the first circuit of storage, therefore, the storage member circuit for forming odd bits label is U1, U3, U (2n+1) and even bit label
U2, U4, U (2n), the first circuit U 1 of odd bits label storage, U3, U (2n+1) MOS field effect transistor M1 Gate bond wires A,
The first circuit U 2 of even bit label storage, U4, U (2n) MOS field effect transistor M1 Gate bond wires B, when work, to A, B conducting wire
It is passed through periodic electric signal successively.
2. a kind of element circuit of dynamic memory according to claim 1, which is characterized in that the periodic electric signal
The electric signal that sinusoidal ac is divided into upper half period and lower half period, by the upper half periodic electric signal of sinusoidal ac with lead
Line A connections, the lower half periodic electric signal of sinusoidal ac is connect with conducting wire B, and A, B guide roller conductance electricity read in the frequency of data
Rate is identical as simple alternating current electric frequency.
3. a kind of element circuit of dynamic memory according to claim 2, which is characterized in that the sinusoidal ac is to use
Diode one-way guide flow it is positive and negative it is electrically separated out.
4. a kind of element circuit of dynamic memory according to claim 1, which is characterized in that the substrate of the MOS field effect transistor M1
Connect the source electrode of MOS field effect transistor M1, the source electrode of the substrate connection MOS field effect transistor M2 of the MOS field effect transistor M2.
5. a kind of design method of the element circuit of dynamic memory, which is characterized in that described includes the first circuit of multiple storages, described
The first circuit of storage includes storage member and ON-OFF control circuit, and the storage member is capacitance, and the ON-OFF control circuit includes opening
Powered-down road and control circuit, the signal input of the first circuit of switching circuit control storage, the control circuit receive switch
The signal of circuit carries out information storage to control storage member, by high potential one end of the storage member and next storage member
Switching circuit input terminal is connected, and forms the first circuit series connection of several storages, switching circuit one is opened, by a upper storage unit
Signal is transferred to the first circuit of next storage, and by the first circuit of storage from the beginning into line label, odd column is stored opening for first input terminal
Powered-down road control terminal is connected to same conducting wire A, and the switching circuit control terminal that even column is stored to first input terminal is connected to same lead
Line B is passed through periodic electric signal so that signal carries out transfer storage successively to A, B conducting wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810548266.8A CN108766490A (en) | 2018-05-31 | 2018-05-31 | A kind of element circuit and design method of dynamic memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810548266.8A CN108766490A (en) | 2018-05-31 | 2018-05-31 | A kind of element circuit and design method of dynamic memory |
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| CN108766490A true CN108766490A (en) | 2018-11-06 |
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| CN201810548266.8A Pending CN108766490A (en) | 2018-05-31 | 2018-05-31 | A kind of element circuit and design method of dynamic memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127236A (en) * | 2002-01-11 | 2008-02-20 | 索尼公司 | Memory cell circuit |
| CN101339804A (en) * | 2006-11-03 | 2009-01-07 | 台湾积体电路制造股份有限公司 | Integrated circuit, static random access memory circuit and memory circuit control method |
-
2018
- 2018-05-31 CN CN201810548266.8A patent/CN108766490A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127236A (en) * | 2002-01-11 | 2008-02-20 | 索尼公司 | Memory cell circuit |
| CN101339804A (en) * | 2006-11-03 | 2009-01-07 | 台湾积体电路制造股份有限公司 | Integrated circuit, static random access memory circuit and memory circuit control method |
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Application publication date: 20181106 |
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