CN108807275A - The production method of semiconductor devices - Google Patents

Abstract

A method for forming a semiconductor device, comprising: providing a base structure, the base structure including a transistor, the transistor including a gate structure and source and drain electrodes located on both sides of the gate structure; performing pre-cleaning; performing After pre-cleaning, a metal layer is formed at least on the surface of the source and the drain; doping dopant to the surface of the source and the drain, the type of the dopant is the same as that of the source and the drain The doping type is the same; annealing is performed to make the metal layer doped with the dopant react with the surface layers of the source and drain to form metal silicide. The technical solution of the invention further reduces the contact resistance of the transistor source and drain.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device.

Background technique

With the continuous shrinking of the integrated circuit process node, the contact area of the source, drain and plug of the transistor is getting smaller and smaller, so that the contact resistance of the source, drain and plug of the transistor increases accordingly, which affects the transistor's electrical properties. In order to reduce the contact resistance of the source and the drain, metal silicide is generally formed on the surfaces of the source and the drain. The method for forming the metal silicide includes: forming a metal layer on the surface of the transistor, and then performing annealing treatment, so that the metal layer reacts with the surface layers of the source electrode and the drain electrode to form a metal silicide, and finally, removing the unreacted metal layer . However, with the further shrinking of the process node of the integrated circuit, reducing the contact resistance only by metal silicide can no longer meet the requirements of the device. How to further reduce the contact resistance of the source and drain has become a technical problem to be solved urgently in the industry.

Contents of the invention

The technical problem to be solved by the invention: how to further reduce the contact resistance of the source and drain of the transistor.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, which includes: providing a base structure, the base structure includes a transistor, the transistor includes a gate structure and source and drain on the side; perform pre-cleaning; after performing the pre-cleaning, at least form a metal layer on the surface of the source and drain; dope dopant to the surface of the source and drain, The type of the dopant is the same as the doping type of the source and drain; annealing is performed so that the metal layer doped with the dopant reacts with the surface layer of the source and drain Formation of metal silicides.

Optionally, after the metal layer is formed on the surface of the source and the drain, dopant is doped into the surface of the source and the drain.

Optionally, also include:

After forming a metal layer on the surface of the source electrode and the drain electrode, and before doping dopant into the surface of the source electrode and the drain electrode, forming a protective layer on the metal layer;

After the dopant is doped to the surface of the source and the drain, the protection layer is removed.

Optionally, after the dopant is doped to the surface of the source and the drain, the protective layer is removed before performing the annealing step.

Optionally, the material of the protective layer includes silicon oxide.

Optionally, the method further includes: forming a plug on the source and the drain.

Optionally, the base structure further includes an interlayer dielectric layer covering the transistor, and the method for forming the plug includes:

Before the pre-cleaning, forming a contact hole exposing the source and drain in the interlayer dielectric layer;

After the annealing, a conductive material is filled into the contact hole to form the plug.

Optionally, before the pre-cleaning, sidewalls are formed on the sidewalls of the contact holes.

Optionally, the transistor is a fin field effect transistor.

Optionally, the fin field effect transistor includes a fin, the gate structure is located on the fin, and includes a metal gate and a capping layer on the metal gate, the source, The drain includes a groove in the fin and a semiconductor material filled in the groove.

Optionally, the transistor includes at least one of a PMOS transistor and an NMOS transistor.

Optionally, the dopant is B or P.

Optionally, the pre-cleaning includes physical sputtering and dry etching.

Optionally, Ar is used for the physical sputtering, and the process parameters include: the radio frequency power is 100W-400W.

Optionally, the dry etching is a Siconi pre-cleaning process, and the process parameters include: the flow rate of He is 600SCCM-2000SCCM, the flow rate of _NH3 is 200SCCM-500SCCM, the flow rate of NF3 is _20SCCM -200SCCM, and the air pressure is 2Torr ～10Torr, the time is 5s～100s.

In the technical scheme of the present invention, pre-cleaning is carried out sequentially, and after forming a metal layer for making metal silicide on the surface of the source and the drain, the surface of the source and the drain is then doped with the source and the drain. Doping with the same type of dopant to reduce the contact resistance of the source and drain by reducing the height of the Schottky barrier, followed by annealing to make the metal layer react with the surface layer of the source and drain to generate metal silicide material to further reduce the contact resistance. Since the step of pre-cleaning is carried out before the step of doping the dopant, it can prevent the surface layer containing the dopant of the source electrode and the drain electrode from being removed, and the concentration of the dopant in the source electrode and the drain electrode is reduced, thereby The loss of the dopant in the surface layer of the source electrode and the drain electrode is avoided, and the further reduction of the contact resistance of the source electrode and the drain electrode is effectively realized.

Other features, aspects, and advantages of the present invention will become apparent through the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which constitute a part of this specification, describe exemplary embodiments of the invention and together with the description serve to explain the principles of the invention, in the accompanying drawings:

Fig. 1 is the fabrication flowchart of semiconductor device in one embodiment of the present invention;

2 to 10 are cross-sectional views of a semiconductor device in various manufacturing stages in an embodiment of the present invention.

Detailed ways

As mentioned above, with the further shrinking of the integrated circuit process node, reducing the contact resistance only through metal silicide can no longer meet the requirements of the device. How to further reduce the contact resistance of the source and drain has become an urgent problem to be solved in the industry. technical problem.

A research plan for the above-mentioned problem is: after forming the source and drain of the transistor, implant dopants on the surface of the source and drain, the type of the dopant is different from the doping type of the source and drain. The same; then, cleaning; then, forming a metal layer on the surface of the transistor, followed by annealing to form metal silicide on the surface of the source and drain; finally, forming a contact with it above the source and drain plug.

Theoretically, the dopant on the surface of the source and the drain can reduce the Schottky barrier height (Schottky Barrier Height, referred to as SBH), thereby reducing the contact resistance of the source and the drain. However, the actual test of the semiconductor device formed by the above solution found that the problem of high contact resistance of the source and drain of the transistor has not been improved.

For this reason, the present invention has carried out a lot of research and analysis, and found that the cause of the above problems may be the sidewall morphology of the plug, the depth of the plug, the doping concentration of the dopant, and the like. However, after verifying these reasons one by one, it is found that even if the influence of these reasons is excluded, the source and drain of the transistor still have the problem of high contact resistance. In view of this, the present invention has carried out further in-depth research, and found that, when cleaning before the source electrode and the drain electrode are formed to be used to make the metal layer of metal silicide, not only can remove the The surface layer of the substance reduces the thickness of the region containing the dopant in the source and drain. In addition, the dopant in the source and drain will be lost to reduce its concentration, resulting in the source, drain The loss of the dopant in the drain leads to a relatively large contact resistance between the source and the drain.

In view of this, the present invention proposes an improved method, which performs pre-cleaning successively, forms a metal layer for making metal silicide on the surfaces of the source and drain electrodes, and then dopes the surface of the source electrodes and the drain electrodes with The doping type of the source and the drain is the same to reduce the contact resistance of the source and the drain by reducing the height of the Schottky barrier, followed by annealing to make the metal layer and the source and the drain The surface layer reacts to form metal silicide to further reduce the contact resistance. Since the step of pre-cleaning is carried out before the step of doping the dopant, it can prevent the surface layer containing the dopant of the source electrode and the drain electrode from being removed, and the concentration of the dopant in the source electrode and the drain electrode is reduced, thereby The loss of the dopant in the surface layer of the source electrode and the drain electrode is avoided, and the further reduction of the contact resistance of the source electrode and the drain electrode is effectively realized.

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments should not be construed as limiting the scope of the present invention unless specifically stated otherwise.

In addition, it should be understood that, for the convenience of description, the dimensions of the various components shown in the drawings are not necessarily drawn according to the actual scale relationship, for example, the thickness or width of some layers may be exaggerated relative to other layers.

The following description of the exemplary embodiments is illustrative only and is not intended to limit the invention and its application or use in any way.

Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where applicable, these techniques, methods and devices should be considered a part of this description.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined or described in one figure, it will not need to be further described in the description of subsequent figures. discuss.

The manufacturing method of the semiconductor device of this embodiment will be described in detail below with reference to FIG. 1 to FIG. 10 .

First, referring to FIG. 2, step S1 in FIG. 1 is executed to provide a base structure S, the base structure S includes a transistor, and the transistor includes a gate structure and a source and a drain located on both sides of the gate structure, the The source and drain are doped source and drain.

In this embodiment, the base structure S includes a semiconductor substrate 1 and transistors 2 and 3 on the semiconductor substrate 1, wherein the transistor 2 is an NMOS transistor and is located in the NMOS region of the semiconductor substrate 1, and the source of the transistor 2 The doping type of S1 and the drain D1 is N type, the transistor 3 is a PMOS transistor, and is located in the PMOS region of the semiconductor substrate 1 , the doping type of the source S2 and the drain D2 of the transistor 3 is P type.

The semiconductor substrate 1 can be a single crystal silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, a silicon germanium substrate, a silicon carbon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, III- Substrates such as group V compound substrates (such as gallium nitride substrates or gallium arsenide substrates, etc.).

The transistor 2 is a FinFET and includes a fin 20 , a gate structure G1 on the fin 20 , and a source S1 and a drain D1 on both sides of the gate structure G1 . Further, the gate structure G1 includes a metal gate 21, a capping layer 22 on the metal gate 21, and sidewalls (not marked) covering the metal gate 21 and the capping layer 22. The sidewalls may be Single or multi-layer. The metal gate 21 can be a single layer of metal or a metal stack, and the function of the capping layer 22 includes protecting the underlying metal gate 21 from being etched in the subsequent step S2 (will be described in detail in step S2 ). Both the source S1 and the drain D1 include a groove (not marked) located in the fin 20 and a semiconductor material filled in the groove, and the semiconductor material can be filled in the groove by epitaxial growth . In a specific embodiment, SiC is selected as the semiconductor material to apply stress to the channel of the NMOS transistor so as to improve the carrier mobility of the transistor. Further, the source S1 and the drain D1 are set as raised source/drain (ie, the top of the raised source/drain exceeds the surface of the fin 20 ), so as to improve the performance of the NMOS transistor.

The transistor 3 is a FinFET, and includes a fin 30 , a gate structure G2 on the fin 30 , and a source S2 and a drain D2 on both sides of the gate structure G2 . Further, the gate structure G2 includes a metal gate 31, a capping layer 32 on the metal gate 31, and sidewalls (not marked) covering the metal gate 31 and the capping layer 32. The sidewalls may be Single or multi-layer. The metal gate 31 may be a single layer of metal or a metal stack, and the function of the capping layer 32 includes protecting the underlying metal gate 31 from being etched in the subsequent step S2 (will be described in detail in step S2 ). Both the source S2 and the drain D2 include a groove (not marked) located in the fin 30 and a semiconductor material filled in the groove. The groove can be arranged in a Σ shape or a rectangle, and the semiconductor material can be The groove is filled in the groove by means of epitaxial growth. In a specific embodiment, SiGe is selected as the semiconductor material to apply stress to the channel of the PMOS transistor so as to improve the carrier mobility of the transistor. Further, the source S2 and the drain D2 are also set as raised source/drain (ie, the top of the raised source/drain exceeds the surface of the fin 30 ), so as to improve the performance of the PMOS transistor.

It should be noted that, in the technical solution of the present invention, the type of transistors should not be limited to fin field effect transistors, and it can be applied to any type of transistors, such as MOS transistors. In a modified example of this embodiment, the base structure S may only include PMOS transistors or only NMOS transistors.

In addition to the semiconductor substrate 1 , the transistor 2 and the transistor 3 , the base structure S also includes an interlayer dielectric layer covering the semiconductor substrate 1 , the transistor 2 and the transistor 3 . In this embodiment, the interlayer dielectric layer includes a first dielectric layer 40 , a second dielectric layer 42 located on the first dielectric layer 40 , and a third dielectric layer located on the second dielectric layer 42 A dielectric layer 43, wherein the first dielectric layer 40 and the second dielectric layer 42 fill the gap between the transistor 2 and the transistor 3, and the upper surface of the second dielectric layer 42 is in contact with the gate structure G1 and the gate structure G2 flush with the top.

In a preferred embodiment, the first dielectric layer 40 is made of an insulating material with less hardness to obtain better filling performance. The second dielectric layer 42 is made of an insulating material with higher hardness to better planarize the second dielectric layer 42, so that the surface of the second dielectric layer 42 is compatible with the gate structure G1 and the gate structure G2. surface flush. In this embodiment, the first dielectric layer 40 and the second dielectric layer 42 are made of the same material (such as silicon oxide), but the manufacturing process of the two is different to obtain different hardness. In a modified example of this embodiment, the first dielectric layer 40 and the second dielectric layer 42 may be made of exactly the same material.

The third dielectric layer 43 can be made of the same material as the first dielectric layer 40 and the second dielectric layer 42 , or can be made of a material different from the first dielectric layer 40 and the second dielectric layer 42 . In this embodiment, the third dielectric layer 43 is silicon oxide.

It should be noted that although in the technical solution of this embodiment, the interlayer dielectric layer is a laminated structure (that is, it includes more than two layers of stacked dielectric layers), in other embodiments, the layer The inter-dielectric layer can also be a single-layer structure.

In a preferred embodiment, a contact hole etch barrier layer 41 is formed between the first dielectric layer 40 and the second dielectric layer 42, and a part of the contact hole etch barrier layer 41 covers the sidewall and the source S1 , the drain D1, the source S2 and the drain D2. The contact hole etch barrier layer 41 is used to stop the etching in the subsequent step S2. In this embodiment, the contact hole etch stop layer 41 is made of silicon nitride.

Next, referring to FIG. 3 , step S2 in FIG. 1 is executed to form a contact hole in the interlayer dielectric layer.

In this embodiment, the contact hole C1 exposing the source S1 and the drain D1, the contact hole C2 exposing the source S2 and the drain D2 are formed in the interlayer dielectric layer, the contact hole C1, the contact hole C2 At least through the third dielectric layer 43 and the second dielectric layer 42 .

In a specific embodiment, the forming method of the contact hole C1 and the contact hole C2 includes: forming a patterned photoresist layer (not shown) on the third dielectric layer 43; Etching is carried out for the mask until the source S1 , the drain D1 , the source S2 and the drain D2 are exposed, the etching may be dry etching; then, the patterned photoresist layer is removed.

In the process of etching to form the contact holes C1 and C2, there may be large deviations in the position accuracy and shape accuracy of the contact holes C1 and C2, so that the top of the gate structure G1, the gate structure The top of G2 is exposed to the etching environment. Since the top of the gate structure G1 is provided with a capping layer 22 and the top of the gate structure G2 is provided with a capping layer 32, the etching can be stopped at the capping layer 22 and the capping layer 32, Prevent the metal gate 21 under the capping layer 22 and the metal gate 31 under the capping layer 32 from being exposed by etching to contact with the conductive material subsequently filled in the contact hole C1 and the contact hole C2 to form a short circuit.

In a preferred embodiment, the material of the capping layer 22 and the capping layer 32 is silicon nitride, which has better etching resistance in various etching environments, thereby more reliably protecting the metal gate 21, Metal grid 31.

In this embodiment, the contact hole C1 and the contact hole C2 are both stepped holes, and present a shape that is wide at the top and narrow at the bottom. Wherein, a step (not marked) is formed in the contact hole C1 near the top of the gate structure G1 , and a step (not marked) is formed in the contact hole C2 near the top of the gate structure G2 .

Next, referring to FIG. 4 , step S3 in FIG. 1 is executed to form sidewalls 44 on the sidewalls of the contact hole C1 and the contact hole C2 .

As mentioned above, the contact hole C1 has a step (not marked) near the top of the gate structure G1, the contact hole C2 has a step (not marked) near the top of the gate structure G2, and the contact holes C1, The structure of the contact hole C2 at the corner of the step is relatively fragile and prone to defects, which will cause short circuits between the conductive material subsequently filled in the contact holes C1 and C2 and the metal gates 21 and 31 . By forming side walls 44 on the side walls of the contact holes C1 and C2, the steps on the side walls of the contact holes C1 and C2 can be covered, so that the defects at the corners of the steps will not contact the subsequent filling of the contact holes. C1, contacts the conductive material in the hole C2, thus avoiding the problem of short circuit.

In this embodiment, the formation method of the spacer 44 includes: forming the third dielectric layer 43, the sidewall of the contact hole C1, the sidewall of the contact hole C2, the source S1, the drain D1, the source S2, the drain A sidewall material layer is formed on D2; the sidewall material layer is etched back to remove the upper surface of the third dielectric layer 43, the source electrode S1, the drain electrode D1, the source electrode S2, and the drain electrode D2. The layer of side wall material, the remaining layer of side wall material constitutes the side wall 44 .

In this embodiment, the material of the sidewall 44 includes silicon nitride. Of course, the sidewall 44 can also be made of other insulating materials suitable for the sidewall, such as silicon oxynitride.

Next, referring to FIG. 5 , step S4 in FIG. 1 is performed to perform pre-cleaning, and then, at least a metal layer 5 is formed on the surfaces of the source electrode S1, the drain electrode D1, the source electrode S2, and the drain electrode D2. The metal layer 5 is used to form metal silicide.

In order to reduce the contact resistance of the source S1, the drain D1, the source S2, and the drain D2 in the semiconductor device, metal silicides are formed on the surfaces of the source S1, the drain D1, the source S2, and the drain D2. Before forming the metal silicide, the semiconductor device needs to be pre-cleaned.

In this embodiment, the function of the pre-cleaning includes: removing the natural silicon oxide (native oxide) on the surface of the source S1, the drain D1, the source S2, and the drain D2, so as to avoid The contact resistance is high. In the step of pre-cleaning, firstly, physical sputtering is performed, and then dry etching is performed.

In the pre-cleaning step, the reason why physical sputtering and then dry etching is that the cleaning effect of physical sputtering is not good, and if the natural silicon oxide on the surface is to be completely removed, it will be harmful to the semiconductor due to the high removal intensity. Devices (especially source S1, drain D1, source S2, drain D2) cause damage, and dry etching can just make up for the deficiency of physical sputtering, used to remove residual natural silicon oxide, and due to dry The etching time of the contact hole C1 and the contact hole C2 will not be too long so that the sidewalls of the contact holes C1 and C2 are lost too much. In addition, dry etching can also enable the semiconductor device to obtain a relatively flat interface and good interface characteristics.

Further, in this embodiment, Ar is used for the physical sputtering, and the process parameters of the physical sputtering include: the radio frequency power is 100W-400W. When this parameter is used for sputtering, most of the native oxides can be effectively removed without damaging the source S1 , the drain D1 , the source S2 , and the drain D2 . Of course, in other embodiments, the physical sputtering may also use ions generated after ionization of other inert gases.

Further, in this embodiment, the dry etching is a Siconi pre-cleaning process, and the process parameters of the Siconi pre-cleaning process include: the flow rate of He is 600SCCM-2000SCCM, the flow rate of _NH3 is 200SCCM- _500SCCM , NF3 The flow rate is 20SCCM～200SCCM, the air pressure is 2Torr～10Torr, and the time is 5s～100s. The Siconi pre-cleaning process has better etching selectivity to the pre-removed substance on the semiconductor device, reduces the loss of the semiconductor device, and can obtain lower leakage current and more concentrated contact resistance distribution, so that in the subsequent A more uniform metal silicide can be formed during the process.

After pre-cleaning, a metal layer 5 is formed on the upper surface of the third dielectric layer 43, the sidewall of the contact hole C1, the sidewall of the contact hole C2, the source S1, the drain D1, the source S2, and the drain D2. . In this embodiment, the metal layer 5 includes a Ti layer and a TiN layer on the Ti layer. After the metal layer 5 is annealed in the subsequent step S8, it is used to form a metal silicide _TiSix , and the metal silicide _TiSix has a low The Schottky barrier height (SBH) is high, so the contact resistance of the source S1, the drain D1, the source S2, and the drain D2 can be significantly reduced. However, it should be noted that, in the technical solution of the present invention, the material of the metal layer 5 should not be limited thereto, and it can also be Co, Ni, Pt and the like.

Next, with reference to FIG. 6, step S5 in FIG. 1 is performed to form a protection layer 6 on the metal layer 5, the protection layer 6 is used to prevent the metal layer 6 from being oxidized before annealing in the subsequent step S8 to form a metal silicide, and It is used to prevent the metal layer 6 from being polluted (will be described in the subsequent step S6).

After the protective layer 6 fulfills its function, it will be removed. In this embodiment, the protective layer 6 is made of silicon oxide, which is relatively easy to remove, and is not easy to damage the underlying metal layer 5 while being removed. Further, the formation process of the protection layer 6 is atomic layer deposition (ALD).

Next, referring to FIG. 7 , step S6 in FIG. 1 is executed, and doping 230 is added to the surface of source S1 and drain D1 (referring to the surface in contact with metal layer 5 ), in other words, dopant 230 only forms The surface layers of the source S1 and the drain D1 are not formed on the bottom of the source S1 and the drain D1. The type of the dopant 230 is the same as that of the source S1 and the drain D1 , both being N type. The dopant 330 is doped into the surface of the source S2 and the drain D2 (referring to the surface in contact with the metal layer 5 ). At the bottom of source S2 and drain D2. The type of the dopant 330 is the same as that of the source S2 and the drain D2 , both of which are P type. The dopant 230 and the dopant 330 can be used to reduce the height of the Schottky barrier, thereby reducing the contact resistance of the source S1 , the drain D1 , the source S2 and the drain D2 .

In this embodiment, forming the dopant 230 and the dopant 330 by means of ion implantation specifically includes: forming a first patterned photoresist layer (not shown) on the protection layer 6, the first The patterned photoresist layer exposes the source electrode S1 and the drain electrode D1, but covers the source electrode S2 and the drain electrode D2; the first ion implantation is performed to implant the dopant 230 into the source electrode S1, the drain electrode D1 and the source electrode S1. At the interface of the metal layer 5; remove the first patterned photoresist layer; form a second patterned photoresist layer (not shown) on the protective layer 6, the second patterned photoresist layer The glue layer exposes the source S2 and the drain D2, but covers the source S1 and the drain D1; perform the second ion implantation to implant the dopant 330 to the interface between the source S2, the drain D2 and the metal layer 5 place. In a modified example of this embodiment, the second patterned photoresist layer may also be sequentially formed first, the second ion implantation is performed, and then the first patterned photoresist layer is sequentially formed, and the second ion implantation is performed. The first ion implantation.

Pollutants will be generated when the first patterned photoresist layer and the second patterned photoresist layer are removed, and the protective layer 6 can prevent the pollutants from adhering to the metal layer 5 below the protective layer 6 , thereby preventing the metal layer 5 from being polluted.

Further, in this embodiment, the dopant 230 is B, and the dopant 330 is P. In a specific embodiment, the process parameters of the first ion implantation include: the implantation energy is 1kev-10kev, the implantation dose is 5.0E14atm/cm ² -1.0E16atm/cm ² , the process parameters of the second ion implantation include: the implantation energy The injection dose is 5.0E14atm/cm ² to 1.0E16atm/cm ² .

In a modified example of this embodiment, the above step S6 may also be performed after the pre-cleaning in the above step S4 and before forming a metal layer on the source and drain electrodes.

Next, referring to FIG. 8 , step S7 in FIG. 1 is executed to remove the protective layer 6 in FIG. 7 . In this embodiment, the protection layer 6 is removed by wet etching, and the etchant used is hydrofluoric acid aqueous solution.

Next, referring to FIG. 9 , step S8 in FIG. 1 is executed to perform annealing, so that the metal layer 5 reacts with the surface layer of the source electrode S1, the surface layer of the drain electrode D1, the surface layer of the source electrode S2, and the surface layer of the drain electrode D2 to generate metal silicide. Object 50. In this embodiment, the metal silicide 50 is TiSi _x .

In this embodiment, the annealing is laser annealing, and the process parameters include: the temperature is 800°C-1000°C.

In a modified example of this embodiment, the above step S8 may be performed first, and then the above step S7 may be performed. Compared with the technical solution of this modified example, the technical solution of this embodiment has the following advantages: the annealing step will densify the protective layer 6, so that not only the protective layer 6 is difficult to remove, but also the lower layer 6 will be removed when the protective layer 6 is removed. The third dielectric layer 43 is much lost, and this problem can be avoided when the annealing step is performed later and the step of removing the protective layer 6 is performed first.

As can be seen from the above analysis, in the technical solution of the present invention, after pre-cleaning is performed sequentially, and a metal layer for making metal silicide is formed on the surface of the source and drain electrodes, then the surface of the source and drain electrodes is doped with The doping type of the source and the drain is the same to reduce the contact resistance of the source and the drain by reducing the height of the Schottky barrier, followed by annealing to make the metal layer and the source and the drain The surface layer reacts to form metal silicide to further reduce the contact resistance. Since the step of pre-cleaning is carried out before the step of doping the dopant, it can prevent the surface layer containing the dopant of the source electrode and the drain electrode from being removed, and the concentration of the dopant in the source electrode and the drain electrode is reduced, thereby The loss of the dopant in the surface layer of the source electrode and the drain electrode is avoided, and the further reduction of the contact resistance of the source electrode and the drain electrode is effectively realized.

Finally, referring to FIG. 10, step S9 in FIG. 1 is executed to fill the contact holes C1 and C2 with conductive material to form plugs C3 and C4, and the plugs C3 and C4 are connected with the source S1 and the drain. The metal silicide 50 on the surface of D1, the source S2, and the drain D2 forms an ohmic contact, which reduces the contact resistance. A base structure is provided, which includes a transistor, the transistor includes a gate structure, and a source and a drain located on both sides of the gate structure

In this embodiment, the conductive material filled in the contact holes C1 and C2 includes W. Of course, the conductive material can also be selected from other materials with lower resistance, such as Cu.

In this embodiment, the method for forming the plugs C3 and C4 includes: forming a conductive material layer covering the third dielectric layer 43 and filling the contact holes C1 and C2; The conductive material layer forms plugs C3 and C4.

So far, the semiconductor device and its manufacturing method according to the embodiment of the present invention have been described in detail. In order to avoid obscuring the idea of the present invention, some details known in the art are not described, and those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description. In addition, various embodiments taught in the disclosure of this specification can be freely combined. It will be appreciated by those skilled in the art that various modifications may be made to the embodiments described above without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. a kind of forming method of semiconductor devices, which is characterized in that including：

There is provided underlying structure, the underlying structure includes transistor, the transistor include gate structure and be located at the grid The source electrode of pole structure both sides, drain electrode；

Carry out prerinse；

After carrying out the prerinse, at least in the source electrode, the forming metal layer on surface of drain electrode；

Dopant, the type of the dopant and the source electrode, the doping type of drain electrode are mixed to the surface of the source electrode, drain electrode It is identical；

It anneals, so as to be mixed with the metal layer of the dopant and generation gold is reacted on the surface layer of the source electrode, drain electrode Belong to silicide.

2. the forming method of semiconductor devices as described in claim 1, which is characterized in that on the source electrode, the surface of drain electrode It is formed after metal layer, dopant is mixed to the surface of the source electrode, drain electrode.

3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that further include：

The source electrode, drain electrode forming metal layer on surface after, to the surface of the source electrode, drain electrode mix dopant before, Protective layer is formed on the metal layer；

After mixing dopant to the surface of the source electrode, drain electrode, the protective layer is removed.

4. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the source electrode, the surface of drain electrode After mixing dopant, before executing described the step of being annealed, the protective layer is removed.

5. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the material of the protective layer includes oxygen SiClx.

6. the forming method of semiconductor devices as described in claim 1, which is characterized in that further include：In the source electrode, drain electrode Upper formation plug.

7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that the underlying structure further includes covering The forming method of the interlayer dielectric layer of the transistor, the plug includes：

Before the prerinse, formed in the interlayer dielectric layer expose the source electrode, drain electrode contact hole；

After the annealing, conductive material is filled into the contact hole to form the plug.

8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that before the prerinse, in institute The side wall for stating contact hole forms side wall.

9. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the transistor is Fin formula field effect transistor.

10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that the fin formula field effect transistor Including fin, the gate structure is located on the fin, and includes the lid on metal gates and the metal gates Cap layers, the source electrode, drain electrode include the groove being located in the fin and the semi-conducting material being filled in the groove.

11. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the transistor packet Include at least one of PMOS transistor, NMOS transistor.

12. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the dopant is B or P.

13. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the prerinse packet It includes：Physical sputtering and dry etching.

14. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the physical sputtering uses Ar, And technological parameter includes：Radio-frequency power is 100W~400W.

15. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the dry etching is Siconi Pre-cleaning processes, and technological parameter includes：The flow of He is 600SCCM~2000SCCM, NH₃Flow be 200SCCM~ 500SCCM, NF₃Flow be 20SCCM~200SCCM, air pressure be 2Torr~10Torr, the time be 5s~100s.