CN108807373A - electrostatic protection device - Google Patents

Abstract

The invention provides an electrostatic protection device, comprising a substrate, a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first P+ injection region, a first N-base are arranged in the P well Injection layer and the first N+ injection region, the N well is provided with the second N-base injection layer, the second N+ injection region and the second P+ injection region; the first P+ injection region, the first N+ injection region are connected to the cathode; the second The second N+ implantation region and the second P+ implantation region are connected to the anode; a first thin gate oxide layer is provided between the first P+ implantation region and the first N+ implantation region, and the first thin gate oxide layer is covered with the first polysilicon gate, a second thin gate oxide layer is provided between the second N+ implant region and the second P+ implant region, and the second thin gate oxide layer is covered with a second polysilicon gate; the second N-base implant layer is connected across the Between the P well and the N well, the first N-base injection layer is located below the first N+ injection region. The invention can solve the problems of high trigger voltage and weak anti-total dose ability.

Description

ESD protection device

technical field

The invention relates to the technical field of electrostatic protection for integrated circuits, in particular to an electrostatic protection device.

Background technique

LDMOS (Laterally Diffused Metal Oxide Semiconductor, Laterally Diffused Metal Oxide Semiconductor) devices are widely used in power management chips, such as DC-DC converters, AC-DC converters, and the like. With the development of integrated circuits in the direction of high speed and high voltage, the weak electrostatic protection ability of LDMOS devices has become a bottleneck restricting its development. Therefore, how to improve the electrostatic protection capability (Electro-Static discharge, ESD) of the LDMOS device has become a research hotspot.

Please refer to Figure 3 and Figure 4. In traditional LDMOS electrostatic protection devices, diodes or silicon controlled rectifiers (Silicon Controlled Rectifier, SCR) are usually used to enhance their electrostatic discharge capabilities, but both solutions are It has the disadvantages of high trigger voltage and weak anti-total dose ability, which limits the application range of electrostatic protection devices, especially in aerospace high-voltage integrated circuits.

Contents of the invention

In view of the above situation, it is necessary to provide an electrostatic protection device to solve the problems of high trigger voltage and weak anti-total dose capability.

An electrostatic protection device, comprising a substrate, a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first P+ injection region, a first An N-base injection layer and a first N+ injection region, the N well is provided with a second N-base injection layer, a second N+ injection region and a second P+ injection region; the first P+ injection region, the first N+ injection region An N+ implanted region is connected to the cathode; the second N+ implanted region and the second P+ implanted region are connected to the anode; a first thin gate is provided between the first P+ implanted region and the first N+ implanted region An oxide layer, the first thin gate oxide layer is covered with a first polysilicon gate, a second thin gate oxide layer is provided between the second N+ implantation region and the second P+ implantation region, and the first thin gate oxide layer is The second thin gate oxide layer is covered with a second polysilicon gate; the second N-base injection layer is connected between the P well and the N well, and the first N-base injection layer is located at the Below the first N+ implantation region.

According to the above electrostatic protection device, between the first P+ implantation region and the first N+ implantation region, and between the second N+ implantation region and the second P+ implantation region, the polysilicon gate structure is used to replace the thick field oxygen layer for isolation, which can Effectively improve the anti-total dose performance of the device. The second N-base injection layer is connected between the P well and the N well, which has the effect of reducing the trigger voltage and improving the anti-total dose performance. In addition, the first N-base injection layer is located at Below the first N+ injection region, the magnification of the NPN tube near the cathode can be enlarged, and the maintenance voltage can be increased at the same time, so that the electrostatic protection device has the advantages of low trigger voltage, high discharge efficiency, and strong anti-total dose ability, which can be applied to Electrostatic protection for high-voltage integrated circuits used in aerospace.

In addition, the electrostatic protection device proposed by the present invention can also have the following additional technical features:

Further, a third thin gate oxide layer and a field oxygen region are sequentially arranged between the first N+ implantation region and the second N+ implantation region, and the third thin gate oxide layer is covered with a third polysilicon gate, and the third polysilicon gate is connected to the cathode.

Further, the second N-base injection layer surrounds the field oxygen region.

Further, the second P+ implantation region, the N well, and the P well constitute a PNP structure, and the first N+ implantation region, the P well, and the second N-base implantation layer constitute an NPN structure.

Further, the P well and the N well are arranged in sequence from left to right in the deep N well, and the first P+ implantation region, the first N-base implant layer and the first N+ implant region, the N well is provided with the second N-base implant layer, the second N+ implant region and the second P+ implant in sequence from left to right Area.

Further, from the anode to the cathode, the electrostatic protection device has three electrostatic discharge paths, the first path being the second P+ injection region, the N well, the P well, and the first P+ injection region ; The second path is the second N+ implantation region, the N well, the P well, and the first N+ implantation region; the third path is the second N+ implantation region, the second N+ implantation region - a base injection layer, the P well, and the first N+ injection region.

Further, the substrate is a P-type silicon substrate.

Description of drawings

Fig. 1 is a schematic structural view of an electrostatic protection device provided by an embodiment of the present invention;

Fig. 2 is the equivalent circuit diagram of Fig. 1;

3 is a schematic structural view of an LDMOS electrostatic protection device in the prior art;

FIG. 4 is a schematic structural diagram of an electrostatic protection device with an LDMOS-SCR structure in the prior art.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. Several embodiments of the invention are shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

It should be noted that when an element is referred to as being “fixed on” another element, it may be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "upper," "lower," and similar expressions are for descriptive purposes only and do not indicate or imply the device or Elements must have certain orientations, be constructed and operate in certain orientations, and therefore should not be construed as limitations on the invention.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to FIG. 1 and FIG. 2 , an electrostatic protection device provided by an embodiment of the present invention includes a substrate 100 , specifically, in this embodiment, the substrate 100 is a P-type silicon substrate.

A deep N well 200 is arranged on the substrate 100, and a P well 300 and an N well 301 are arranged in the deep N well 200. Specifically, in this embodiment, the P well 300 and the N well 301 are sequentially arranged in the deep N well 200 from left to right.

The P well 300 is provided with a first P+ implantation region 401 , a first N-base implantation layer 402 and a first N+ implantation region 403 . Specifically, in this embodiment, the first P+ implantation region 401 , the first N-base implantation layer 402 and the first N+ implantation region 403 are sequentially arranged in the P well 300 from left to right.

The N well 301 is provided with a second N-base injection layer 404 , a second N+ injection region 405 and a second P+ injection region 406 . Specifically, in this embodiment, the second N-base injection layer 404 , the second N+ injection region 405 and the second P+ injection region 406 are sequentially arranged in the first N well 301 from left to right.

The first P+ implantation region 401 and the first N+ implantation region 403 are connected to the cathode; the second N+ implantation region 405 and the second P+ implantation region 406 are connected to the anode.

Specifically, the second N-base injection layer 404 is connected between the P well 300 and the N well 301, and the first N-base injection layer 402 is located in the first N+ injection region 403 below.

A first thin gate oxide layer 501 is provided between the first P+ implant region 401 and the first N+ implant region 403, and the first thin gate oxide layer 501 is covered with a first polysilicon gate 502, so A second thin gate oxide layer 503 is disposed between the second N+ implant region 405 and the second P+ implant region 406 , and the second thin gate oxide layer 503 is covered with a second polysilicon gate 504 .

The second P+ implantation region 406, the N well 301, and the P well 300 form a PNP structure, that is, a triode Qp; the first N+ implantation region 403, the P well 300, and the second N-base The injection layer 404 constitutes an NPN structure, that is, a transistor Qn.

Among them, Rpw is p well resistance, Rnw is n well resistance.

In this embodiment, a third thin gate oxide layer 505 and a field oxide region 506 are sequentially provided between the first N+ implantation region 403 and the second N+ implantation region 405, and on the third thin gate oxide layer 505 Covered with a third polysilicon gate 507, the third polysilicon gate 507 is connected to the cathode. The second N-base injection layer 404 surrounds the field oxygen region 506 .

From the anode to the cathode, the electrostatic protection device has three electrostatic discharge paths, the first path being the second P+ injection region 406, the N well 301, the P well 300, and the first P+ injection region 401; the second path is the second N+ implantation region 405, the N well 301, the P well 300, and the first N+ implantation region 403; the third path is the second N+ implantation region 405 , the second N-base injection layer 404 , the P well 300 , and the first N+ injection region 403 , so they have strong electrostatic discharge capability and high discharge efficiency.

According to the electrostatic protection device provided in this embodiment, between the first P+ implantation region and the first N+ implantation region, and between the second N+ implantation region and the second P+ implantation region, a polysilicon gate structure is used instead of a thick field oxygen layer. Isolation can effectively improve the anti-total dose performance of the device. The second N-base injection layer is connected between the P well and the N well, which can reduce the trigger voltage and improve the anti-total dose performance. In addition, the first N-base The injection layer is located below the first N+ injection region, which can expand the magnification of the NPN tube near the cathode, and at the same time increase the maintenance voltage, so that the electrostatic protection device has the advantages of low trigger voltage, high discharge efficiency, and strong total dose resistance. It can be applied to the electrostatic protection of high-voltage integrated circuits used in aerospace.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (7)

1. An electrostatic protection device, characterized in that, comprises a substrate, the substrate is provided with a deep N well, the deep N well is provided with a P well and an N well, and the P well is provided with a first P+ injection region, the first N-base injection layer and the first N+ injection region, the second N-base injection layer, the second N+ injection region and the second P+ injection region are arranged in the N well; the first P+ The implanted region, the first N+ implanted region is connected to the cathode; the second N+ implanted region, the second P+ implanted region is connected to the anode; between the first P+ implanted region and the first N+ implanted region A first thin gate oxide layer is provided, the first thin gate oxide layer is covered with a first polysilicon gate, and a second thin gate is provided between the second N+ implantation region and the second P+ implantation region An oxide layer, the second thin gate oxide layer is covered with a second polysilicon gate; the second N-base injection layer is connected between the P well and the N well, and the first N - the base injection layer is located below the first N+ injection region. 2. The electrostatic protection device according to claim 1, wherein a third thin gate oxide layer and a field oxygen region are sequentially provided between the first N+ implanted region and the second N+ implanted region, and the The third thin gate oxide layer is covered with a third polysilicon gate, and the third polysilicon gate is connected with the cathode. 3. The electrostatic protection device according to claim 2, wherein the second N-base injection layer surrounds the field oxygen region. 4. The electrostatic protection device according to claim 1, wherein the second P+ injection region, the N well, and the P well form a PNP structure, and the first N+ injection region, the P well . The second N-base injection layer constitutes an NPN structure. 5. The electrostatic protection device according to claim 1, characterized in that, the P well and the N well are sequentially arranged in the deep N well from left to right, and the P well is sequentially arranged from left to right The first P+ injection region, the first N-base injection layer, and the first N+ injection region are provided, and the N well is sequentially provided with the second N-base injection layer, The second N+ implantation region and the second P+ implantation region. 6. The electrostatic protection device according to claim 1, characterized in that, from the anode to the cathode, the electrostatic protection device has three electrostatic discharge paths, the first path being the second P+ injection region, the N well, the P well, the first P+ implantation region; the second path is the second N+ implantation region, the N well, the P well, and the first N+ implantation region; the third path These are the second N+ implantation region, the second N-base implantation layer, the P well, and the first N+ implantation region. 7. The electrostatic protection device according to claim 1, wherein the substrate is a P-type silicon substrate.