CN108831834A - Method for forming power semiconductor device - Google Patents

Abstract

A kind of forming method of power semiconductor, including：The semiconductor layer of first kind doping is provided；The Patterned masking layer with opening is formed in the semiconductor layer surface；Using diffusion technique to ion doping is carried out in the semiconductor layer below the opening, Carriers Absorption area is formed, the Doped ions that the diffusion technique uses can form energy level defect in the Carriers Absorption area.The forming method of the power semiconductor is formed by power semiconductor anti-SEGR ability with higher.

Description

Method for forming power semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a power semiconductor device.

Background technique

One of the core components of vertical conductive double-diffused MOS structure (VDMOS) device power integrated circuits and power integrated systems. The gate and source of VDMOS are on the upper surface of the substrate, while the drain is on the lower surface of the substrate. The source and drain are on the opposite plane of the substrate. When the current flows from the drain to the source, the current flows vertically inside the silicon chip, so the area of the silicon chip can be fully utilized to improve the ability to pass current.

Power VDMOS devices have the advantages of both bipolar transistors and MOS transistors, fast switching speed, high input impedance, low driving power consumption, negative temperature coefficient, no secondary breakdown, and are widely used in aviation, aerospace, nuclear energy and other fields . However, in the space radiation environment, power VDMOS devices are vulnerable to various rays and charged particles, especially heavy ions-induced single event burnout (SEB) and single event gate penetration (SEGR), resulting in device damage.

How to improve the anti-SEGR ability of the device is an urgent problem to be solved at present.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for forming a power semiconductor device, which can improve the single event burnout effect (SEB) and single event gate wear-through effect (SEGR) of the device.

In order to solve the above problems, the present invention provides a method for forming a power semiconductor device, comprising: providing a first-type doped semiconductor layer; forming a patterned mask layer with openings on the surface of the semiconductor layer; using a diffusion process to Ion doping is performed in the semiconductor layer below the opening to form a carrier absorption region, and the dopant ions used in the diffusion process can form energy level defects in the carrier absorption region.

Optionally, the dopant ions used in the diffusion process include heavy metal ions.

Optionally, the dopant ions used in the diffusion process include at least one of Pt, Au, Cu or Pd.

Optionally, the doping concentration of the heavy metal ions in the carrier absorption region is 5e13cm ^-3 -5e15cm ^-3 .

Optionally, before performing ion doping in the semiconductor layer below the opening by a diffusion process, further comprising performing ion implantation on the semiconductor layer along the opening to form implantation defects in the semiconductor layer below the opening .

Optionally, the implanted ion used in the ion implantation is at least one of H or He.

Optionally, the implantation energy used in the ion implantation is 0.1MeV-5MeV, and the implantation dose is 1e11cm ^-2 -1e14cm ^-2 .

Optionally, the surface of the carrier absorption region is coplanar with the surface of the semiconductor layer.

Optionally, the carrier absorption region includes a plurality of discrete carrier absorption regions.

Optionally, the distance between adjacent sub-absorbing regions is less than 2 μm.

Optionally, it also includes: after removing the patterned mask layer, forming a gate structure on the surface of the semiconductor layer, the gate structure is located above the carrier absorption region; A body region doped with the second type is formed in the semiconductor layer on the side.

Optionally, the minimum distance between the edge of the carrier absorption region and the body region is greater than 0 and less than or equal to 2 μm.

Optionally, the doping depth of the carrier absorption region is less than or equal to the doping depth of the body region.

In the method for forming a power semiconductor device of the present invention, a carrier absorption region with energy level defects is formed in the semiconductor layer through a diffusion process, which can absorb excess carriers generated by heavy ions between device body regions, thereby Improve the anti-SEGR ability of power semiconductor devices.

Description of drawings

1 to 5 are structural schematic diagrams of the formation process of a semiconductor device according to a specific embodiment of the present invention.

Detailed ways

The specific implementation of the method for forming a power semiconductor device provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1 to FIG. 5 , which are schematic structural diagrams of the forming process of a power semiconductor device according to a specific embodiment of the present invention.

Referring to FIG. 1 , a semiconductor layer 100 doped with a first type is provided.

The semiconductor layer 100 may be a first-type doped single crystal silicon substrate, or may include a substrate and a first-type doped epitaxial layer located on the surface of the substrate, or, the semiconductor layer 100 may also be A plurality of stacked first type doped epitaxial layers is included. The material of the semiconductor layer may be semiconductor materials such as silicon, germanium or silicon germanium. Those skilled in the art can select the semiconductor layer 100 with a suitable structure, material and doping concentration according to the performance requirements of the power semiconductor device.

In this specific implementation, the first type of doping is N-type doping, and the second type of doping is P-type doping; in other specific implementations, the first type of doping can also be P type doping, the second type doping is N type doping. The N-type doping ions may be at least one of P, As or Td, and the P-type doping ions may be at least one of B, In or Ga.

In this specific embodiment, the semiconductor layer 100 includes an N-type heavily doped substrate, and an N-type lightly doped epitaxial layer located on the surface of the substrate.

Referring to FIG. 2 , a patterned mask layer 200 having openings 201 is formed on the surface of the semiconductor layer 100 .

The patterned mask layer 200 is a hard mask layer. The method for forming the patterned mask layer 200 includes: after forming a mask material layer on the surface of the semiconductor substrate 100 by a deposition or growth process, forming a patterned photoresist layer 202 on the surface of the mask material layer, The patterned photoresist layer 202 exposes part of the surface of the mask material layer, and the patterned photoresist layer 202 is used as a mask to etch the mask material layer to form a patterned mask with an opening 201 Layer 200.

The patterned mask layer 200 can be a single-layer or multi-layer structure, and the material of the patterned mask layer 200 includes one or more of hard mask materials such as silicon dioxide, silicon nitride, and silicon carbide. . The patterned mask layer 200 adopts a hard mask material, which has a strong diffusion barrier capability.

Referring to FIG. 3 , the semiconductor layer 100 below the opening 201 is ion-doped by a diffusion process to form a carrier absorption region 300 .

In this specific implementation manner, before performing the diffusion process, the patterned photoresist layer 202 is removed first. Since the diffusion process is performed at high temperature, removing the patterned photoresist layer 202 can prevent the patterned photoresist layer 202 from polluting the surface of the semiconductor layer 100 .

The dopant ions used in the diffusion process can form deep-level impurities in the carrier absorption region. In a specific embodiment, the dopant ions are heavy metal ions, for example including at least one of heavy metal ions such as Pt, Au, Cu or Pd. The doping of heavy metal ions will be a deep-level impurity in the carrier absorption region 104 , which can act as a recombination center to absorb excess carriers generated by heavy ions. At the same time, heavy metal impurities are deep-level defects, which will not significantly affect device doping and device performance.

The doping concentration of the heavy metal ions may be 5e13cm ^-3 -5e15cm ^-3 . Those skilled in the art can reasonably adjust the doping concentration of heavy metal ions based on the doping concentration range and according to the withstand voltage requirements of the device.

In a specific embodiment, the dopant ion used in the diffusion process is Pt, which is spin-coated on the surface of the semiconductor layer 100 and the patterned mask layer 200 by using a liquid source, and the diffusion temperature range is 550°C-850°C. , the diffusion time ranges from 20 min to 40 min, and a carrier absorption region 300 with a certain diffusion depth and doping concentration is formed in the semiconductor layer 100 . In other specific implementation manners, a heavy metal alloy may also be formed on the surface of the semiconductor layer 100 below the opening 201 , and then advanced at a high temperature, so that the heavy metal ions diffuse into the semiconductor layer 100 .

In other specific implementation manners, the diffusion process may also use other dopant ions capable of generating deep level defects in the semiconductor layer 100 , which is not limited here.

Parameters such as diffusion temperature and diffusion time of the diffusion process can be adjusted, and parameters such as doping concentration and depth of the carrier absorption region 300 can be adjusted to meet the requirements of actual devices.

In another specific embodiment of the present invention, before performing the diffusion process, further comprising performing ion implantation on the semiconductor layer 100 along the opening 201, forming implant defects in the semiconductor layer 100 below the opening, Then, a diffusion process is performed, and ion doping is performed in the semiconductor layer 100 where implanted defects have been formed to form a carrier absorption region.

Specifically, the implanted ions used in the ion implantation are at least one of H or He, and are used to form implanted defects in the semiconductor layer. The ion implantation is carried out at room temperature, the implantation energy can be 0.1MeV˜5 MeV, and the implantation agent can be 1e11cm ⁻² ˜1e14cm ⁻² .

The implantation defects formed in the semiconductor layer 100 are more conducive to the subsequent ion doping through the diffusion process, and under the same doping conditions, the implantation defects are formed before the diffusion process, which can effectively improve the doping in the carrier absorption region. The concentration of ions is increased, and the number of defect energy levels is increased, thereby further improving the carrier absorption capacity of the carrier absorption region.

In a specific implementation manner, after the patterned mask layer 200 having the opening 201 is formed, the semiconductor layer 100 is implanted with He ions along the opening 201, the implantation energy is 3.3 MeV, and the implantation dose is 1e13cm ⁻² ; After the implantation is completed, a diffusion process is performed to diffuse Pt into the semiconductor layer 100 below the opening 201 at a temperature of 700° C. for 30 minutes.

The surface of the carrier absorption region 300 is coplanar with the surface of the semiconductor layer 100, and is formed by diffusion from the surface of the semiconductor layer 100 into the semiconductor layer 100, so that the carrier absorption region 300 and the subsequently formed gate The distance between the dielectric layers is the closest, which can minimize the influence of electron-holes generated after the heavy ions bombard the device on the gate dielectric layer.

In this specific embodiment, the opening 201 exposes part of the continuous surface of the semiconductor layer 100 , therefore, the formed carrier absorption region 300 is a complete and continuous doped region. In other specific implementation manners, the opening 201 may further include a plurality of discrete sub-openings 301 , so that the finally formed carrier absorption region 300 includes a plurality of discrete sub-absorption regions. In order to improve the ability of each sub-absorption region to absorb carriers, the distance between adjacent sub-absorption regions is less than 2 μm.

Please refer to FIG. 4, after removing the patterned mask layer 200, a gate structure is formed on the surface of the semiconductor layer 100, the gate structure is located above the carrier absorption region 300; Body regions 403 doped with the second type are formed in the semiconductor layer 100 on both sides.

The gate structure includes a gate 402 and a gate dielectric layer 401 between the gate 402 and the semiconductor layer 100 . The material of the gate 402 may be polysilicon or other suitable gate materials, and the material of the gate dielectric layer 401 may be dielectric materials such as silicon oxide, hafnium oxide, and zirconium oxide.

In this specific embodiment, the material of the gate 402 is polysilicon, the material of the gate dielectric layer 401 is silicon oxide, and the method for forming the gate structure includes: adopting a thermal oxidation process, forming A silicon oxide layer is formed, and then a polysilicon layer is deposited on the surface of the gate dielectric material layer; the polysilicon layer and the silicon oxide layer are etched to form gate 402 and gate dielectric layer 401 respectively.

The gate structure is located above the carrier absorption region 300, and the gate structure completely covers the area where the carrier absorption region 300 is located, so that the carrier absorption region 300 is completely located on the gate In the semiconductor layer 100 below the structure.

Body regions 403 of the second doping type are formed in the semiconductor layer 100 on both sides of the gate structure by diffusion or ion implantation process. By controlling the size and position of the gate structure and the carrier absorption region 300 , the distance between the carrier absorption region 300 and the body region 403 can be adjusted.

In a specific embodiment, the minimum distance between the edge of the carrier absorption region 300 and the body region 403 is greater than 0 and less than or equal to 2 μm. The carrier absorption region 300 is mainly used to absorb excess carriers in the neck of the semiconductor layer 100 between the body regions 403, so the closer the carrier absorption region 300 is to the body region 101, the better the absorption effect. it is good. If the distance is too long, the absorption effect will be poor. Since the carrier absorption region 300 is formed in the neck region, in order to meet the requirements of breakdown voltage and on-resistance, the width of the neck region can be adjusted accordingly by adjusting the width of the gate structure. The region width is the distance between two body regions 403 .

The carrier absorption region 300 mainly absorbs excess carriers through the edge, so the edge source morphology of the carrier absorption region 300 has an impact on the carrier absorption, especially the part adjacent to the body region 403 edge. According to the requirements on parameters such as on-resistance and breakdown voltage of the device, the shape of the carrier absorption region 300 can be adjusted by adjusting the shape of the opening 201 . The edge near the body region 403 can be arc-shaped, perpendicular to the surface of the semiconductor layer 100 or other shapes.

In a specific embodiment of the present invention, the doping depth of the carrier absorption region 104 is less than or equal to the doping depth of the body region 101, so as to avoid reducing the breakdown voltage of the device; in other specific embodiments, If the requirement for the breakdown voltage of the device is not high, the doping depth of the carrier absorption region 104 may also be slightly greater than the doping depth of the body region 101 .

Please refer to FIG. 5 , a first type doped source region 501 is formed in the body region 101 on both sides of the gate structure; a capping layer 502 covering the top and sidewalls of the gate structure is formed; A source 503 is formed on the surface of the layer 502 , the body region 403 and the source region 501 ; a drain 504 is formed on the other surface of the semiconductor layer 100 opposite to the gate structure.

Implanting first type dopant ions into the body region 403 to form the source region 501 . In this specific implementation manner, the source region 501 is N-type doped.

The material of the capping layer 502 may be a dielectric material such as silicon oxide or silicon nitride, which is used to protect the gate structure. The method for forming the capping layer 502 includes: depositing a capping material layer on the surface of the semiconductor layer 100 and the gate structure, patterning the capping material layer, and forming a cap covering the top and sidewalls of the gate structure Layer 502.

The source electrode 503 is a metal layer, and the source electrode 503 is formed by depositing a metal material on the surface of the cap layer 502 and the semiconductor layer 100 and patterning and alloying the metal material.

It also includes, after forming the source electrode 503 , depositing a metal layer on the back of the semiconductor layer 100 to form the drain electrode 504 . In order to reduce the thickness of the power semiconductor device, before forming the drain 504 , it also includes thinning the back of the semiconductor layer 100 , and then forming the drain 504 on the thinned surface.

In the method for forming a power semiconductor device according to a specific embodiment of the present invention, a carrier absorption region with energy level defects is formed in the semiconductor layer between the body regions through a diffusion process, and the carrier absorption region can affect the device body. The excess carriers generated by heavy ions between the regions are absorbed, thereby improving the SEGR resistance of power semiconductor devices.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Be the protection scope of the present invention.

Claims (13)

1. A method for forming a power semiconductor device, comprising: providing a first type doped semiconductor layer; forming a patterned mask layer with openings on the surface of the semiconductor layer; Ion doping is performed on the semiconductor layer below the opening by a diffusion process to form a carrier absorption region, and the dopant ions used in the diffusion process can form energy level defects in the carrier absorption region. 2 . The method for forming a power semiconductor device according to claim 1 , wherein the dopant ions used in the diffusion process include heavy metal ions. 3 . 3 . The method for forming a power semiconductor device according to claim 1 , wherein the dopant ions used in the diffusion process include at least one of Pt, Au, Cu or Pd. 4 . The method for forming a power semiconductor device according to claim 2 , wherein the doping concentration of the heavy metal ions in the carrier absorption region is 5e13cm ^-3 -5e15cm ^-3 . 5 . The method for forming a power semiconductor device according to claim 1 , further comprising: doping the semiconductor layer along the opening before performing ion doping on the semiconductor layer below the opening by using a diffusion process. 6 . The layer is ion-implanted to form implanted defects in the semiconductor layer below the opening. 6 . The method for forming a power semiconductor device according to claim 5 , wherein the ion implantation used in the ion implantation is at least one of H or He. 7 . The method for forming a power semiconductor device according to claim 6 , wherein the implantation energy used in the ion implantation is 0.1MeV˜5 MeV, and the implantation dose is 1e11cm ⁻² ˜1e14cm ⁻² . 8 . The method for forming a power semiconductor device according to claim 1 , wherein the surface of the carrier absorption region is coplanar with the surface of the semiconductor layer. 9. The method for forming a power semiconductor device according to claim 1, wherein the carrier absorption region comprises a plurality of discrete sub-absorption regions. 10 . The method for forming a power semiconductor device according to claim 9 , wherein the distance between adjacent sub-absorption regions is less than 2 μm. 11 . 11. The method for forming a power semiconductor device according to claim 1, further comprising: after removing the patterned mask layer, forming a gate structure on the surface of the semiconductor layer, the gate structure is located at Above the carrier absorption region; a second type doped body region is formed in the semiconductor layer on both sides of the gate structure. 12 . The method for forming a power semiconductor device according to claim 11 , wherein the minimum distance between the edge of the carrier absorption region and the body region is greater than 0 and less than or equal to 2 μm. 13 . 13 . The method for forming a power semiconductor device according to claim 11 , wherein the doping depth of the carrier absorption region is less than or equal to the doping depth of the body region. 14 .