CN108874011B - A gate modulation circuit of LDMOS solid-state power amplifier - Google Patents

Abstract

The invention discloses a gate modulation circuit of an LDMOS solid-state power amplifier, which comprises an adjustable regulated power supply, a buffer, a turn-on circuit and a turn-off circuit; the adjustable regulated power supply is connected to an LDMOS tube through the turn-on circuit, so that the The buffer is connected to the LDMOS tube through the turn-on circuit and the turn-off circuit, the adjustable voltage-stabilized power supply provides a stable output voltage, and the buffer, the turn-on circuit, and the turn-off circuit are connected to the LDMOS transistor. The LDMOS tube connection realizes the state switching and adjustment of the LDMOS solid-state power amplifier; the present invention utilizes an adjustable regulated power supply, a co-direction/reverse buffer, a turn-on circuit, and a turn-off circuit to realize the LDMOS tube gate modulation circuit, The gate voltage amplitude of the LDMOS tube is adjustable, the time of the front and rear edges of the pulse waveform is adjustable, the circuit is simple, the realization is convenient, and the reliability is high.

Description

A gate modulation circuit of LDMOS solid-state power amplifier

technical field

The invention relates to the technical field of microwave solid-state power amplifiers, in particular to a gate modulation circuit of an LDMOS solid-state power amplifier.

Background technique

LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a microwave power device with huge market demand and broad development prospects. Because LDMOS has the advantages of high linearity, high gain, high reliability, etc., it has been widely used in the civilian field. At present, silicon microwave LDMOS has become an important choice for base station power technology. In addition, after the use of LDMOS transistors in broadband frequency modulation transmitters, transmitters of digital terrestrial television systems, and airborne transponders, the overall performance of the system has been greatly improved.

Compared with microwave power bipolar devices, microwave power LDMOS transistors have no secondary breakdown, large safe working area, negative temperature coefficient, high linearity, strong burnout resistance, fast switching speed, simple matching circuit, and driving loss. small features. The application of LDMOS devices in the civilian field has been widely praised. In the military field, LDMOS is also a commonly used power amplifier, which is widely used in radar, electronic countermeasures, satellite communications and other products.

When the LDMOS solid-state amplifier is working, the input signal generally adopts the radio frequency modulation signal, and the power amplifier is modulated at the same time, and the LDMOS tube is controlled to work or cut off by the external TTL signal. The combination of radio frequency modulation and power amplifier modulation can reduce the noise suppression of the power amplifier and improve the efficiency of the amplifier. .

The modulation of LDMOS solid-state amplifiers is generally divided into two ways: gate modulation and drain modulation. The gate modulation voltage is low and the current is small, so the circuit is simple and easy to implement. When the drain is modulated, the current flowing through the modulation switch is large, the drain voltage is high, the switch control circuit is complex, and the rising and falling edges of the pulse signal output are large. Due to the characteristics of LDMOS devices, gate modulation circuits are generally used. In the existing gate modulation circuit, an external TTL modulation pulse is directly applied to the gate of the LDMOS device. When the modulation pulse is at a high level, the LDMOS device is turned on, and when the modulation pulse is at a low level, the LDMOS device is turned off. However, due to the distributed capacitance between the gate and the source of the LDMOS device, discharge time is required when the modulation pulse is at a low level, resulting in a tailing phenomenon in the turn-off of the LDMOS device, and the back edge of the power amplifier modulation pulse output is large, which is difficult to meet the required pulse. Occasions with small delay and small front and rear edges.

In view of the above-mentioned defects, the creator of the present invention finally obtained the present invention after a long period of research and practice.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned technical defects, the technical solution adopted by the present invention is to provide a gate modulation circuit of an LDMOS solid-state power amplifier, including an adjustable voltage-stabilized power supply, a buffer, a turn-on circuit, and a turn-off circuit; The power supply is connected to the LDMOS tube through the turn-on circuit, the buffer is connected to the LDMOS tube through the turn-on circuit and the turn-off circuit, the adjustable voltage-stabilized power supply provides a stable output voltage, and the buffer , the turn-on circuit and the turn-off circuit are connected with the LDMOS transistor to realize state switching and adjustment of the LDMOS solid-state power amplifier.

Preferably, the adjustable regulated power supply includes a first resistor, a potentiometer, a first energy storage capacitor, a second energy storage capacitor, and a voltage stabilizer; the positive end of the first energy storage capacitor is connected to the stabilizer. The first pin, the third pin and the fourth pin of the voltage regulator, the negative end of the first energy storage capacitor is grounded; the positive end of the second energy storage capacitor is connected to the fifth pin of the voltage stabilizer pin, sixth pin, seventh pin, the negative end of the second energy storage capacitor is grounded; the second pin of the voltage stabilizer U1 is grounded; the first resistor is connected in series with the potentiometer, The common terminal of the first resistor and the potentiometer is connected to the eighth pin of the voltage regulator, and one end of the first resistor is connected to the fifth pin and the sixth pin of the voltage regulator. pin and the seventh pin, one end of the potentiometer is grounded.

Preferably, the input end of the buffer is connected to an external TTL modulation signal, the output end of the buffer includes a first output end and a second output end, and the first output end outputs a forward signal and is connected to the One end of the second resistor is connected to one end of the seventh resistor of the shut-off circuit after the second output end outputs the reverse signal, and the phases of the two signals are opposite.

Preferably, the turn-on circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a turn-on tube, a first Zener diode, and a gate capacitor; the third resistor and the The cathode of the first Zener diode is connected in parallel, the cathode of the first Zener diode is connected to one end of the second resistor and then connected to the gate of the turn-on tube, and the anode of the first Zener diode is grounded; the One end of the fourth resistor and the fifth resistor connected in parallel is connected to the source of the turn-on tube, and the other end is grounded; one end of the sixth resistor is connected to the source of the turn-on tube, and the other end is connected to the gate capacitor , the other end of the gate capacitor is grounded.

Preferably, the shutdown circuit further includes an eighth resistor, a ninth resistor, a tenth resistor, a shutdown transistor, a second Zener diode, and a third Zener diode; the eighth resistor and the second Zener diode. The negative electrode of the voltage regulator diode is connected in parallel, the negative electrode of the second voltage regulator diode is connected to one end of the seventh resistor and then connected to the gate of the shutdown tube, and the positive electrode of the second voltage regulator diode is grounded; the ninth voltage regulator diode is connected to the ground; Both ends of the resistor are respectively connected with the drain of the turn-off tube and the source of the turn-on tube, the tenth resistor is connected in parallel with the third zener diode, and the negative electrode of the third zener diode is connected to the The source of the turn-on tube is connected, and the anode of the third Zener diode is grounded.

Preferably, the output voltage of the voltage regulator is adjusted by the potentiometer, and the adjustment range is determined by the voltage dividing ratio between the first resistor and the potentiometer.

Preferably, the rising edge time of the gate modulation pulse of the LDMOS transistor can be adjusted by adjusting the values of the sixth resistor and the gate capacitance; the falling edge time of the gate modulation pulse of the LDMOS transistor can be adjusted by adjusting the value of the gate modulation pulse of the LDMOS transistor. The values of the sixth resistor, the ninth resistor and the gate capacitance are adjusted.

Preferably, the radio frequency output signal of the LDMOS solid-state power amplifier is a continuous wave or a pulse signal.

Preferably, the first pin is the en pin, the second pin is the gnd pin, the third pin and the fourth pin are the in pin, the fifth pin and the The sixth pin is the vout pin, the seventh pin is the sen pin, and the eighth pin is the adj pin.

Preferably, the buffer is set as a forward/reverse buffer.

Compared with the prior art, the beneficial effects of the present invention are: the present invention utilizes an adjustable regulated power supply, a co-direction/reverse buffer, a turn-on circuit, and a turn-off circuit to realize the gate modulation circuit of the LDMOS tube and realize the gate voltage of the LDMOS tube. The amplitude is adjustable, the time of the front and rear edges of the pulse waveform is adjustable, the circuit is simple, the realization is convenient, and the reliability is high.

Description of drawings

1 is a circuit diagram of a gate modulation circuit of an LDMOS solid-state power amplifier of the present invention;

FIG. 2 is a timing diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention.

Detailed ways

The above and other technical features and advantages of the present invention will be described in more detail below with reference to the accompanying drawings.

Example 1

As shown in FIG. 1, FIG. 1 is a circuit diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention; the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention includes an adjustable regulated power supply, a buffer, and a turn-on circuit. , Turn off the circuit.

Specifically, the adjustable regulated power supply includes a first resistor R1, a potentiometer RP1, a first energy storage capacitor C1, a second energy storage capacitor C2, and a voltage regulator U1.

The voltage regulator U1 includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, and an eighth pin. One pin is the en pin, the second pin is the gnd pin, the third pin and the fourth pin are both the in pin, the fifth pin and the sixth pin are both The vout pin, the seventh pin is the sen pin, and the eighth pin is the adj pin.

The positive end of the first energy storage capacitor C1 is connected to the first pin, the third pin, and the fourth pin of the voltage regulator U1, and the first energy storage capacitor C1 The negative terminal is grounded.

The positive end of the second energy storage capacitor C2 is connected to the fifth pin, the sixth pin, and the seventh pin of the voltage regulator U1, and the second energy storage capacitor C2 The negative terminal is grounded.

The second pin of the voltage regulator U1 is grounded.

The first resistor R1 and the potentiometer RP1 are connected in series, and the common terminal of the first resistor R1 and the potentiometer RP1 is connected to the adjustment terminal of the voltage regulator U1, that is, the eighth pin, the One end of the first resistor R1 is connected to the fifth pin, the sixth pin and the seventh pin of the voltage regulator U1, and one end of the potentiometer RP1 is grounded. The output voltage value of the voltage regulator U1 is adjusted by the potentiometer RP1.

Preferably, the input end of the buffer U2 is connected to an external TTL modulation signal, and the output end of the buffer U2 includes a first output end and a second output end, so that the external TTL modulation signal is divided into two signals, the The first output terminal outputs a forward signal and is connected to one end of the second resistor R2, and the second output terminal outputs a reverse signal and is connected to one end of the seventh resistor R7, and the two signals are in opposite phases.

The buffer U2 is preferably configured as a forward/reverse buffer.

Preferably, the turn-on circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a turn-on transistor V1, a first Zener diode V2, and a gate capacitor C3.

The third resistor R3 is connected in parallel with the negative electrode of the first Zener diode V2, and the negative electrode of the first Zener diode V2 is connected to one end of the second resistor R2 and then connected to the gate of the turn-on transistor V1, The anode of the first Zener diode V2 is grounded. The second resistor R2, the third resistor R3 and the first Zener diode V2 are the gate protection circuit of the turn-on transistor V1 to prevent the turn-on tube V1 from being damaged by excessive voltage.

One end of the fourth resistor R4 and the fifth resistor R5 connected in parallel is connected to the source of the open tube V1, and the other end is grounded, so as to ensure that when there is no external TTL signal input, the source of the open tube V1 is grounded potential.

One end of the sixth resistor R6 is connected to the source of the turn-on transistor V1, the other end is connected to the gate capacitor C3, and the other end of the gate capacitor C3 is grounded. The sixth resistor R6 and the gate capacitor C3 form a charging loop, which can adjust the leading edge time of the gate pulse of the LDMOS transistor.

Preferably, the shutdown circuit includes the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the shutdown transistor V3, the second Zener diode V4, and the third Zener diode V5. .

The eighth resistor R8 is connected in parallel with the negative electrode of the second Zener diode V4, and the negative electrode of the second Zener diode V4 is connected to one end of the seventh resistor R7 and then connected to the gate of the shutdown transistor V3. , the anode of the second Zener diode V4 is grounded. The seventh resistor R7, the eighth resistor R8 and the second Zener diode V4 are the gate protection circuit of the shutdown transistor V3 to prevent the shutdown transistor from being damaged due to excessive voltage.

Both ends of the ninth resistor R9 are respectively connected to the drain of the turn-off transistor V3 and the source of the turn-on transistor V1, so as to limit the current passing through when the turn-off transistor is turned on. The tenth resistor R10 is connected in parallel with the third Zener diode V5, the cathode of the third Zener diode V5 is connected to the source of the turn-on tube V1, and the anode of the third Zener diode V5 is grounded, using to filter out the voltage spike between the drain and source of the turn-off transistor V3.

Embodiment 2

Specifically, the specific working principle of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention is that the output voltage of the voltage regulator U1 can be adjusted through the first resistor R1 and the potentiometer RP1, and an appropriate The resistance value of the first resistor R1 and the potentiometer RP1 can control the output voltage value range of the voltage stabilizer U1 to be between 0.8V and 5V.

When the external TTL modulation signal is low level, the first output terminal of the buffer U2 outputs a low level, the second output terminal outputs a high level, the turn-on transistor V1 is turned off, and the turn-off transistor V3 is turned on, the gate voltage of the LDMOS tube is 0V, and the LDMOS tube is turned off, thereby ensuring that the LDMOS solid-state power amplifier is in the off state and no signal is output, ensuring reliable cut-off; when the external TTL modulation signal is at a high level , the first output terminal of the buffer U2 outputs a high level, the second output terminal outputs a low level, the turn-on transistor V1 is turned on, the turn-off transistor V3 is turned off, and the LDMOS transistor gate The pole voltage is the voltage value output by the voltage regulator U1, and the LDMOS transistor is turned on, thereby ensuring that the LDMOS solid-state power amplifier is in an amplifying state and starts signal output, ensuring reliable conduction and amplification.

FIG. 2 is a timing diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention, and the specific waveforms of each point in FIG. 2 are described:

RFin is the radio frequency input pulse signal, TTL is the externally input pulse modulation signal, H is the gate pulse signal of the turn-on transistor V1, L is the gate pulse signal of the turn-off transistor V3, and M is the gate pulse modulation of the LDMOS transistor Signal.

Among them, the RFin signal is generally a pulse-modulated signal, which is nested in the TTL signal, but sometimes for some applications, the RFin signal has a wider pulse width than the TTL signal, or it can be a continuous wave signal. After being amplified by the LDMOS solid-state power amplifier, the The leading and trailing edge time of the signal output pulse depends on the leading and trailing edge time of the gate pulse signal applied to the LDMOS tube.

In FIG. 2 , the rising edge time t1 of the gate pulse modulation signal of the LDMOS transistor is adjustable. When the turn-on transistor V1 is turned on, the output power of the voltage regulator U1 is connected to the gate through the sixth resistor R6. The capacitor C3 and the capacitance between the gate and source of the LDMOS tube are charged. When the gate voltage of the LDMOS tube reaches the turn-on voltage (VGS(TH)), the LDMOS tube starts to conduct, and its on time is determined by the sixth resistor R6 and all The capacitance value between the gate capacitor C3 and the gate-source of the LDMOS transistor is determined. Since the capacitance value between the gate-source of the LDMOS transistor is basically fixed, the value of the sixth resistor R6 and the gate capacitor C3 can be adjusted by adjusting the values of the sixth resistor R6 and the gate capacitor C3. The size of the rising edge time t1.

In FIG. 2, the falling edge time t2 of the gate pulse modulation signal of the LDMOS transistor is adjustable. When the turn-on transistor V1 is turned off, the turn-off transistor V3 is turned on, and the gate capacitor C3 is connected to the gate-source of the LDMOS transistor. The charge on the capacitor is discharged to the ground through the sixth resistor R6 and the ninth resistor R9. When the gate voltage of the LDMOS tube is lower than the turn-on voltage (VGS(TH)), the LDMOS tube starts to turn off, and the cut-off time is determined by the The sixth resistor R6, the ninth resistor R9, the gate capacitor C3 and the capacitance between the gate and source of the LDMOS transistor are determined. Since the capacitance between the gate and source of the LDMOS transistor is a fixed value, by adjusting the sixth resistor R6 , the value of the ninth resistor R9 and the gate capacitor C3 can adjust the falling edge time t2.

The invention utilizes an adjustable regulated power supply, a co-direction/reverse buffer, a turn-on circuit, and a turn-off circuit to realize the gate modulation circuit of the LDMOS tube, so as to realize the adjustable amplitude of the gate voltage of the LDMOS tube and the adjustable time of the front and rear edges of the pulse waveform. The circuit is simple, the realization is convenient, and the reliability is high.

The above descriptions are only preferred embodiments of the present invention, which are merely illustrative rather than limiting for the present invention. Those skilled in the art understand that many changes, modifications and even equivalents can be made within the spirit and scope defined by the claims of the present invention, but all fall within the protection scope of the present invention.

Claims (6)

1. a gate modulation circuit of an LDMOS solid-state power amplifier, is characterized in that, comprises adjustable regulated power supply, buffer, turn-on circuit, shut-off circuit; Described adjustable regulated power supply passes through described turn-on circuit and LDMOS tube connected, the buffer is connected to the LDMOS transistor through the turn-on circuit and the turn-off circuit, the adjustable voltage-stabilized power supply provides a stable output voltage, the buffer, the turn-on circuit, the turn-off circuit The disconnection circuit is connected with the LDMOS tube to realize the state switching and adjustment of the LDMOS solid-state power amplifier; The adjustable regulated power supply includes a first resistor, a potentiometer, a first energy storage capacitor, a second energy storage capacitor, and a voltage stabilizer; the positive end of the first energy storage capacitor is connected to the first energy storage capacitor of the voltage stabilizer. A pin, a third pin and a fourth pin, the negative end of the first energy storage capacitor is grounded; the positive end of the second energy storage capacitor is connected to the fifth pin, the fourth pin of the voltage stabilizer The sixth pin and the seventh pin, the negative end of the second energy storage capacitor is grounded; the second pin of the voltage stabilizer is grounded; the first resistor and the potentiometer are connected in series, and the first resistor and the common terminal of the potentiometer is connected to the eighth pin of the voltage stabilizer, and the other end of the first resistor is connected to the fifth pin, the sixth pin and the other end of the voltage stabilizer. the seventh pin, the other end of the potentiometer is grounded; The first pin is the en pin, the second pin is the gnd pin, the third pin and the fourth pin are the in pin, the fifth pin and the sixth pin are The pins are all vout pins, the seventh pin is the sen pin, and the eighth pin is the adj pin; the input end of the buffer is connected to an external TTL modulation signal, and the output end of the buffer includes the first output terminal and a second output terminal, the first output terminal outputs a forward signal and is connected to the first terminal of the second resistor, and the second output terminal outputs a reverse signal and is connected to the seventh resistor of the shutdown circuit The first end of the first output end and the output signal phase of the second output end are opposite; The turn-on circuit includes the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the turn-on tube, the first Zener diode, and the gate capacitor; the third resistor and the first resistor Zener diodes are connected in parallel, the cathode of the first Zener diode is connected to the second end of the second resistor and then connected to the gate of the turn-on tube, and the anode of the first Zener diode is grounded; the first Zener diode is connected to the ground; One end of the fourth resistor and the fifth resistor connected in parallel is connected to the source of the turn-on tube, and the other end is grounded; one end of the sixth resistor is connected to the source of the turn-on tube, and the other end is connected to the gate capacitor, The other end of the gate capacitor is grounded; the drain of the turn-on tube is connected to the fifth pin, the sixth pin and the seventh pin of the voltage regulator. 2. The gate modulation circuit of the LDMOS solid-state power amplifier according to claim 1, wherein the shutdown circuit further comprises an eighth resistor, a ninth resistor, a tenth resistor, a shutdown transistor, a second voltage regulator diode and a third Zener diode; the eighth resistor and the second Zener diode are connected in parallel, and the negative electrode of the second Zener diode and the second end of the seventh resistor are connected to the shutdown tube The gate of the second Zener diode is connected to the ground; the two ends of the ninth resistor are respectively connected to the drain of the turn-off tube and the source of the turn-on tube; the tenth resistor and the The third zener diode is connected in parallel, the negative electrode of the third zener diode is connected to the source electrode of the turn-on tube, and the positive electrode of the third zener diode is grounded. 3. The gate modulation circuit of the LDMOS solid-state power amplifier according to claim 1, wherein the output voltage of the voltage regulator is adjusted by the potentiometer, and the adjustment range is determined by the first resistor and the The voltage divider ratio of the potentiometer is determined. 4. The gate modulation circuit of the LDMOS solid-state power amplifier according to claim 2, wherein the rising edge time of the gate modulation pulse of the LDMOS transistor is adjusted by adjusting the values of the sixth resistor and the gate capacitance Adjustment; the falling edge time of the gate modulation pulse of the LDMOS transistor can be adjusted by adjusting the values of the sixth resistor, the ninth resistor and the gate capacitance. 5 . The gate modulation circuit of the LDMOS solid-state power amplifier according to claim 1 , wherein the radio frequency output signal of the LDMOS solid-state power amplifier is a continuous wave or a pulse signal. 6 . 6 . The gate modulation circuit of the LDMOS solid-state power amplifier according to claim 1 , wherein the buffer is set as a non-inverting/inverting buffer. 7 .

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