CN108878419B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate, the substrate comprising a high-resistance device region, the high-resistance device region being composed of a device region and an edge region; forming discrete dummy gates on the substrate of the device region and the edge region ; An interlayer dielectric film is formed on the exposed substrate of the dummy gate, and the interlayer dielectric film covers the top of the dummy gate; the interlayer dielectric film is planarized so that the remaining interlayer dielectric film is exposed on the top of the dummy gate, and the remaining layers The interlayer dielectric film serves as an interlayer dielectric layer. Compared with the solution in which the dummy gate is not formed, the present invention can improve the top flatness of the interlayer dielectric layer and improve the top dishing problem of the interlayer dielectric layer during the subsequent planarization process of forming the interlayer dielectric layer. Thereby, it is beneficial to improve the performance of the semiconductor structure.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, integrated circuit feature sizes continue to decrease. In order to accommodate the reduction in feature size, the channel length of MOSFET devices has also been shortened accordingly. However, with the shortening of the channel length of the device, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinch off the channel. The difficulty is also increasing, making subthreshold leakage (subthreshold leakage) phenomenon, the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better accommodate the reduction in feature size, semiconductor technology has gradually begun to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFETs). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides, which has much stronger gate-to-channel control capability than planar MOSFET devices, and can well suppress short-channel effects; and FinFET is relatively For other devices, it has better compatibility with existing integrated circuit fabrication technologies.

In FinFETs, a large number of resistor devices (Resistor Device) are used. At present, with the introduction of metal gate (MetalGate), in order to reduce process difficulty and process cost, a metal layer is generally formed on the interlayer dielectric layer above the isolation structure as a metal resistance device.

However, the process of forming the metal resistance device tends to degrade the performance of the semiconductor structure.

SUMMARY OF THE INVENTION

The problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same to optimize the performance of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a high-resistance device region, and the high-resistance device region is composed of a device region and an edge region; A discrete dummy gate is formed on the substrate of the edge region; an interlayer dielectric film is formed on the exposed substrate of the dummy gate, and the interlayer dielectric film covers the top of the dummy gate; and the interlayer dielectric film is subjected to During the planarization process, the top of the dummy dummy gate is exposed by the remaining interlayer dielectric film, and the remaining interlayer dielectric film is used as an interlayer dielectric layer.

Optionally, after the interlayer dielectric layer is formed, the method further includes the steps of: removing the dummy dummy gate in the edge region, and forming an opening in the interlayer dielectric layer; forming a dummy metal gate filling the opening; A metal layer is formed on the interlayer dielectric layer in the device region.

Optionally, the extending direction of the metal layer is perpendicular to the extending direction of the dummy gate.

Optionally, the metal layer is doped with N ions or C ions.

Optionally, the material of the metal layer is one or more of TiN, TaN, TiCN or TiC.

至

Optionally, the thickness of the metal layer is

to

Optionally, after the metal layer is formed, the method further includes the step of: forming a conductive plug electrically connected to the metal layer.

Optionally, the distance between the device region and the edge region is 5 nm to 2000 nm.

Optionally, the base includes a substrate and a plurality of discrete fins on the substrate, the substrate including a high resistance device region.

Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate includes a high-resistance device region, and the high-resistance device region is composed of a device region and an edge region; a dummy gate located at the device region and the edge The interlayer dielectric layer is located on the substrate exposed by the dummy gate, and the top of the interlayer dielectric layer exposed to the dummy gate is flush.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, discrete dummy gates are formed on the substrates of the device region and the edge region. Compared with the solution in which the dummy gates are not formed, in the subsequent planarization process of forming the interlayer dielectric layer, the interlayer dielectric layer can be improved. The flatness of the top of the dielectric layer can improve the top dishing problem of the interlayer dielectric layer, thereby helping to improve the performance of the semiconductor structure.

In an optional solution, after forming the interlayer dielectric layer, it further includes forming a metal layer on the interlayer dielectric layer located in the device region, and the extension direction of the metal layer is perpendicular to the extension direction of the dummy gate, Therefore, the cross talk effect (Cross Talk Effect) between the metal layer and the dummy gate can be avoided.

In an optional solution, after the interlayer dielectric layer is formed, a dummy metal gate is used to replace the dummy dummy gate in the edge region; in semiconductor manufacturing, a metal gate of a transistor is usually formed, and a dummy metal gate is used to replace the dummy gate. The virtual dummy gate in the edge region can form the metal gate and the dummy metal gate in the same step, thereby improving the planarization effect during the formation of the metal gate and improving the top recess of the metal gate.

In an optional solution, the dummy dummy gate in the device region is not replaced by a dummy metal gate, so that electromagnetic interference (eg, inductance effect) of the metal layer can be reduced.

Description of drawings

1 to 12 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

It can be known from the background art that the process of forming the metal resistance device is likely to cause performance degradation of the semiconductor structure. The reasons for the performance degradation in analyzing semiconductor structures are:

Currently, a discrete metal layer is usually formed on the interlayer dielectric layer above the isolation structure as a Metal Resistor Device. When the interlayer dielectric layer is formed, since the area corresponding to the isolation structure is an sparse area (Iso Area), after the planarization process for forming the interlayer dielectric layer, the top of the interlayer dielectric layer is flat. The thickness is poor, and the top of the interlayer dielectric layer is prone to a problem of dishing, which leads to a decrease in the performance of the semiconductor structure.

In order to solve the technical problem, the present invention forms discrete dummy gates on the substrates of the device region and the edge region. Compared with the solution without forming the dummy gates, the top of the interlayer dielectric layer after the planarization process can be improved. The flatness improves the top concave problem of the interlayer dielectric layer.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 12 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

1 and 2, FIG. 1 is a top view, and FIG. 2 is a schematic cross-sectional structure diagram of FIG. 1 along the A1A2 secant line, providing a substrate (not marked), the substrate includes a high-resistance device region (not marked), the high The resistive device region consists of device region I and edge region II.

In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100 , and the substrate 100 includes a high-resistance device region.

The high resistance device region is used to form a metal resistance device. Specifically, the metal resistance device is formed on the device region I.

In this embodiment, the fins 110 are formed on the substrate 100 of the high-resistance device region, and the fins 110 of the high-resistance device region are used to improve the pattern density of the high-resistance device region. , compared with the solution in which the fins 110 are not formed on the high-resistance device region substrate 100 , when the interlayer dielectric layer is subsequently formed on the isolation structure 111 , the planarization of the interlayer dielectric layer can be improved. The problem of top recess after processing, thereby improving the top flatness of the interlayer dielectric layer.

It should be noted that the substrate 100 further includes a transistor region (not shown) for forming a fin field effect transistor, and the fin portion 110 of the transistor region is used for providing a channel of the formed fin field effect transistor .

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

The material of the fins 110 is the same as that of the substrate 100 . In this embodiment, the material of the fins 110 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, in order to make the process environments on both sides of the device region I the same or similar, thereby improving the planarization effect, the edge region II is located on both sides of the device region I.

It should be noted that, as shown in FIG. 1 , in this embodiment, the number of fins 110 on the device region I and the edge region II is taken as an example for illustration (for the convenience of illustration, the device region in FIG. 2 is used for illustration). 3 fins 110) are shown in each of I and edge region II. However, the present invention does not limit the number of fins 110 on the device region I and the edge region II.

The distance between the device region I and the edge region II should neither be too small nor too large. If the distance is too small, the top of the interlayer dielectric layer on the side of the edge region II away from the device region I is prone to sinking; if the distance is too large, the gap between the edge region II and the device region I The top of the interlayer dielectric layer in between is prone to sinking problems. Therefore, in this embodiment, the distance between the device region I and the edge region II is 5 nm to 2000 nm.

Referring to FIG. 2 , after the base is provided, the step further includes: forming an isolation structure 111 on the substrate 100 , the isolation structure 111 covers part of the sidewall of the fin 110 , and the top of the isolation structure 111 is lower than the top of the fins 110 .

The isolation structure 111 is used as an isolation structure of the semiconductor device, and is used for isolating adjacent devices and also for isolating the adjacent fins 110 .

In this embodiment, the material of the isolation structure 111 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

3 to 6, FIG. 3 is a top view based on FIG. 1, FIG. 4 is a schematic cross-sectional structure diagram of FIG. 3 along the B1B2 secant line (the device area and the edge area each illustrate 3 fins), and FIG. 5 is FIG. 3 A schematic cross-sectional structure along the C1C2 secant line (only two dummy gates are shown), FIG. 6 is a cross-sectional structure schematic diagram along the D1D2 secant line in FIG. 3 (only two virtual dummy gates are shown), in the device regions I and A discrete dummy gate 120 is formed on the substrate (not shown) of the edge region II.

The dummy gate 120 is used to improve the pattern density (PatternDensity) of the high-resistance device region (not marked). Compared with the solution in which the dummy gate 120 is not formed, a layer is subsequently formed on the isolation structure 111 When the interlayer dielectric layer is formed, the problem of the top depression of the interlayer dielectric layer after the planarization process can be improved, thereby improving the top flatness of the interlayer dielectric layer.

In this embodiment, the metal resistance device is subsequently formed on the interlayer dielectric layer of the device region I. In order to reduce the electromagnetic interference (eg inductance effect) of the metal resistance device, the material of the dummy gate 120 is: polysilicon.

The polysilicon material has high process compatibility, so that the introduction of the dummy gate 120 can avoid adverse effects on the performance of the formed semiconductor structure.

Specifically, the dummy gate 120 spans the fin portion 110 and covers part of the top surface and sidewall surface of the fin portion 110 . Wherein, the dummy dummy gates 120 of the device region I and the edge region II are separated from each other, so as to facilitate the subsequent processing of the dummy dummy gates 120 of the device region I and the edge region II respectively.

It should be noted that, the substrate 100 further includes a region for forming a fin field effect transistor (not shown in the figure), so in the step of forming the dummy gate 120, the dummy gate 120 also spans all the The fins 110 of the transistor region are described.

The dummy gate 120 in the transistor region occupies a space for the metal gate (MetalGate) of the fin field effect transistor to be formed subsequently.

7 and 8 , FIG. 7 is a schematic cross-sectional structure diagram based on FIG. 5 , and FIG. 8 is a cross-sectional structure schematic diagram based on FIG. 6 , an interlayer dielectric film is formed on the substrate (not labeled) exposed by the dummy gate 120 , the interlayer dielectric film covers the top of the dummy gate 120; the interlayer dielectric film is planarized so that the remaining interlayer dielectric film is exposed on the top of the dummy gate 120, and the remaining interlayer dielectric The film serves as the interlayer dielectric layer 130 .

The interlayer dielectric layer 130 provides a process platform for the subsequent formation of the metal gate of the fin field effect transistor, provides a process platform for the formation process of the metal resistance device, and is also used to isolate adjacent devices. .

In this embodiment, the top of the interlayer dielectric layer 130 is flush with the top of the dummy gate 120 .

The material of the interlayer dielectric layer 130 is an insulating material. The material of the interlayer dielectric layer 130 may be silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 130 is silicon oxide.

In this embodiment, the process used in the planarization treatment is a chemical mechanical polishing (CMP) process.

It should be noted that the substrate 100 of the high-resistance device region (not marked) is formed with the fins 110 and the dummy gates 120 spanning the fins 110 , so the pattern of the high-resistance device region is dense Therefore, the problem of the top depression of the interlayer dielectric layer 130 in the high-resistance device region after the planarization process can be improved, which is beneficial to improve the top flatness of the interlayer dielectric layer 130 .

9 to 11 , FIG. 9 is a schematic cross-sectional structure based on FIG. 8 , FIG. 10 is a cross-sectional structural schematic based on FIG. 9 , and FIG. 11 is a cross-sectional structure based on FIG. 7 . After forming the interlayer dielectric layer 130 , further comprising the steps of: removing the dummy gate 120 (as shown in FIG. 8 ) in the edge region II (as shown in FIG. 9 ), and forming an opening 121 in the interlayer dielectric layer 130 (as shown in FIG. 9 ) ; forming a dummy metal gate 122 (as shown in FIG. 10 ) filling the opening 121 ; forming a metal layer 140 (as shown in FIG. 11 ) on the interlayer dielectric layer 130 in the device region I (as shown in FIG. 11 ) shown).

In this embodiment, in the step of removing the dummy gate 120 in the edge region II, the dummy gate 120 in the transistor region is also removed, and the opening 121 is also formed in the interlayer dielectric layer 130 in the transistor region ; That is, in the same step, the dummy gates 120 of the transistor region and the edge region II are removed.

Specifically, the process used to remove the dummy gate 120 in the transistor region and the edge region II is a wet etching process.

In other embodiments, a dry etching process or a combination of dry and wet etching processes may also be used to remove the dummy gates in the transistor region and the edge region.

Correspondingly, in the step of forming the dummy metal gate 122, a metal gate is also formed in the opening 121 of the transistor region.

The metal gate is used to control the opening and closing of the channel of the formed fin field effect transistor.

Specifically, the steps of forming the metal gate and the dummy metal gate 122 include: forming a metal material layer filling the opening 121, the metal material layer covering the top of the interlayer dielectric layer 130; A planarization process is performed to remove the metal material layer above the top of the interlayer dielectric layer 130 , the remaining metal material layer located in the transistor area opening 121 is used as a metal gate, and the remaining metal material layer located in the edge area II opening 121 The material layer acts as a dummy metal gate 122 .

Wherein, the material of the metal material layer may be W, Al, Cu, Ag, Au, Pt, Ni or Ti.

In this embodiment, the process used in the planarization treatment is a chemical mechanical polishing process.

By using the dummy metal gate 122 to replace the dummy dummy gate 120 in the edge region II, in the process of forming the metal gate, the metal material layer in the edge region II is also planarized, thereby improving the performance of the edge region II. The effect of planarization during metal gate formation.

In addition, the dummy dummy gate 120 of the device region I is not replaced by the dummy metal gate 122, so that the electromagnetic interference (eg, inductance effect) of the metal layer 140 formed subsequently can be reduced.

In this embodiment, the metal layer 140 is used as a metal resistance device.

The resistivity target value of the metal resistance device is determined according to actual process requirements. In this embodiment, the resistivity target value of the metal resistance device is 600 ohms/square to 700 ohms/square.

In order to reduce the resistivity of the metal resistance device, the metal layer 140 has doping ions, and the doping ions are N ions or C ions, and the higher the doping concentration of the doping ions, the higher the resistivity. Small. Specifically, according to the target value of the resistivity of the metal resistance device, the doping concentration of the doping ions is reasonably controlled.

In this embodiment, the material of the metal layer 140 is one or more of TiN, TaN, TiCN and TiC.

至

The thickness of the metal layer 140 is determined according to actual process requirements, so that the resistivity of the metal resistance device can reach the target value. In this embodiment, the thickness of the metal layer 140 is

to

It should be noted that the metal layer 140 is formed on the interlayer dielectric layer 130 of the device region I, in order to avoid the crosstalk effect (Cross Talk between the metal layer 140 and the dummy gate 120 of the device region I) Effect), the extending direction of the metal layer 140 is perpendicular to the extending direction of the dummy gate 120 .

It should also be noted that, referring to FIG. 12 , which is a schematic cross-sectional structure diagram based on FIG. 11 , after the metal layer 140 is formed, the step further includes: forming a conductive plug 150 electrically connected to the metal layer 140 .

The conductive plug 150 is used to achieve electrical connection with the high-resistance device region, and is also used to achieve electrical connection between the device and an external circuit. In this embodiment, the material of the contact hole plug 150 is a metal material such as W, Al, Cu, Ag, or Au.

Correspondingly, the present invention also provides a semiconductor structure.

3, 4, 7 and 8, the semiconductor structure includes:

A substrate (not marked), the substrate includes a high-resistance device region (not marked), and the high-resistance device region is composed of a device region I and an edge region II; the dummy gate 120 is located in the device region I and the edge region II The interlayer dielectric layer 130 is located on the exposed substrate of the dummy dummy gate 120 , and the interlayer dielectric layer 130 exposes the top of the dummy dummy gate 120 .

In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100 , and the substrate 100 includes a high-resistance device region.

The high resistance device region is used to form a metal resistance device. Specifically, the metal resistance device is formed on the device region I.

It should be noted that the substrate 100 further includes a transistor region (not shown) for forming a fin field effect transistor, and the fin portion 110 of the transistor region is used for providing a channel of the formed fin field effect transistor .

It should also be noted that, as shown in FIG. 1 , in this embodiment, the number of fins 110 on the device region I and the edge region II is taken as an example for description (for the convenience of illustration, the device in FIG. 4 is used for illustration). Region I and edge region II each illustrate 3 fins 110). However, the present invention does not limit the number of fins 110 on the device region I and the edge region II.

In this embodiment, the high-resistance device region substrate 100 has the fins 110 and dummy gates 120 , and the fins 110 and the dummy gates 120 of the high-resistance device region are used to improve the high-resistance device region The pattern density (PatternDensity); the formation process of the interlayer dielectric layer 130 includes a planarization process, compared with the high-resistance device region substrate 100 without the fins 110 and the dummy gate 120. The present invention can improve the top concave problem of the interlayer dielectric layer 130 after the planarization process, thereby improving the top flatness of the interlayer dielectric layer 130 .

In this embodiment, in order to make the process environments on both sides of the device region I the same or similar, thereby improving the planarization effect, the edge region II is located on both sides of the device region I.

The distance between the device region I and the edge region II should neither be too small nor too large. If the distance is too small, the top of the interlayer dielectric layer 130 on the side of the edge region II away from the device region I is prone to concave problems; if the distance is too large, the edge region II and the device region I The top of the interlayer dielectric layer 130 in between is prone to a concave problem. Therefore, in this embodiment, the distance between the device region I and the edge region II is 5 nm to 2000 nm.

In this embodiment, the metal resistance device is formed on the interlayer dielectric layer 130 of the device region I. In order to reduce the electromagnetic interference (eg inductance effect) of the metal resistance device, the material of the dummy gate 120 is polysilicon.

The polysilicon material has high process compatibility, so that the introduction of the dummy gate 120 can avoid adverse effects on the performance of the formed semiconductor structure.

The interlayer dielectric layer 130 provides a process platform for forming the metal gate of the fin field effect transistor, provides a process platform for the formation process of the metal resistance device, and also serves to isolate adjacent devices.

In this embodiment, the top of the interlayer dielectric layer 130 is flush with the top of the dummy gate 120 .

In this embodiment, the semiconductor structure further includes: an isolation structure 111 located on the substrate 100, the isolation structure 111 covers part of the sidewall of the fin 110, and the top of the isolation structure 111 is lower than the the top of the fins 110.

The isolation structure 111 is used as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and also for isolating adjacent fins 110 .

The semiconductor structure is formed by the foregoing formation method. For the specific description of the semiconductor structure, please refer to the corresponding description in the foregoing formation method, and details are not repeated here.

In the present invention, the discrete dummy gates 120 are formed on the substrates of the device region I and the edge region II, thereby improving the top flatness of the interlayer dielectric layer 130 after the planarization process, and improving the top recess of the interlayer dielectric layer 130 question.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (8)

1. A method for forming a semiconductor structure, comprising: providing a base including a substrate and a plurality of discrete fins on the substrate, the substrate including a high resistance device region consisting of a device region and an edge region; A plurality of discrete dummy gates are respectively formed on the substrates of the device region and the edge region; the dummy gates formed on the substrate of the device region span each of the fins on the device region and cover the a portion of the top surface and sidewall surface of a fin; a dummy gate formed on the base of the edge region spanning each of the fins on the edge region and covering a portion of the top surface and sides of the fin wall surface; forming an interlayer dielectric film on the exposed substrate of the dummy gate, the interlayer dielectric film covering the top of the dummy gate; performing a planarization process on the interlayer dielectric film, so that the remaining interlayer dielectric film is exposed on the top of the dummy gate, and the remaining interlayer dielectric film is used as an interlayer dielectric layer; After the interlayer dielectric layer is formed, the dummy gate in the edge region is removed, and an opening is formed in the interlayer dielectric layer; forming a dummy metal gate filling the opening; A metal layer is formed on the interlayer dielectric layer in the device region. 2 . The method for forming a semiconductor structure according to claim 1 , wherein the extending direction of the metal layer is perpendicular to the extending direction of the dummy gate. 3 . 3 . The method for forming a semiconductor structure according to claim 1 , wherein the metal layer is doped with N ions or C ions. 4 . 4 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the metal layer is one or more of TiN, TaN, TiCN and TiC. 5 . 5. The method for forming a semiconductor structure according to claim 1, wherein the thickness of the metal layer is

to

6 . The method for forming a semiconductor structure according to claim 1 , wherein after the metal layer is formed, the method further comprises the step of: forming a conductive plug electrically connected to the metal layer. 7 . 7 . The method for forming a semiconductor structure according to claim 1 , wherein the distance between the device region and the edge region is 5 nm to 2000 nm. 8 . 8. A semiconductor structure, characterized in that, comprising: a base, the base including a substrate and a plurality of discrete fins on the substrate, the substrate including a high-resistance device region, the high-resistance device region consisting of a device region and an edge region; A plurality of discrete dummy gates are respectively located on the substrates of the device region and the edge region; the dummy gates formed on the substrate of the device region span each of the fins on the device region and cover the a portion of the top surface and sidewall surface of a fin; a dummy gate formed on the base of the edge region spanning each of the fins on the edge region and covering a portion of the top surface and sides of the fin wall surface; an interlayer dielectric layer, located on the exposed substrate of the dummy gate, and the interlayer dielectric layer exposes the top of the dummy gate; A metal layer is formed on the interlayer dielectric layer in the device region.

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