CN108878440A - SONOS non-volatility memorizer and its manufacturing method - Google Patents
SONOS non-volatility memorizer and its manufacturing method Download PDFInfo
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- CN108878440A CN108878440A CN201810696243.1A CN201810696243A CN108878440A CN 108878440 A CN108878440 A CN 108878440A CN 201810696243 A CN201810696243 A CN 201810696243A CN 108878440 A CN108878440 A CN 108878440A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000001413 cellular effect Effects 0.000 claims abstract description 71
- 238000010276 construction Methods 0.000 claims abstract description 71
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 238000003860 storage Methods 0.000 claims abstract description 42
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 170
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 95
- 229920005591 polysilicon Polymers 0.000 claims description 95
- 239000000758 substrate Substances 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 17
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000003694 hair properties Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a kind of SONOS non-volatility memorizers, dielectric layer is isolated between having the first grid in isolation between the second grid structure of selecting pipe and the first grid structure of storage tube, the first side that dielectric layer autoregistration is formed in first grid structure is isolated between the first grid, second grid structure self-aligning is formed in the first side of isolation dielectric layer between the first grid；Two first grid structure forming regions are defined by first window in the cellular construction combination of two neighboring unit structure compositions, and the two sides of first grid structure are defined by the first top of medial surface silicon oxide layer autoregistration that autoregistration is formed in first window.The invention discloses a kind of manufacturing methods of SONOS non-volatility memorizer.The size of selecting pipe and storage tube of the invention is all defined by autoregistration, and the area of memory cell structure can be effectively reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of SONOS (Silicon-Oxide-
Nitride-Oxide-Silicon) non-volatility memorizer.The invention further relates to a kind of systems of SONOS non-volatility memorizer
Make method.
Background technique
SONOS non-volatility memorizer is widely used in advanced flash memory, electrically-erasable memory product.SONOS is non-to be waved
The cellular construction of hair property memory generally includes storage tube and selecting pipe, the cellular construction of 2T type SONOS non-volatility memorizer
In include a complete storage tube and a complete selecting pipe, each transistor, that is, storage tube and selecting pipe have completely
Source region, drain region and polysilicon gate, and the polysilicon gate of two transistors shares one layer of polysilicon.Since existing 2T type SONOS is non-
The storage tube and selecting pipe of the cellular construction of volatile storage all include by complete source region and drain region, and area occupied is larger.
In order to reduce the area of SONOS non-volatility memorizer, 1.5T type structure is generallyd use, is only needed in 1.5T type structure using two
Source-drain area, as shown in Figure 1, being the cellular construction figure of existing 1.5T type SONOS non-volatility memorizer, existing 1.5T type
The cellular construction of SONOS non-volatility memorizer includes：
The gate structure of storage tube includes the ONO layer 3 being formed on 1 surface of semiconductor substrate such as silicon substrate, the first polycrystalline
Si-gate 2 and top silicon oxide layer 4；ONO layer 3 is formed by stacking by oxide layer, nitration case and oxide layer.
The gate structure of selecting pipe includes the gate oxide 8 being formed on 1 surface of semiconductor substrate, the second polysilicon gate 6.
With dielectric layer 13 is isolated between the first grid between first polysilicon gate 2 and the second polysilicon gate 6, it is isolated between the first grid
Dielectric layer 13 generallys use oxide layer.
Two cellular constructions form a cellular construction and combine, in cellular construction combination, the first side of two storage tubes
It is adjacent, and the first side of two storage tubes is formed with side wall 14, fills out between the side wall 14 of the first side of two storage tubes
Filled with conductive polysilicon layer 5.The surface of the semiconductor substrate 1 between the first side of two storage tubes is formed with
One source and drain injection region 9.The bottom of polysilicon layer 5 and the first source and drain injection region 9 are adjacent.
It is formed in second side, that is, lateral surface of each second polysilicon gate 6 by side wall 12.The second of the second polysilicon gate 6
The surface of the semiconductor substrate 1 of lateral position is formed with the source and drain injection region 11 of lightly doped drain 10 and heavy doping, wherein gently
The side of the side autoregistration of doped drain 10 and second polysilicon gate 6, source and drain injection region 11 and corresponding side wall 12 is certainly
Alignment.
In addition, CMOS logic device is also integrated on the surface of same semi-conductive substrate 1, such as NMOS tube or PMOS tube, Fig. 1
In show the gate structure of logical device that one is formed by stacking by gate oxide 7 and the second polysilicon gate 61, in logic device
The two sides of the gate structure of part are also formed with corresponding lightly doped drain 10 and source and drain injection region 11.Second polycrystalline of logical device
Si-gate 61 and the second polysilicon gate 6 of selecting pipe are usually formed simultaneously, and are also formed in the side of the second polysilicon gate 61 by side wall
12；Gate oxide 7 and gate oxide 8 can be formed simultaneously when thickness is identical；The thickness of gate oxide 7 and gate oxide 8 also can
At this moment difference is formed separately.
2 cellular constructions are shown in Fig. 1, since each cellular construction includes adjacent the first polysilicon gate 2 and
Two polysilicon gates 6 and the structure that forms a whole, usually the first polysilicon gate 2 between two neighboring cellular construction are adjacent and total
With identical source and drain injection region 9, the second polysilicon gate 6 between two neighboring cellular construction is adjacent and shares identical source and drain note
Enter area 11；The source and drain injection region of each cellular construction includes two, i.e. source and drain injection region 9 and 11.
In structure shown in Fig. 1, the meeting of polysilicon layer 5 at 9 top of the source and drain injection region storage tube adjacent with another direction
Bit line be connected, the mode of operation of entire SONOS non-volatility memorizer need according to polysilicon layer 5 and with another side
The connection relationship being connected to the bit line of adjacent storage tube carries out.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of SONOS non-volatility memorizers, to selecting pipe and can deposit
The size for storing up pipe carries out autoregistration setting, can effectively reduce the area of memory cell structure.For this purpose, the present invention also provides one kind
The manufacturing method of SONOS non-volatility memorizer.
In order to solve the above technical problems, the cellular construction of SONOS non-volatility memorizer provided by the invention includes one
Storage tube and a selecting pipe.
The first grid structure of the storage tube includes being sequentially overlapped the ONO layer in semiconductor substrate surface, the first polycrystalline
Si-gate and the first top silicon oxide layer.
The second grid structure of the selecting pipe include be sequentially overlapped in the semiconductor substrate surface gate dielectric layer and
Second polysilicon gate.
Dielectric layer is isolated between having the first grid in isolation between the second grid structure and the first grid structure；Described
The first side that dielectric layer autoregistration is formed in the first grid structure, the second grid structure self-aligning are isolated between one grid
It is formed in the first side that dielectric layer is isolated between the first grid.
Two adjacent cellular constructions form a cellular construction and combine, in the cellular construction combination, described in two
The second side of the first grid structure of cellular construction is adjacent, the first grid structure of two cellular constructions
Region between first side is defined by first window；The first window is unfolded by the second silicon nitride layer photoetching, and two
The first top silicon oxide layer autoregistration of the cellular construction is formed in two medial surfaces of the first window；Described
The second side of one polysilicon gate is defined by the second side autoregistration of corresponding first top silicon oxide layer；Described first
The first side of polysilicon gate is defined by the first side autoregistration of corresponding first top silicon oxide layer, first window
Second silicon nitride layer outside mouthful is removed before the first side definition of first polysilicon gate.
It is described filled with isolating oxide layer between second gate in region between the second side of the first grid structure
It is formed before second silicon nitride layer removal of the isolating oxide layer outside the first window between second gate.
First source-drain area autoregistration is formed in the semiconductor substrate between the second side of the first grid structure
In, and first source-drain area shares for two cellular constructions in cellular construction combination, first source-drain area
Autoregistration is formed before isolating oxide layer is formed between the second gate.
Second source-drain area be formed in the semiconductor substrate outside the first side of the corresponding second grid structure and
The first side autoregistration of second source-drain area and the corresponding second grid structure.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that being formed with p-well, the first grid structure and described in the semiconductor substrate surface
Two gate structures are formed on the p-well surface, first source-drain area and second source-drain area all by N+ district's groups at.
A further improvement is that the gate dielectric layer is oxide layer；It is oxide layer that dielectric layer is isolated between the first grid.
A further improvement is that the second side in the first grid structure is formed with the first side wall；Described second
The first side of gate structure is formed with the second side wall.
A further improvement is that being also formed with the first lightly doped drain in first source-drain area, described first gently mixes
The second side autoregistration with corresponding first polysilicon gate respectively of the two sides in miscellaneous drain region；The two sides of first source-drain area
Respectively with the first side wall autoregistration of the second side of corresponding first polysilicon gate.
The second lightly doped drain, second lightly doped drain and corresponding institute are also formed in second source-drain area
State the first side autoregistration of the second polysilicon gate；The first side of second source-drain area and corresponding second side wall is certainly
Alignment.
A further improvement is that in first source-drain area, the table of second source-drain area and second polysilicon gate
Face autoregistration is formed with metal silicide.
A further improvement is that being formed with the contact for drawing first source-drain area at the top of first source-drain area
Hole, is formed with the contact hole for drawing second source-drain area at the top of second source-drain area, and each contact hole all passes through
Interlayer film.
In order to solve the above technical problems, the SONOS of the manufacturing method of SONOS non-volatility memorizer provided by the invention is non-
The cellular construction of volatile storage includes a storage tube and a selecting pipe；Include the following steps：
Step 1: sequentially forming ONO layer, the first polysilicon layer and the second silicon nitride layer in semiconductor substrate surface.
Step 2: carrying out chemical wet etching to second silicon nitride layer forms first window.
Step 3: forming first in two medial surfaces of the first window using growth of silicon oxide and comprehensive etching technics
Top silicon oxide layer.
Step 4: carrying out first time etching to first polysilicon layer between two first top silicon oxide layers
Form the second side of the first polysilicon gate of the two neighboring storage tube.
The first grid structure of the storage tube of each cellular construction includes being sequentially overlapped in semiconductor substrate surface
ONO layer, the first polysilicon gate and the first top silicon oxide layer；Two adjacent cellular constructions form a cellular construction group
Close, the second side of the first grid structure of two cellular constructions is adjacent and the second side of the first grid structure by
The second side of first top silicon oxide layer of the second side and top of first polysilicon gate is formed by stacking.
Step 5: carrying out two first grid structures that first time source and drain is infused in the cellular construction combination
Autoregistration forms the first source-drain area in the semiconductor substrate between second side, and first source-drain area is the unit knot
Two cellular constructions in structure combination share.
Step 6: filling isolation oxidation between second gate in region between the second side of the first grid structure
Layer.
Step 7: removing second silicon nitride layer and exposing the first side of each first top silicon oxide layer.
Step 8: carrying out second of etching to first polysilicon layer forms described the first of the corresponding storage tube
The first side of polysilicon gate, the first side of first polysilicon gate and the first side of first top silicon oxide layer
Autoregistration and together superposition form the first side of the first grid structure.
Step 9: forming the in the first side of the first grid structure using deposit plus comprehensive etching technics autoregistration
Dielectric layer is isolated between one grid and removes the ONO layer being isolated outside dielectric layer first side between the first grid.
Step 10: sequentially forming gate dielectric layer and the second polysilicon layer, comprehensive etching of polysilicon is carried out described first
Between grid be isolated dielectric layer first side autoregistration formed the second polysilicon gate, the second grid structure of the selecting pipe include according to
The secondary gate dielectric layer for being superimposed on the semiconductor substrate surface and second polysilicon gate.
Step 11: carrying out second of source and drain injection using the first side of the second grid structure as autoregistration boundary
The second source-drain area is formed in the semiconductor substrate outside the first side of the corresponding second grid structure.
Step 12: forming interlayer film and contact hole, the contact hole passes through the interlayer film, in first source-drain area
Top and the top of second source-drain area be all respectively formed with corresponding contact hole.
A further improvement is that being formed with p-well, the first grid structure and described in the semiconductor substrate surface
Two gate structures are formed on the p-well surface, first source-drain area and second source-drain area all by N+ district's groups at.
A further improvement is that the gate dielectric layer is oxide layer；It is oxide layer that dielectric layer is isolated between the first grid.
A further improvement is that after the second side side of the first polysilicon gate of storage tube described in step 4 is formed
Further include the steps that forming the first side wall in the second side of the first grid structure using deposit plus comprehensive etching technics.
Formed after second polysilicon gate in step 10 further includes using deposit plus comprehensive etching technics described the
The first side of two gate structures forms the step of the second side wall.
A further improvement is that further including carrying out first time lightly doped drain note before forming first side wall in step 4
The step of entering to form the first lightly doped drain, the two sides of first lightly doped drain respectively with corresponding first polysilicon
The second side autoregistration of grid, the second side of first source-drain area and corresponding first side wall in subsequent step five
Autoregistration, first lightly doped drain and first source-drain area are superimposed.
It is formed in step 10 before second side wall, further includes carrying out second of lightly doped drain to inject to form second gently
The step of doped drain, the first side autoregistration of second lightly doped drain and corresponding second polysilicon gate；Afterwards
The first side autoregistration of second source-drain area and corresponding second side wall in continuous step 11, described second gently mixes
Miscellaneous drain region and second source-drain area are superimposed.
A further improvement is that step 12 is formed before the interlayer film, further include：In first source-drain area, institute
The surface autoregistration for stating the second source-drain area and second polysilicon gate forms metal silicide.
A further improvement is that the material of first side wall includes silicon nitride；The material of second side wall includes nitrogen
SiClx.
In the cellular construction of SONOS non-volatility memorizer of the present invention, the first grid structure of storage tube is by by from right
Standard is formed in the first top silicon oxide layer autoregistration definition of the inside area of first window, and isolation dielectric layer is all between the first grid
The second grid structure self-aligning of first side and selecting pipe that autoregistration is formed in corresponding first grid structure is formed in
The first side of dielectric layer is isolated between the first grid, so, the gate structure of storage tube of the invention and selecting pipe is all used from right
Quasi- technique is formed, and additional lithographic definition is not needed, and the size of cellular construction can be made to accomplish minimum, so as to effectively reduce storage
The area of cellular construction.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the cellular construction figure of existing 1.5T type SONOS non-volatility memorizer；
Fig. 2 is the cellular construction figure of SONOS non-volatility memorizer of the embodiment of the present invention；
Fig. 3 A- Fig. 3 Q is the device junction composition in each step of present invention method.
Specific embodiment
As shown in Fig. 2, being the cellular construction figure of SONOS non-volatility memorizer of the embodiment of the present invention, the embodiment of the present invention
The cellular construction of SONOS non-volatility memorizer includes a storage tube and a selecting pipe.
The first grid structure of the storage tube includes being sequentially overlapped the ONO layer 102 in 101 surface of semiconductor substrate,
One polysilicon gate 103 and the first top silicon oxide layer 104.In the embodiment of the present invention, the semiconductor substrate 101 is silicon substrate.
It is formed with p-well on 101 surface of semiconductor substrate, the first grid structure and subsequent second grid structure are formed in
On the p-well surface.
The second grid structure of the selecting pipe includes being sequentially overlapped in the gate dielectric layer on 101 surface of semiconductor substrate
110 and second polysilicon gate 111.In the embodiment of the present invention, the gate dielectric layer 110 is oxide layer.
Dielectric layer 105 is isolated between having the first grid in isolation between the second grid structure and the first grid structure；Institute
State the first side that isolation 105 autoregistration of dielectric layer between the first grid is formed in the first grid structure, the second grid knot
Structure autoregistration is formed in the first side of isolation dielectric layer 105 between the first grid.Namely the selection of the embodiment of the present invention
Managing the corresponding second grid structure is formed using self-registered technology, does not need to use lithographic definition, therefore can be by described
The size reduction of two gate structures.It is oxide layer that dielectric layer 105 is isolated in the embodiment of the present invention, between the first grid.
Two adjacent cellular constructions form a cellular construction and combine, in the cellular construction combination, described in two
The second side of the first grid structure of cellular construction is adjacent, the first grid structure of two cellular constructions
Region between first side is defined by first window 202；It please refers to shown in subsequent figure 3B, the first window 202 is by second
201 photoetching of silicon nitride layer is unfolded into, and first top silicon oxide layer, 104 autoregistration of two cellular constructions is formed in
Two medial surfaces of the first window 202；The second side of first polysilicon gate 103 is by corresponding first top
The second side autoregistration of silicon oxide layer 104 defines；The first side of first polysilicon gate 103 is by corresponding described first
The first side autoregistration of top silicon oxide layer 104 defines, and second silicon nitride layer 201 outside the first window 202 exists
It is removed before the first side definition of first polysilicon gate 103.
Filled with isolating oxide layer 107 between second gate in region between the second side of the first grid structure,
Shape before second silicon nitride layer 201 removal of the isolating oxide layer 107 outside the first window 202 between the second gate
At.
First source-drain area, 109 autoregistration is formed in the lining of the semiconductor between the second side of the first grid structure
In bottom 101, and first source-drain area 109 is that two cellular constructions in cellular construction combination share, described the
Autoregistration is formed one source-drain area 109 before the formation of isolating oxide layer 107 between the second gate.
Second source-drain area 114 is formed in the semiconductor substrate outside the first side of the corresponding second grid structure
In 101 and the first side autoregistration of second source-drain area 114 and the corresponding second grid structure.
In the embodiment of the present invention, first source-drain area 109 and second source-drain area 114 all by N+ district's groups at.
The first side wall 106 is formed in the second side of the first grid structure；The of the second grid structure
One side is formed with the second side wall 112.In the embodiment of the present invention, the material of first side wall 106 and second side wall 112
It can be silicon nitride or silica.
The first lightly doped drain 108, first lightly doped drain 108 are also formed in first source-drain area 109
The two sides second side autoregistration with corresponding first polysilicon gate 103 respectively；The two sides of first source-drain area 109
Respectively with 106 autoregistration of the first side wall of the second side of corresponding first polysilicon gate 103.
The second lightly doped drain 113, second lightly doped drain 113 are also formed in second source-drain area 114
With the first side autoregistration of corresponding second polysilicon gate 111；Second source-drain area 114 and corresponding described second
The first side autoregistration of side wall 112.
On the surface of first source-drain area 109, second source-drain area 114 and second polysilicon gate 111 from right
Standard is formed with metal silicide 115.
The contact hole 117 for drawing first source-drain area 109 is formed at the top of first source-drain area 109, in institute
The top for stating the second source-drain area 114 is formed with the contact hole 117 for drawing second source-drain area 114, and each contact hole 117 is all
Across interlayer film 116.
In the cellular construction of SONOS non-volatility memorizer of the embodiment of the present invention, the first grid structure of storage tube is by leading to
Cross 104 autoregistration of the first top silicon oxide layer definition that autoregistration is formed in the inside area of first window 202, first grid interval
It is all that autoregistration is formed in the first side of corresponding first grid structure and the second grid knot of selecting pipe from dielectric layer 105
Structure autoregistration is formed in the first side of isolation dielectric layer 105 between the first grid, so, the grid of storage tube of the invention and selecting pipe
Pole structure is all formed using self-registered technology namely the size of storage tube of the invention and selecting pipe is defined using autoregistration
It realizes, does not need additional lithographic definition, the size of cellular construction can be made to accomplish minimum, so as to effectively reduce storage unit knot
The area of structure.
In addition, being compared with existing device shown in FIG. 1, in first source in device of the embodiment of the present invention shown in Fig. 2
The top in drain region 109 does not need to form conductive polysilicon layer, and is directly formed contact hole 1117 and draws first source and drain
Area 109, therefore the mode of operation of the storage tube of the last embodiment of the present invention is different with existing structure shown in FIG. 1.
In addition, in the embodiment of the present invention, isolating oxide layer 107 between the top second gate of first source-drain area 109
It is all silica with the interlayer film 116, after the contact hole 117 at the top of first source-drain area 109 carries out lithographic definition, directly
The opening of the isolating oxide layer 107 between the interlayer film 116 and the second gate can be formed by tapping into row oxide etch, it
Filling metal forms the contact hole 117 in the opening again afterwards, so the top of the first source-drain area 109 described in the embodiment of the present invention
The etching technics of the opening of the contact hole 117 in portion once can etch to be formed, and etching technics is simple.
It is the device junction composition in each step of present invention method as shown in Fig. 3 A to Fig. 3 Q, the present invention is implemented
The cellular construction of the SONOS non-volatility memorizer of the manufacturing method of example SONOS non-volatility memorizer includes a storage tube
With a selecting pipe；Include the following steps：
Step 1: as shown in Figure 3A, sequentially forming ONO layer 102, the first polysilicon layer 103 on 101 surface of semiconductor substrate
With the second silicon nitride layer 201.In present invention method, first polysilicon layer 103 with a thickness ofDescribed
Nitride silicon layer 201 with a thickness of
In present invention method, p-well, the formation of ONO layer 102 are formed on 101 surface of semiconductor substrate
In on the p-well surface.
Step 2: as shown in Figure 3B, carrying out chemical wet etching to second silicon nitride layer 201 and forming first window 202.
Step 3: as shown in Figure 3 C, carrying out growth of silicon oxide and forming silicon oxide layer 104；As shown in Figure 3D, silica is carried out
Comprehensive etching technics the first window 202 two medial surfaces formed the first top silicon oxide layer 104.
Step 4: as shown in Figure 3D, to first polysilicon layer between two first top silicon oxide layers 104
103 carry out the second side that etching for the first time forms the first polysilicon gate 103 of the two neighboring storage tube.
The first grid structure of the storage tube of each cellular construction includes being sequentially overlapped in 101 table of semiconductor substrate
The ONO layer 102 in face, the first polysilicon gate 103 and the first top silicon oxide layer 104；Two adjacent cellular construction compositions one
The combination of a cellular construction, the second side of the first grid structure of two cellular constructions is adjacent and the first grid structure
Second side by the of the second side of first polysilicon gate 103 and first top silicon oxide layer 104 at top
Two side faces are formed by stacking.
As shown in FIGURE 3 E, it carries out first time lightly doped drain to inject to form the first lightly doped drain 108, described first is lightly doped
The second side autoregistration with corresponding first polysilicon gate 103 respectively of the two sides in drain region 108,
As shown in FIGURE 3 E, first is formed in the second side of the first grid structure using deposit plus comprehensive etching technics
Side wall 106.In present invention method, the deposition thickness of first side wall 106 isFirst side wall 106
Material includes silicon nitride.
Step 5: as illustrated in Figure 3 F, two that first time source and drain is infused in the cellular construction combination described the are carried out
The first source-drain area 109 of autoregistration formation in the semiconductor substrate 101 between the second side of one gate structure, described first
The second side autoregistration of source-drain area 109 and corresponding first side wall 106, first lightly doped drain 108 and described
First source-drain area 109 is superimposed.First source-drain area 109 is that two cellular constructions in cellular construction combination are total
With.
Step 6: as shown in Figure 3 G, filling second gate in the region between the second side of the first grid structure
Between isolating oxide layer 107.Form described the be filled up completely in the region between the second side of the first grid structure
Isolating oxide layer 107, which generallys use to deposit, between two grid adds flatening process, and in present invention method, deposition thickness is firstThe second gate between isolating oxide layer 107, at this moment between the second gate isolating oxide layer 107 can be filled up completely it is described
Region between the second side of first grid structure simultaneously extends to outside region；Use flatening process by the first grid later
Second isolating oxide layer 107 removal outside region between the second side of pole structure, makes second isolating oxide layer
107 are only filled in the region between the second side of the first grid structure.
Step 7: as shown in figure 3h, removing second silicon nitride layer 201 and exposing each first top silicon oxide layer
104 first side.
Step 8: as shown in fig. 31, second of etching is carried out to first polysilicon layer 103 and forms corresponding described deposit
Store up the first side of first polysilicon gate 103 of pipe, the first side of first polysilicon gate 103 and first top
The first side autoregistration of portion's silicon oxide layer 104 and together superposition form the first side of the first grid structure.
Step 9: as shown in fig. 31, forming dielectric layer 105 using deposit；Later, as shown in figure 3j, to dielectric layer 105 into
Dielectric layer 105 is isolated between the first side of the first grid structure forms the first grid in the comprehensive etching technics autoregistration of row,
That is corresponding to spacer medium between the first grid for the first side for being only remained in the first grid structure after etching comprehensively in Fig. 3 J
Layer 105, the dielectric layer 105 outside the first side of the first grid structure are all removed.Meanwhile the corresponding comprehensive etching of Fig. 3 J
Technique also removes the ONO layer 102 being isolated outside 105 first side of dielectric layer between the first grid.Embodiment of the present invention side
In method, between the first grid be isolated dielectric layer 105 be silica, the dielectric layer 105 of deposit with a thickness of
Step 10: forming gate dielectric layer 110 as shown in Fig. 3 K；As shown in figure 3l, the second polysilicon layer 111 is formed；Such as figure
Shown in 3M, the first side autoregistration of dielectric layer 105 is isolated between the first grid and forms for the comprehensive etching for carrying out polysilicon
Two polysilicon gates 111, the second grid structure of the selecting pipe include being sequentially overlapped in the institute on 101 surface of semiconductor substrate
State gate dielectric layer 110 and second polysilicon gate 111.It is found that second polysilicon gate 111 uses completely as shown in Fig. 3 M
Self-registered technology definition, does not need to use lithographic definition, therefore present invention method can reduce second polysilicon gate 111
Size.
In present invention method, the gate dielectric layer 110 is oxide layer.
As shown in Fig. 3 N, carries out second of lightly doped drain and inject to form the second lightly doped drain 113, described second is lightly doped
The first side autoregistration in drain region 113 and corresponding second polysilicon gate 111.
As shown in Fig. 3 O, second is formed in the first side of the second grid structure using deposit plus comprehensive etching technics
Side wall 112.The material of second side wall 112 includes silicon nitride.
Step 11:, using the first side of the second grid structure as autoregistration boundary, carrying out second as shown in Fig. 3 P
The second source is formed in the semiconductor substrate 101 that secondary source and drain is infused in outside the first side of the corresponding second grid structure
Drain region 114.The first side autoregistration of second source-drain area 114 and corresponding second side wall 112, described second gently mixes
Miscellaneous drain region 113 and second source-drain area 114 are superimposed.
In present invention method, first source-drain area 109 and second source-drain area 114 all by N+ district's groups at.
First lightly doped drain 108 and second lightly doped drain 113 are all lightly doped for N-type.
Step 12: as shown in Fig. 3 P, in first source-drain area 109, second source-drain area 114 and described more than second
The surface autoregistration of crystal silicon grid 111 forms metal silicide 115.
As shown in Fig. 3 Q, interlayer film 116 is formed.
As shown in Fig. 2, contact hole 117, the contact hole 117 passes through the interlayer film 116, in first source-drain area
109 top and the top of second source-drain area 114 are all respectively formed with corresponding contact hole 117.
In present invention method, 107 He of isolating oxide layer between the top second gate of first source-drain area 109
The interlayer film 116 is all silica, after the contact hole 117 at the top of first source-drain area 109 carries out lithographic definition, directly
The opening of the isolating oxide layer 107 between the interlayer film 116 and the second gate can be formed by carrying out oxide etch, later
Filling metal forms the contact hole 117 in the opening again, so the top of the first source-drain area 109 described in the embodiment of the present invention
The etching technics of opening of contact hole 117 once can etch to be formed, etching technics is simple.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of SONOS non-volatility memorizer, which is characterized in that the cellular construction of SONOS non-volatility memorizer includes one
A storage tube and a selecting pipe；
The first grid structure of the storage tube includes being sequentially overlapped the ONO layer in semiconductor substrate surface, the first polysilicon gate
With the first top silicon oxide layer；
The second grid structure of the selecting pipe includes the gate dielectric layer and second being sequentially overlapped in the semiconductor substrate surface
Polysilicon gate；
Dielectric layer is isolated between having the first grid in isolation between the second grid structure and the first grid structure；The first grid
Between isolation dielectric layer autoregistration be formed in the first side of the first grid structure, the second grid structure self-aligning is formed
The first side of dielectric layer is isolated between the first grid；
Two adjacent cellular constructions form a cellular construction and combine, in the cellular construction combination, two units
The second side of the first grid structure of structure is adjacent, and the first of the first grid structure of two cellular constructions
Region between side is defined by first window；The first window is unfolded by the second silicon nitride layer photoetching, described in two
The first top silicon oxide layer autoregistration of cellular construction is formed in two medial surfaces of the first window；More than described first
The second side of crystal silicon grid is defined by the second side autoregistration of corresponding first top silicon oxide layer；First polycrystalline
The first side of Si-gate is defined by the first side autoregistration of corresponding first top silicon oxide layer, outside the first window
Second silicon nitride layer first polysilicon gate first side definition before be removed；
Filled with isolating oxide layer between second gate in region between the second side of the first grid structure, described second
It is formed before second silicon nitride layer removal of the isolating oxide layer outside the first window between grid；
First source-drain area autoregistration is formed in the semiconductor substrate between the second side of the first grid structure, and
First source-drain area is that two cellular constructions in cellular construction combination share, and first source-drain area is described
Autoregistration is formed before isolating oxide layer is formed between second gate；
Second source-drain area is formed in the semiconductor substrate outside the first side of the corresponding second grid structure and described
The first side autoregistration of second source-drain area and the corresponding second grid structure.
2. SONOS non-volatility memorizer as described in claim 1, it is characterised in that：The semiconductor substrate is silicon substrate.
3. SONOS non-volatility memorizer as claimed in claim 2, it is characterised in that：In the semiconductor substrate surface shape
At there is p-well, the first grid structure and the second grid structure are formed on the p-well surface, first source and drain
Area and second source-drain area all by N+ district's groups at.
4. SONOS non-volatility memorizer as claimed in claim 2, it is characterised in that：The gate dielectric layer is oxide layer；Institute
Isolation dielectric layer is oxide layer between stating the first grid.
5. SONOS non-volatility memorizer as claimed in claim 2, it is characterised in that：The of the first grid structure
Two side faces are formed with the first side wall；The second side wall is formed in the first side of the second grid structure.
6. SONOS non-volatility memorizer as claimed in claim 5, it is characterised in that：Shape is gone back in first source-drain area
At there is the first lightly doped drain, the two sides of first lightly doped drain respectively with corresponding first polysilicon gate second
Side autoregistration；The two sides of first source-drain area respectively with the second side of corresponding first polysilicon gate described
One side wall autoregistration；
The second lightly doped drain, second lightly doped drain and corresponding described are also formed in second source-drain area
The first side autoregistration of two polysilicon gates；The first side of second source-drain area and corresponding second side wall is from right
It is quasi-.
7. SONOS non-volatility memorizer as claimed in claim 6, it is characterised in that：In first source-drain area, described
The surface autoregistration of two source-drain areas and second polysilicon gate is formed with metal silicide.
8. SONOS non-volatility memorizer as described in claim 1, it is characterised in that：At the top of first source-drain area
It is formed with the contact hole for drawing first source-drain area, is formed at the top of second source-drain area and draws second source and drain
The contact hole in area, each contact hole all pass through interlayer film.
9. a kind of manufacturing method of SONOS non-volatility memorizer, the cellular construction of SONOS non-volatility memorizer includes one
Storage tube and a selecting pipe；It is characterised in that it includes following steps：
Step 1: sequentially forming ONO layer, the first polysilicon layer and the second silicon nitride layer in semiconductor substrate surface；
Step 2: carrying out chemical wet etching to second silicon nitride layer forms first window；
Step 3: forming the first top in two medial surfaces of the first window using growth of silicon oxide and comprehensive etching technics
Silicon oxide layer；
It is formed Step 4: carrying out etching for the first time to first polysilicon layer between two first top silicon oxide layers
The second side of first polysilicon gate of the two neighboring storage tube；
The first grid structure of the storage tube of each cellular construction includes the ONO being sequentially overlapped in semiconductor substrate surface
Layer, the first polysilicon gate and the first top silicon oxide layer；Two adjacent cellular constructions form a cellular construction and combine, and two
The second side of the first grid structure of a cellular construction is adjacent and the second side of the first grid structure is by described
The second side of first top silicon oxide layer of the second side and top of first polysilicon gate is formed by stacking；
Step 5: carrying out the second of two first grid structures that first time source and drain is infused in the cellular construction combination
Autoregistration forms the first source-drain area in the semiconductor substrate between side, and first source-drain area is the cellular construction group
Two cellular constructions in conjunction share；
Step 6: filling isolating oxide layer between second gate in region between the second side of the first grid structure；
Step 7: removing second silicon nitride layer and exposing the first side of each first top silicon oxide layer；
Step 8: carrying out first polycrystalline that second of etching forms the corresponding storage tube to first polysilicon layer
The first side of the first side of Si-gate, the first side of first polysilicon gate and first top silicon oxide layer is from right
Standard and together superposition form the first side of the first grid structure；
Step 9: forming the first grid in the first side of the first grid structure using deposit plus comprehensive etching technics autoregistration
Between be isolated dielectric layer and by between the first grid be isolated dielectric layer first side outside the ONO layer remove；
Step 10: sequentially forming gate dielectric layer and the second polysilicon layer, comprehensive etching of polysilicon is carried out between the first grid
The first side autoregistration of spacer medium layer forms the second polysilicon gate, and the second grid structure of the selecting pipe includes successively folding
It is added on the gate dielectric layer and second polysilicon gate of the semiconductor substrate surface；
Step 11: using the first side of the second grid structure as autoregistration boundary, carries out second of source and drain and be infused in pair
The second source-drain area is formed in the semiconductor substrate outside the first side for the second grid structure answered；
Step 12: forming interlayer film and contact hole, the contact hole passes through the interlayer film, on the top of first source-drain area
Portion and the top of second source-drain area are all respectively formed with corresponding contact hole.
10. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 9, it is characterised in that：In the semiconductor
Substrate surface is formed with p-well, and the first grid structure and the second grid structure are formed on the p-well surface, institute
State the first source-drain area and second source-drain area all by N+ district's groups at.
11. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 9, it is characterised in that：The gate dielectric layer
For oxide layer；It is oxide layer that dielectric layer is isolated between the first grid.
12. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 9, it is characterised in that：
It further include being added entirely using deposit after the second side side formation of first polysilicon gate of storage tube described in step 4
Face etching technics is the step of the second side of the first grid structure forms the first side wall；
It further includes using deposit plus comprehensive etching technics in the second gate that second polysilicon gate is formed in step 10 later
The first side of pole structure forms the step of the second side wall.
13. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 12, it is characterised in that：
It further include carrying out first time lightly doped drain to inject to form the first lightly doped drain before forming first side wall in step 4
The step of area, the two sides of first lightly doped drain are respectively with the second side of corresponding first polysilicon gate from right
Standard, the second side autoregistration of first source-drain area and corresponding first side wall in subsequent step five, described first
Lightly doped drain and first source-drain area are superimposed；
It is formed in step 10 before second side wall, further includes carrying out second of lightly doped drain to inject to form second and be lightly doped
The step of drain region, the first side autoregistration of second lightly doped drain and corresponding second polysilicon gate；Subsequent step
The first side autoregistration of second source-drain area and corresponding second side wall in rapid 11, second lightly doped drain
Area and second source-drain area are superimposed.
14. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 12, it is characterised in that：Step 10 dimorphism
Before the interlayer film, further include：In first source-drain area, the table of second source-drain area and second polysilicon gate
Face autoregistration forms metal silicide.
15. the manufacturing method of SONOS non-volatility memorizer as claimed in claim 12, it is characterised in that：First side
The material of wall includes silicon nitride；The material of second side wall includes silicon nitride.
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