CN108878526A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, on which fins are provided, and fin gaps are formed between adjacent fins; a hard mask is provided above the fins; An anti-penetration layer is formed above the mask, and there are anti-penetration ions in the anti-penetration layer; an anti-diffusion layer is formed, the height of the anti-diffusion layer is lower than the height of the fins, and an anti-diffusion layer is injected into the gap of the fins ions, the anti-diffusion ions can prevent the anti-puncture ions from diffusing to the top of the fin; remove the hard mask; perform annealing.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the improvement of the integration level of semiconductor devices, the critical dimensions of transistors are continuously reduced. The reduction of critical dimensions means that more transistors can be arranged on a chip, thereby improving the performance of devices. However, as the size of the transistor decreases sharply, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short channel effect, thereby increasing the channel leakage current of the transistor.

The gate of the Fin Field-Effect Transistor (FinFET) has a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewall of the fin, so that the inversion layer is formed on each side of the channel, which can control the connection of the circuit on multiple sides of the fin. with disconnect. This design can increase the control of the gate to the channel region, so that the short channel effect of the transistor can be well suppressed. However, FinFETs still suffer from short-channel effects.

In order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. One method is to reduce the possibility of drain-source punch-through and reduce the short-channel effect by performing anti-penetration implantation on the bottom of the fin.

However, the method of forming the semiconductor structure easily affects the performance of the formed semiconductor structure.

Contents of the invention

The problem solved by the present invention is to provide a semiconductor and its forming method, which can improve the performance of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which fins are arranged, and there are fin gaps between adjacent fins; A hard mask; an anti-penetration layer is formed above the hard mask, and there are anti-penetration ions in the anti-penetration layer; an anti-diffusion layer is formed, the height of the anti-diffusion layer is lower than the height of the fins, Implanting anti-diffusion ions into the gaps of the fins, the anti-diffusion ions can prevent the diffusion of the anti-puncture ions to the top of the fins; remove the hard mask; perform annealing.

Optionally, the annealing temperature is greater than or equal to 850°C.

Optionally, the ions implanted into the anti-diffusion layer are one or more combinations of carbon ions, germanium ions and nitrogen ions.

Optionally, a protective layer is formed above the anti-puncture layer, and the protective layer prevents the upward diffusion of the anti-puncture ions.

Optionally, the protective layer is made of one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN.

Optionally, the anti-penetration layer covers the fin gap.

Optionally, forming the anti-diffusion layer includes: forming an initial anti-diffusion layer, the initial anti-diffusion layer covers the entire fin, and the initial anti-diffusion layer is formed by a fluid chemical vapor deposition process; An annealing process, the temperature of the first annealing process is 400°C-650°C; performing thermal ion implantation on the initial anti-diffusion layer, the temperature of the thermal ion implantation process is 450°C-500°C; etching the initial anti-diffusion layer The diffusion layer is made to have a height lower than that of the fins, forming an anti-diffusion layer.

Optionally, after performing thermal ion implantation, a second annealing process is performed on the initial diffusion prevention layer, and the temperature of the second annealing process is 500°C-700°C.

Optionally, in the thermal ion implantation process, the implanted ions are He.

Optionally, the energy of the thermionic implantation is 1-50Kev, and the implantation dose is 1.0e14-1.0e19atm/cm ² .

Optionally, after the anti-diffusion layer is formed, the anti-penetration layer and the protective layer are etched so that the heights of the anti-penetration layer and the protective layer are equal to the anti-diffusion layer.

Optionally, after the hard mask is set, an oxide layer is covered on the hard mask, and the oxide layer is removed before forming the punch-through prevention layer.

Optionally, the substrate includes a first transistor region and a second transistor region, and the doping type of the anti-puncture ion is opposite to the doping type of the transistor in the corresponding region.

Optionally, the first transistor region is an NMOS transistor, and the ion doping type for preventing punch-through in the first transistor region is P-type.

Optionally, the anti-puncture layer is only formed in the first transistor region.

Optionally, the anti-puncture layer ions in the first transistor region are boron ions or boron fluoride ions.

The present invention also includes a semiconductor structure formed by any one of the above methods.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the semiconductor forming method of the present invention, an anti-penetration layer is formed, which can prevent or reduce the penetration between the source region and the drain region, thereby reducing the leakage current;

Further, an anti-diffusion layer and a protective layer are arranged next to the anti-puncture layer, the protective layer can prevent the anti-puncture ions from diffusing to the outside, and the anti-diffusion layer can reduce the anti-puncture ions that diffuse into the channel of the transistor.

Further, the anti-diffusion ions are formed in the anti-diffusion layer in the gap between adjacent fins, making the process more convenient, and effectively preventing the ions in the anti-penetration layer from diffusing to the top of the fin.

Further, the example of the present invention adopts a three-step process to prepare the anti-diffusion layer, combined with annealing, thermal ion implantation and other processes, the introduction of thermal ion implantation process reduces the temperature of FCVD oxide densification, so that the quality of the formed diffusion layer is higher.

Description of drawings

1-3 are structural schematic diagrams of each step of a method for forming a semiconductor structure.

4-13 are structural schematic diagrams of each step of an embodiment of a method for forming a semiconductor structure according to the present invention.

FIG. 14 is a schematic diagram of the steps of forming the semiconductor structure of the present invention.

Detailed ways

The wafer test structure of the present invention will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the beneficial effects of the present invention . Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

There are many problems in the formation method of the semiconductor structure, and it is difficult to guarantee the stable performance of the formed semiconductor structure.

After research, it is found that as the size of the fin used to form the fin field effect transistor continues to shrink, the bottom of the source region and the drain region formed in the fin is prone to bottom punch through (punch through), that is, the source region and the drain region. A short circuit occurs between the bottoms, generating a leakage current at the bottoms of the source and drain regions. In order to overcome the bottom punch-through phenomenon, one method is to implant anti-type ions in the region between the bottom of the source region and the drain region to isolate the bottom of the source region and the drain region.

1 to 3 are structural schematic diagrams of various steps in a method for forming a semiconductor structure.

Referring to FIG. 1 , a substrate is provided, and a fin 101 and a hard mask 110 on top of the fin 101 are disposed on the substrate 100 . The substrate includes: a first transistor region A and a second transistor region B.

Continuing to refer to FIG. 1 , an anti-penetration layer 102 is formed on the substrate 100 , the surface of the anti-penetration layer 102 is lower than the top surface of the fin portion 101 .

Referring to FIG. 2 , ion implantation is performed on the anti-puncture layer 102 , and the anti-puncture ions are implanted.

Please refer to FIG. 3 , after the anti-puncture ions are implanted, an annealing treatment is performed to diffuse the anti-puncture ions into the bottom of the fin 101 .

Wherein, during the annealing process, the anti-puncture ions are easy to diffuse to the top of the fin portion 101 , thus causing the threshold voltage of the subsequently formed transistor to increase, thereby affecting the performance of the transistor.

In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which fins are arranged, and there are fin gaps between adjacent fins; A hard mask is arranged above the hard mask; an anti-penetration layer is formed above the hard mask, and there are anti-penetration ions in the anti-penetration layer; an anti-diffusion layer is formed, and the height of the anti-diffusion layer is lower than the height of the fins , implanting anti-diffusion ions into the gap of the fin, the anti-diffusion ions can prevent the diffusion of the anti-puncture ions to the top of the fin; removing the hard mask; performing annealing.

Wherein, in the forming method of the semiconductor structure of the present invention, before performing the annealing treatment, an anti-diffusion layer is formed, and anti-diffusion ions are implanted into the gap between adjacent fins, that is, the anti-diffusion layer and the anti-penetration layer. The ions are located on the top of the anti-diffusion layer and the anti-penetration layer. At the same time, due to the doping characteristics, the doping concentration gradually decreases from the doping source of the anti-diffusion ions outward, so the anti-diffusion ions also exist in the fins, and the anti-diffusion ions The ions in the anti-penetration layer can be prevented from diffusing to the top of the fin, so that the anti-penetration ions diffusing into the channel of the transistor can be reduced. Therefore, the method for forming the semiconductor structure can reduce the impact of the anti-puncture ions on the threshold voltage of the formed transistor, thereby improving the performance of the formed semiconductor structure. In addition, since the anti-diffusion ions are formed in the anti-diffusion layer, the process operation is more convenient, and at the same time, the ions in the anti-penetration layer are effectively prevented from diffusing to the top of the fin.

In addition, the anti-puncture layer of the present invention has anti-puncture ions, which can prevent or reduce the breakthrough of the source region and the drain region in the semiconductor structure, thereby reducing the leakage current.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 13 are structural schematic diagrams of each step in an embodiment of a method for forming a semiconductor structure of the present invention.

In this embodiment, the substrate includes: a first transistor region A and a second transistor region B. In other embodiments, the substrate may also only include the first transistor region or the second transistor region.

In this embodiment, the first transistor region A is used to form an NMOS transistor; the second transistor region B is used to form a PMOS. In other embodiments, the first transistor region can also be used to form a PMOS transistor; the second transistor region is used to form an NMOS.

Referring to FIG. 4 , the substrate further includes: a hard mask 204 located on the top of the fin 202 , and the hard mask 204 can protect the top of the fin 202 from implanting anti-puncture in the subsequent anti-puncture ion implantation process. ions, thereby reducing the impact of anti-puncture ion implantation on transistor performance.

In one embodiment of the present invention, the step of forming the substrate includes: providing an initial substrate; forming a patterned hard mask 204 on the initial substrate; using the hard mask 204 as a mask, patterning The initial substrate forms a substrate 200 and a fin 202 on the substrate 200, and the fin 202 is used to form a transistor channel.

Optionally, after the hard mask is set, an oxide layer 203 is covered on the hard mask 204 , and the oxide layer 203 covers the hard mask 204 , the fins 202 and the fin gaps 20 . The material of the oxide layer 203 may be SiO ₂ . The oxide layer 203 is subsequently removed before the formation of the anti-puncture layer.

Please refer to FIG. 5, the oxide layer 203 is removed, and an anti-puncture layer 205 is formed. The anti-puncture layer 205 has anti-puncture ions in it. The anti-puncture layer covers the fins and the gaps between the fins, and is used to prevent the semiconductor structure from The source and drain regions are punched through, thereby reducing the leakage current.

Referring to FIG. 6 , in one embodiment of the present invention, the substrate includes a first transistor region A and a second transistor region B. Referring to FIG. Optionally, the first transistor region A is an NMOS transistor, and the second transistor region B is a PMOS transistor. The doping type of the anti-punching ion is opposite to the doping type of the transistor in the corresponding region. Optionally, the punch-through preventing ions in the first transistor region are P-type ions, such as boron ions or boron fluoride ions, and the punch-through preventing ions in the second transistor region are N-type ions, such as phosphorus ions or arsenic ions.

Optionally, the anti-puncture layer is only provided in the region A of the first transistor region. Specifically, on the basis of the process in FIG. 5 , the part of the anti-puncture layer in the second transistor region B is etched away, and only the part of the anti-puncture layer in the first transistor region A remains. Alternatively, in the process step of depositing the punch-through prevention layer, a mask is used to block the second transistor region B, so that the punch-through prevention layer is only formed on the part of the punch-through prevention layer in the first transistor region A. This setting is because compared with PMOS transistors, NMOS transistors have more severe loss of dopant ions (eg, B ions), and thus are more likely to suffer from current breakthrough.

Optionally, in an embodiment of the present invention, the substrate includes a first transistor region A and a second transistor region B. The first anti-punching ion implantation is performed on the first transistor region A, and the second anti-punching ion implantation is performed on the second transistor region B. In other embodiments, when the substrate only includes the first transistor region or the second transistor region, the step of anti-puncture ion implantation only includes: performing the first anti-puncture ion implantation on the first transistor region, or The second transistor region is subjected to second anti-puncture ion implantation.

If the thickness of the anti-penetration layer 205 is too large, material waste is likely to occur; if the thickness of the anti-penetration layer 205 is too small, it is difficult to fully prevent the source-drain breakthrough of the formed transistor. Therefore, in this embodiment, the thickness of the through layer 205 is 20 angstroms to 60 angstroms.

In this embodiment, if the concentration of the punch-through ions in the punch-through prevention layer 205 is too high, the punch-through prevention ions will easily diffuse through the diffusion prevention layer to the top of the fin 202, thereby easily affecting the performance of the formed transistor; if the punch-through prevention The concentration of the anti-puncture ions in the layer 205 is too low, and it is difficult to prevent source-drain breakthrough of the formed transistor. Therefore, in this embodiment, the concentration of anti-puncture ions in the anti-puncture layer 205 is 1.0E13 atoms/cm ² -1.0E15 atoms/cm ² .

In this embodiment, the technological parameters of the anti-puncture ion implantation include: the implantation dose is 1.0E13 atoms/cm ² -1.0E15 atoms/cm ² ; the implantation energy is 5KeV-100KeV.

Please refer to FIG. 7 , in one embodiment of the present invention, a protective layer 206 is formed above the anti-puncture layer 205, and the protective layer 205 prevents the anti-puncture ions in the anti-puncture layer 205 from diffusing upward during annealing. . Since the purpose of the anti-puncture layer 205 is to prevent the source region and the drain region in the semiconductor device from being penetrated, this purpose cannot be achieved if the anti-puncture ions diffuse upwards. Therefore, the protective layer 205 is provided to prevent the upward diffusion of the anti-puncture ions. Optionally, the protective layer is made of one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN.

Please refer to FIG. 8 , in one embodiment of the present invention, an initial anti-diffusion layer 208 is formed, and the initial anti-diffusion layer 208 covers the entire fin portion 202, that is, covers the top and side surfaces of the fin portion, and the initial anti-diffusion layer 208 The material can be silicon dioxide, and the initial anti-diffusion layer 208 can be formed by a fluid chemical vapor deposition (FCVD) process. Compared with other deposition processes, the fluid chemical vapor deposition material uses a polymer material as a carrier, and has good fluidity and filling capacity. good.

Subsequently, a first annealing process is performed on the initial anti-diffusion layer 208. The temperature of the first annealing process is 400°C-650°C. The first annealing process is mainly to volatilize the polymer material. In the first annealing process, Si-O bonds are gradually formed. Subsequently, thermal ion implantation is performed on the initial anti-diffusion layer 208, and the temperature of the thermal ion implantation process is 450°C-500°C. Since the material also contains a large amount of water, there are hydrogen bonds between water molecules. The purpose of this thermal ion implantation is to use the stress of the implanted ions to break the redundant hydrogen bonds. Optionally, the ion implanted in the thermal ion implantation process is He, the implantation energy is 1-50Kev, and the implantation dose is 1.0e14-1.0e19atm/cm ² . Optionally, a second annealing process may be performed on the initial anti-diffusion layer 208, the temperature of the second annealing process is 500° C.-700° C. to remove H ions therein, and simultaneously cure the formed initial anti-diffusion layer;

Finally, the initial anti-diffusion layer 208 is etched to make its height lower than that of the fins to form an anti-diffusion layer 207 (as shown in FIG. 9 ). In this embodiment, a three-step process is used to prepare the anti-diffusion layer, combined with annealing, thermal ion implantation and other processes, and the introduction of the thermal ion implantation process reduces the densification temperature of the FCVD oxide, so that the quality of the formed diffusion layer is higher.

In this embodiment, the materials of the initial diffusion prevention layer 208 and the diffusion prevention layer 207 may be silicon oxide or silicon oxynitride.

Referring to FIG. 10 , after the anti-diffusion layer 207 is formed, the anti-penetration layer 205 and the protective layer 206 are etched so that the heights of the anti-puncture layer 205 and the protective layer 206 are flush with the anti-diffusion layer.

Please refer to FIG. 11 , implant anti-diffusion ions into the fin gap 20, and the anti-diffusion ions can prevent the ions in the anti-penetration layer from diffusing to the top of the fin. Specifically, the anti-diffusion ions are implanted in the anti-diffusion layer 207. In the protective layer 206 and the anti-penetration layer 205, due to the doping characteristics, the doping concentration gradually decreases from the doping source point of the anti-diffusion ions to the outside, so the anti-diffusion ions also exist in the fins at the same time, for example, the anti-diffusion ions exist In the doped region 209 shown in FIG. 12 , the anti-diffusion ions can prevent the ions in the anti-puncture layer from diffusing to the top of the fin, thereby reducing the anti-puncture ions that diffuse into the channel of the transistor.

The element of the anti-diffusion ion is an element of the fourth main group or an atomic element that is not easily bonded to the fin atoms. The number of electrons in the outermost layer of the atoms of the fourth main group element is the same as that of the fin portion 202, so it is not easy to form many electrons in the fin portion 202, and therefore, it is not easy to change the conductivity of the fin portion 202. ; Atoms that are not easy to bond with fin atoms are not easily activated during the subsequent annealing process. Therefore, atoms that do not easily bond to fin atoms are also less likely to change the conductivity of the fin 202 . In addition, the anti-diffusion ions can enter the gaps formed by the atoms of the fins 202 , thereby preventing the anti-puncture ions from diffusing to the top of the fins 202 through the gaps, thereby improving the performance of the formed semiconductor structure.

Therefore, the anti-diffusion layer 207 can prevent the anti-puncture ions in the fin 202 from diffusing to the top of the fin 202 during the subsequent annealing process, thereby reducing the anti-puncture ions that diffuse into the channel of the transistor and reducing the anti-puncture ion pair. The effect of the threshold voltage of the formed transistor, thereby improving the performance of the formed semiconductor structure.

In this embodiment, the anti-diffusion ions include: one or more combinations of carbon ions, germanium ions and nitrogen ions. After the carbon ions, germanium ions and nitrogen ions enter the atomic gap of the fin 202 , they can prevent the anti-puncture ions from diffusing to the top of the fin 202 . In addition, nitrogen ions are not easy to be activated during the annealing process so as not to affect the conductivity of the fin portion 202 ; carbon and germanium are elements of the fourth main group, and are not easily activated during the annealing process to affect the conductivity of the fin portion 202 .

If the concentration of anti-diffusion ions in the anti-diffusion layer 207 is too high, it will easily affect the conductivity of the fin 202 and reduce the transistor performance; 202 top spread. Therefore, in this embodiment, the concentration of the anti-diffusion ions in the anti-diffusion layer 207 is 1.0E13 atoms/cm ² -1.0E16 atoms/cm ² .

In this embodiment, the process parameters of the anti-diffusion ion implantation include: the implantation energy is 1KeV-30KeV; the implantation dose is 1.0E13atoms/cm ² -1.0E16atoms/cm ² .

Referring to FIG. 13 , finally, the hard mask is removed and annealed for the semiconductor structure.

The annealing treatment is used to activate the anti-punching ions, so that the anti-punching ions can prevent source-drain punch-through. During the annealing process, the anti-diffusion ions in the anti-diffusion layer 207 can block the diffusion of the anti-puncture ions in the anti-puncture layer to the top of the fin 202, thereby reducing the impact of the anti-puncture ions on the formed transistor. influence, thereby improving the performance of semiconductor structures.

In this embodiment, the annealing temperature of the annealing treatment is greater than or equal to 850°C.

It should be noted that, in this embodiment, after performing the degradation treatment, the forming method further includes: forming a gate structure across the fin 202 , the gate structure covers a part of the sidewall of the fin 203 and top surface.

In this embodiment, the top of the anti-penetration layer is flush with the bottom of the anti-diffusion layer. In other embodiments, the top of the anti-penetration layer can also be lower than the bottom of the anti-diffusion layer, or the top of the anti-penetration layer is higher than the top of the anti-diffusion layer, and the bottom of the anti-penetration layer below the top of the diffusion barrier.

FIG. 14 is a schematic diagram of the steps of forming the semiconductor structure of the present invention.

The present invention also includes a semiconductor structure made by the above-mentioned semiconductor forming method.

In summary, in the semiconductor forming method of the present invention, an anti-penetration layer is formed, which can prevent or reduce the penetration between the source region and the drain region, thereby reducing the leakage current;

Further, an anti-diffusion layer and a protective layer are arranged next to the anti-puncture layer, the protective layer can prevent the anti-puncture ions from diffusing to the outside, and the anti-diffusion layer can reduce the anti-puncture ions that diffuse into the channel of the transistor.

Further, the anti-diffusion ions are formed in the anti-diffusion layer in the gap between adjacent fins, making the process more convenient, and effectively preventing the ions in the anti-penetration layer from diffusing to the top of the fin.

Further, the example of the present invention adopts a three-step process to prepare the anti-diffusion layer, combined with annealing, thermal ion implantation and other processes, the introduction of thermal ion implantation process reduces the temperature of FCVD oxide densification, so that the quality of the formed diffusion layer is higher.

Therefore, the method for forming a semiconductor structure can improve the performance of the formed semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A method for forming a semiconductor structure, comprising: providing a substrate, the substrate is provided with fins, and there is a fin gap between adjacent fins; placing a hard mask over the fins; An anti-penetration layer is formed above the hard mask, and there are anti-penetration ions in the anti-penetration layer; forming an anti-diffusion layer, the height of the anti-diffusion layer is lower than the height of the fins, and injecting anti-diffusion ions into the gaps of the fins, the anti-diffusion ions can prevent the anti-diffusion ions from diffusing to the top of the fins ; removing the hard mask; Annealed. 2. The method for forming a semiconductor structure according to claim 1, wherein the annealing temperature is greater than or equal to 850°C. 3. The method for forming a semiconductor structure according to claim 1, wherein the ions implanted into the anti-diffusion layer are one or more combinations of carbon ions, germanium ions and nitrogen ions. 4 . The method for forming a semiconductor structure according to claim 1 , wherein a protective layer is formed above the anti-puncture layer, and the protective layer prevents the upward diffusion of the anti-puncture ions. 5. The method for forming a semiconductor structure according to claim 4, wherein the protective layer is made of one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN. 6 . The method for forming a semiconductor structure according to claim 1 , wherein the anti-puncture layer covers the fin gap. 7. The method for forming a semiconductor structure according to claim 1, wherein forming an anti-diffusion layer comprises: forming an initial anti-diffusion layer, the initial anti-diffusion layer covers the entire fin, and the initial anti-diffusion layer is formed by a fluid chemical vapor deposition process; performing a first annealing process on the initial anti-diffusion layer, and the temperature of the first annealing process is 400°C-650°C; Performing thermal ion implantation on the initial anti-diffusion layer, the temperature of the thermal ion implantation process is 450°C-500°C; Etching the initial anti-diffusion layer to make its height lower than that of the fins to form an anti-diffusion layer. 8. The method for forming a semiconductor structure according to claim 7, wherein after performing thermal ion implantation, a second annealing process is performed on the initial diffusion prevention layer, and the temperature of the second annealing process is 500°C- 700°C. 9. The method for forming a semiconductor structure according to claim 6, wherein in the thermal ion implantation process, the implanted ions are He. 10 . The method for forming a semiconductor structure according to claim 6 , wherein the energy of the thermionic implantation is 1-50Kev, and the implantation dose is 1.0e14-1.0e19atm/cm ² . 11. The method for forming a semiconductor structure according to claim 4, wherein after forming the anti-diffusion layer, etching the anti-puncture layer and the protective layer, so that the heights of the anti-puncture layer and the protective layer are the same as The anti-diffusion layer is flush. 12 . The method for forming a semiconductor structure according to claim 1 , wherein after the hard mask is provided, an oxide layer is covered on the hard mask, and the oxide layer is removed before forming the punch-through prevention layer. 13 . 13. The method for forming a semiconductor structure according to claim 1, wherein the substrate includes a first transistor region and a second transistor region, and the doping type of the anti-puncture ion is the doping type of the transistor corresponding to the region. The type is reversed. 14 . The method for forming a semiconductor structure according to claim 13 , wherein the first transistor region is an NMOS transistor, and the ion doping type for preventing punch-through in the first transistor region is P-type. 15. The method for forming a semiconductor structure according to claim 13, wherein the anti-puncture layer is only formed in the first transistor region. 16 . The method for forming a semiconductor structure according to claim 14 , wherein the anti-puncture layer ions in the first transistor region are boron ions or boron fluoride ions. 17. A semiconductor structure formed by the method according to any one of claims 1-16.