CN108962751A - Preparation method of GaN HEMT device - Google Patents

Abstract

The invention discloses a preparation method of a GaN HEMT device, which comprises the following steps: providing a substrate; forming a device body on a substrate, wherein the device body sequentially comprises a first GaN layer, an AlGaN layer, a second GaN layer and a dielectric layer from bottom to top; forming a grid electrode recess in the device body, wherein the grid electrode recess penetrates through the dielectric layer and the second GaN layer and extends to the surface of the AlGaN layer; performing primary annealing on the device body with the grid electrode recess; performing surface treatment on the device body subjected to primary annealing by using nitrogen; forming a metal gate in the surface-treated gate recess; and carrying out secondary annealing on the device with the metal gate.

Description

Fabrication method of GaN HEMT device

technical field

Embodiments of the present invention relate to the field of semiconductors, in particular to a method for preparing a GaN HEMT device.

Background technique

High electron mobility transistors (HEMTs) are of great importance in high power and high frequency applications. In particular, aluminum gallium nitride (AlGaN)/gallium nitride (GaN) HEMT devices have outstanding advantages in terms of operating bandwidth, output power, operating efficiency, and radiation resistance, and have broad application prospects.

However, existing AlGaN/GaN HEMT devices face the problem of large surface leakage. Specifically, the reverse surface leakage current of the gate will lead to a decrease in the breakdown voltage and transconductance, which will reduce the output power of the device, and the cut-off frequency and maximum oscillation frequency will be reduced in terms of small signal characteristics. At the same time, due to the increase of leakage current on the opposite surface of the gate, the DC power consumption of the device itself will increase, resulting in high power loss and reduced efficiency.

Therefore, it is necessary to improve the surface leakage of GaN HEMT devices to improve the overall performance of the devices.

Contents of the invention

The embodiment of the present invention aims to provide a method for manufacturing a GaN HEMT device, so as to reduce device surface leakage.

According to one aspect of the present invention, a method for preparing a GaN HEMT device is proposed, including: providing a substrate; forming a device body on the substrate, and the device body sequentially includes a first GaN layer, an AlGaN layer, a second GaN layer and a dielectric layer; forming a gate recess in the device body, the gate recess passing through the dielectric layer, the second GaN layer and extending to the surface of the AlGaN layer; forming a gate recess The device body is annealed once; the device body that has been annealed once is subjected to surface treatment with nitrogen; the metal grid is formed in the grid recess after surface treatment; and the device with the metal grid is subjected to secondary annealing.

According to some embodiments, before forming the gate recess, a mask layer is provided on the dielectric layer, so that the gate recess is formed through the mask layer; and after one annealing and before surface treatment, the mask layer is removed

According to some embodiments, the temperature for one annealing is 400° C., and the time is 30˜60 s.

According to some embodiments, the time for surface treatment with nitrogen is 30-60 s.

According to some embodiments, the temperature for performing the secondary annealing is 450° C., and the time is 30˜60 s.

According to some embodiments, forming the metal gate includes depositing Ni/Au in the gate recess by electron beam evaporation.

According to some embodiments, forming the gate recess includes: photoetching the mask layer; etching the dielectric layer with SF ₆ gas; and etching the second GaN layer with BCl ₃ gas.

In the preparation method of the GaN HEMT device according to the embodiment of the present invention, an integrated process flow of primary annealing-nitrogen surface treatment-secondary annealing is designed, wherein the primary annealing and secondary annealing are respectively performed before and after forming the metal gate . Specifically, one-time annealing is beneficial to reduce gate leakage in the device and provide high-quality gate contact; surface treatment with nitrogen can supplement the surface Ga-N bond to reduce the impact of the etching process when forming gate recesses. Damage caused by the device; secondary annealing can be used to further reduce defects such as atomic dislocations on the device surface. Through such an integrated process, GaN HEMT devices with low surface leakage can be manufactured without increasing the cost, thereby improving the overall performance of the device.

Description of drawings

Other objects and advantages of the present invention will be apparent from the following description of the present invention with reference to the accompanying drawings, and may help to provide a comprehensive understanding of the present invention.

FIG. 1 shows a schematic diagram of the process of a method for manufacturing a GaN HEMT device according to an exemplary embodiment of the present invention; and

FIG. 2 shows a flow chart of the method for fabricating the GaN HEMT device of FIG. 1 .

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be noted that, in the drawings or descriptions of the specification, similar or identical parts all use the same figure numbers. Implementations not shown or described in the accompanying drawings are forms known to those of ordinary skill in the art. Additionally, while illustrations of parameters including particular values may be provided herein, it should be understood that the parameters need not be exactly equal to the corresponding values, but rather may approximate the corresponding values within acceptable error margins or design constraints. The directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the protection scope of the present invention.

FIG. 1 shows a schematic diagram of the process of a method for manufacturing a GaN HEMT device according to an exemplary embodiment of the present invention, and FIG. 2 shows a flowchart of the method for manufacturing a GaN HEMT device in FIG. 1 . Referring to Figure 1-2, the fabrication method of GaN HEMT devices includes:

S1, providing a substrate 1;

S2, forming a device body 2 on the substrate 1, the device body 2 sequentially includes a first GaN layer 21, an AlGaN layer 22, a second GaN layer 23 and a dielectric layer 24 in order from bottom to top;

S3, forming a gate recess 3 in the device body 2, the gate recess 3 passes through the dielectric layer 24, the second GaN layer 23 and extends to the surface of the AlGaN layer 22;

S4, performing an annealing A on the device body 2 formed with the gate recess 3;

S5, surface-treating the once-annealed device body ₂ with nitrogen N2;

S6, forming a metal gate 5 in the surface-treated gate recess 3;

S7, performing secondary annealing B on the device formed with the metal gate 5 .

In the preparation method of the GaN HEMT device according to the embodiment of the present invention, an integrated process flow of primary annealing A-nitrogen surface treatment-secondary annealing B is designed, wherein the primary annealing A and the secondary annealing B respectively form metal The gate 5 is performed front and back. Specifically, one-time annealing A is beneficial to reduce gate leakage in the device and provide high-quality gate contact; surface treatment with nitrogen can supplement the surface Ga-N bonds to reduce the formation of gate recesses such as etching The damage caused by the process to the device; the secondary annealing B can be used to further reduce defects such as atomic dislocations on the device surface. Through such an integrated process, GaN HEMT devices with low surface leakage can be manufactured without increasing the cost, thereby improving the overall performance of the device.

Specifically, the substrate 1 can be made of silicon carbide, and the silicon carbide can be, for example, semi-insulating silicon carbide, including 4H, 3C, 6H, and 15R polytypes. In some other embodiments, other suitable substrates such as sapphire, aluminum nitride, gallium nitride, silicon, zinc oxide, etc. may also be selected. As shown in (b) of FIG. 1 , a device body 2 is epitaxially grown on a substrate 1 . Specifically, a first GaN layer 21 is formed on the substrate 1, an AlGaN layer 22 is formed on the first GaN layer 21, a second GaN layer 23 is formed on the AlGaN layer 22, and a dielectric layer 24 is formed on the second GaN layer 23 . Due to the discontinuity of the conduction band at the interface of the first GaN layer 21 and the AlGaN layer 22, a triangular potential well will be formed, thereby gathering many electrons on one side of the first GaN layer 21 to form a two-dimensional electron gas (2DEG), and Guaranteed high mobility for GaN HEMT devices. The dielectric layer 24 can be made of silicon nitride, and the passivation effect of silicon nitride can reduce etching damage when the gate recess 3 is subsequently formed. The dielectric layer 24 can also be selected from aluminum nitride, silicon dioxide, ONO structure and the like.

Further, as shown in (c) of FIG. 1 , a gate recess 3 is formed in the device body 2 . Specifically, the dielectric layer 24 can be etched with SF ₆ gas to expose the surface of the second GaN layer 23 ; then the second GaN layer 23 can be etched with BCl ₃ gas to expose the surface of the AlGaN layer 22 . Thus, the gate recess 3 passing through the dielectric layer 24 , the second GaN layer 23 and extending to the surface of the AlGaN layer 22 is formed. The etching process may cause damage to the AlGaN layer 22 . In some embodiments, in order to limit the opening position of the gate recess 3 and prevent etching from causing damage to the area where the gate recess 3 is not formed, a mask may be provided on the dielectric layer 24 before the gate recess 3 is formed. film layer 4 , so that the gate recess 3 is formed through the mask layer 4 . The mask layer 4 can be a photoresist, and a specific area of the photoresist can be removed by photolithography to form the opening of the gate recess 3, and the unremoved part of the mask layer 4 is used to cover the dielectric layer 24. non-etched area.

Continuing to refer to (c) of FIG. 1 , an annealing A is performed on the device body 2 formed with the gate recess 3 . Specifically, the temperature of the primary annealing A can be set to 400° C., and the time is 30˜60 s. One-time annealing A is beneficial to reduce gate leakage in the device and provide high-quality gate contact.

Further, as shown in (d) of FIG. 1 , the surface treatment of the device body 2 after the primary annealing A treatment is carried out with nitrogen gas. In some embodiments, the mask layer 4 may be removed after annealing A and before surface treatment. Surface treatment with nitrogen includes placing the device body 2 in a nitrogen atmosphere. At this time, the nitrogen is in full contact with the surface of the AlGaN layer 22, which is conducive to the formation of new Ga-N bonds to compensate for the surface damage caused by the etching process, thereby ensuring subsequent The metal gate can be formed with high quality. The time for surface treatment with nitrogen may be 30-60s.

Further, as shown in (e) of FIG. 1 , a metal gate 5 is formed in the surface-treated gate recess 3 . The gate 5 can be deposited in the gate recess 3 by electron beam evaporation, and the metals that can be used include but are not limited to Ni/Au, Ni/Au/Ti, Ni/Pt/Au/Ni or Ni/Pt/ Multi-layer metal systems such as Au/Pt/Ti.

Continuing to refer to (e) of FIG. 1 , a secondary annealing B is performed on the device formed with the metal gate 5 . Specifically, the temperature of the secondary annealing B can be set to 450° C., and the time is 30˜60 s. Secondary annealing B can be used to further reduce defects such as atomic dislocations on the device surface.

Therefore, in the integrated process flow of primary annealing-nitrogen surface treatment-secondary annealing of the present invention, before the metal gate 5 is formed, the formation of the metal gate 5 is provided with good conditions for the formation of the metal gate 5 through primary annealing and surface treatment. The environment of the gate recess 3 is conducive to the formation of high-quality gate contacts; after the metal gate 5 is formed, the defects on the surface of the device can be further reduced by secondary annealing. Therefore, after a series of process steps, the manufacturing method of the embodiment of the present invention can advantageously reduce the surface leakage of the device.

The following will be described based on specific embodiments.

Example 1

Step 1: sequentially epitaxially grow the first GaN layer, AlGaN layer, second GaN layer and SiN dielectric layer on the SiC substrate, and cover the photoresist on the SiN dielectric layer;

Step 2: exposing and developing the photoresist to expose the SiN dielectric layer to form a recessed gate opening;

Step 3: Etch the SiN dielectric layer with SF ₆ gas, and then etch the second GaN layer with BCl ₃ gas to expose the AlGaN layer, forming a layer that passes through the SiN dielectric layer, the second GaN layer and extends to the surface of the AlGaN layer The grid is recessed;

Step 4: performing a rapid thermal annealing process at a temperature of 400° C. for 60 s in a high-temperature furnace;

Step 5: remove the remaining photoresist, and then place the device in a nitrogen atmosphere for 60s;

Step 6: Depositing a Ni/Au metal layer in the gate recess by using an electron beam process to form a metal gate;

Step 7: performing a rapid thermal annealing process at a temperature of 450° C. for 60 s in a high-temperature furnace.

The surface leakage of the GaN HEMT device prepared in Example 1 is significantly reduced, and the performance of the device is improved.

Although the present invention has been described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to illustrate the implementation of the present invention, and should not be construed as a limitation of the present invention.

It will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims (7)

1. a kind of preparation method of GaN HEMT device, comprising:

Substrate is provided；

Device body is formed on the substrate, the device body successively includes the first GaN layer, AlGaN by sequence from bottom to top Layer, the second GaN layer and dielectric layer；

Gate recess is formed in device body, the gate recess passes through dielectric layer, the second GaN layer and extends to AlGaN layer Surface；

It is once annealed to the device body for being formed with gate recess；

Device body through once annealing is surface-treated with nitrogen；

Metal gates are formed in surface treated gate recess；

Double annealing is carried out to the device for being formed with metal gates.

2. exposure mask is arranged on dielectric layer the method according to claim 1, wherein being formed before gate recess Layer, so that gate recess is formed across mask layer；And

It carries out after once annealing, before being surface-treated, removes the mask layer.

3. the method according to claim 1, wherein the temperature once annealed be 400 DEG C, the time be 30~ 60s。

4. the method according to claim 1, wherein being 30~60s with the time that nitrogen is surface-treated.

5. the method according to claim 1, wherein carry out double annealing temperature be 450 DEG C, the time be 30~ 60s。

6. the method according to claim 1, wherein forming metal gates includes by electron beam evaporation in grid Ni/Au is deposited in recessed.

7. according to the method described in claim 2, it is characterized in that, formation gate recess includes:

Mask layer described in photoetching；

Use SF₆Dielectric layer described in gas etching；And

Use BCl₃Second GaN layer described in gas etching.