CN109040833B - Decoding circuit and related decoding method applied to multimedia device - Google Patents

Abstract

The invention provides a decoding circuit applied to a multimedia device, which is used for decoding coded data to generate system information and comprises a plurality of processing circuits and a decision circuit. The processing circuits are used for processing the coded data respectively to generate a plurality of processed signals; wherein the plurality of processing circuit modules respectively correspond to a plurality of bit combinations of a portion of the system information; and the decision circuit is used for deciding the system information according to the processed signals.

Description

Decoding circuit and related decoding method applied to multimedia device

technical field

The present invention relates to a receiving circuit in a multimedia device, and more particularly, to a decoding circuit and a related decoding method applied to the multimedia device.

Background technique

In the current second-generation digital video broadcasting (DVB-S2) system, the receiver decodes the received physical layer signal (Physical Layer Signaling, PLS) encoded data to obtain a system information including 7 bits. The system information mainly includes modulation mode, symbol rate, whether there is preamble data, and forward error correction (Forward Error Correction, FEC) data length...etc. In the current extended second-generation digital video broadcasting (DVB-S2X) system, in addition to the different coding methods, there is one more system information to distinguish the second-generation digital video broadcasting and the extended second-generation digital video broadcasting system. A bit of generation for digital video broadcasting. Since the receiver cannot confirm the 8-bit system information before decoding, the receiver may encounter errors when decoding the encoded data of the physical layer signal, and needs to repeat the decoding many times to decode the correct system information. ; In addition, when the signal quality is poor, it is more likely to increase the probability of decoding errors, thus resulting in lower performance.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to provide a decoding circuit applied to a display device and a related decoding method, which can quickly and accurately decode the encoded data of the physical layer signal to obtain system information, so as to solve the problem in the prior art. The problem.

In one embodiment of the present invention, a decoding circuit applied to a multimedia device is provided, which decodes encoded data to generate a system information, and the decoding circuit includes a plurality of processing circuits and a determination circuit. The plurality of processing circuits are used to respectively process the encoded data to generate a plurality of processed signals; wherein the plurality of processing circuits are respectively corresponding to various bit combinations of a part of the system information; and the decision circuit It is used to determine the system information according to the plurality of processed signals.

In another embodiment of the present invention, a decoding method applied to a multimedia device is provided, which is used for decoding encoded data to generate a system information, and the decoding method includes the following steps: using a plurality of processing circuits to respectively processing the encoded data to generate a plurality of processed signals; wherein the plurality of processing circuits respectively correspond to various bit combinations of a part of the system information; and determine the system according to the plurality of processed signals information.

In another embodiment of the present invention, a decoding circuit applied to a multimedia device is provided for decoding an encoded data to generate a system information, and the decoding circuit includes a processing circuit and a determination circuit. The processing circuit is used for separately processing the encoded data to generate a plurality of processed signals, wherein the plurality of processed signals are respectively corresponding to a plurality of bit combinations of a part of the system information; and the determination circuit is coupled to in the plurality of processing circuits, and used for determining that the partial information corresponds to one of the plurality of bit combinations according to the plurality of processed signals.

Description of drawings

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a circuit applied to a display device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of one frame.

FIG. 3 is a block diagram of a decoding circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the rotation circuits 312 and 322 performing phase rotation.

FIG. 5 is a schematic diagram of the rotation circuits 332 and 342 performing phase rotation.

FIG. 6 is a block diagram of a decoding circuit according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of the operation of the superposition circuit.

FIG. 8 is a block diagram of a decoding circuit according to another embodiment of the present invention.

FIG. 9 is a flowchart of a decoding method applied to a display device according to an embodiment of the present invention.

The component numbers in the figure are explained as follows:

100 circuits

110 frame synchronization circuit

120 frame start section judgment circuit

130 Physical layer signal encoding data acquisition circuit

140 decoding circuit

302, 802 descrambling circuit

310, 320, 330, 340, 810 processing circuit

312, 322, 332, 342, 812 Rotary circuit

314, 324, 334, 344 Superposition Circuits

318, 328, 338, 348, 818 conversion circuit

304, 804 decision circuit

900～906 steps

Detailed ways

Please refer to FIG. 1 , which is a block diagram of a circuit 100 applied to a multimedia device according to an embodiment of the present invention. In this embodiment, the circuit 100 can be installed in a TV or a TV set-top box, and meets the Specifications for the Extended Second Generation Digital Video Broadcasting (DVB-S2X) system. Referring to FIG. 1 , the circuit 100 includes a frame synchronization circuit 110 , a frame start segment determination circuit 120 , a physical layer signal (PLS) encoded data extraction circuit 130 and a decoding circuit 140 .

In the operation of the circuit 100, first, the frame synchronization circuit 110 receives a received signal through the antenna, wherein the received signal includes a plurality of frames. Figure 2 shows a schematic diagram of a frame 200, wherein the frame 200 includes a physical layer header and a plurality of data slots for storing encoded data, and the physical layer header includes A start of frame (SOF) and a PLS code (PLS code) are included, wherein the start of frame contains information required for time synchronization. The frame start segment determination circuit 120 determines the address of the frame start segment in each frame, so that the PLS encoded data extraction circuit 130 can obtain the PLS encoded data in each frame. The decoding circuit 140 decodes the PLS encoded data to obtain a system information.

In the DVB-S2X system, the PLS encoded data is generated by the transmitting end calculating the system information and a generator matrix. The first bit b0 is used to indicate whether the signal conforms to the DVB-S2 system or the DVB-S2X system. For example, when the first bit b0 is "0", it indicates that the signal conforms to the DVB-S2 system, and when the first bit b0 is "0" When the bit b0 is "1", it indicates that the signal conforms to the DVB-S2X system; and the eighth bit b7 is used to indicate whether the PLS encoded data has a pilot data, for example, when the eighth bit b7 is "0" It means that there is no leading data, and when the eighth bit b7 is "1", it means that there is leading data. In the DVB-S2 system, the generator matrix is a 6*32 matrix, and the transmitter will multiply the six bits (b1,...,b6) in the system information and the generator matrix to a 1*32 intermediate matrix (that is, 32-bit data), and then generate a 1*64 matrix through the logical operation of the last bit b7 in the system information and the intermediate matrix, and then map it to a constellation to generate PLS encoded data. On the other hand, in the DVB-S2X system, the generator matrix is a 7*32 matrix, and the transmitter will multiply the first seven bits (b0,b1,...,b6) in the system information by the generator matrix to A 1*32 intermediate matrix, and then through the logical operation of the last bit b7 in the system information and the intermediate matrix to generate a 1*64 matrix, and then mapped to a constellation to generate PLS encoded data . Since the method of generating the PLS encoded data is well known to those skilled in the art, the detailed calculation method will not be repeated here.

The following is an example of a generator matrix in a DVB-S2 system:

And the following is an example of generator matrix in DVB-SX2 system:

The main feature of the present invention is that the received PLS encoded data is accurately and efficiently decoded and restored to system information by the decoding circuit 140 for subsequent operations.

Please refer to FIG. 3 , which is a block diagram of the decoding circuit 140 according to an embodiment of the present invention. As shown in FIG. 3, the decoding circuit 140 includes a descrambler circuit 302, four processing circuits 310, 320, 330, 340 and a decision circuit 304, wherein the processing circuit 310 includes a rotation circuit 312, a conversion circuit The circuit 318 and the processing circuit 320 include a rotation circuit 322 and a conversion circuit 328 , the processing circuit 330 includes a rotation circuit 332 and a conversion circuit 338 , and the processing circuit 340 includes a rotation circuit 342 and a conversion circuit 348 . In this embodiment, the descrambling circuit 302 is used to descramble the PLS encoded signal to generate a descrambled PLS encoded signal, and the four processing circuits 310 , 320 , 330 , and 340 are respectively used to descramble the PLS encoded signal. The PLS coded signal is processed by different calculation methods to generate the first, second, third and fourth processed signals respectively, wherein the four processing circuits 310, 320, 330 and 340 respectively correspond to a part of the system information Four combinations of information (the first bit b0 and the eighth bit b7), and these processed signals are used to reflect which bit combination this part of the information has. Specifically, the processing circuits 310, 320, 330, and 340 correspond to the bit combinations (b0=0, b7=0), (b0=0, b7=1), (b0=1, b7=1), The partial information of (b0=1, b7=0), when the partial information of the system information corresponding to the PLS coded signal has the combination of (b0=0, b7=0), the first processing generated by the processing circuit 310 The post-signal will be distinguishable (eg, a particularly high value) relative to other post-processing signals. Similarly, the processing circuits 320, 330 and 340 are respectively capable of targeting system information with partial information of (b0=0, b7=1), (b0=1, b7=1), (b0=1, b7=0) The corresponding descrambled PLS-encoded signals generate second, third and fourth processed signals that are identifiable with respect to other processed signals. Finally, the decision circuit 304 determines the difference between the first bit b0 and the eighth bit b7 of the system information according to the first, second, third and fourth processed signals output by the processing circuits 310 , 320 , 330 and 340 value, and further determine other bits b1-b6 according to the judgment result. The operation of each circuit element in the processing circuit modules 310, 320, 330, 340 and the decision circuit 304 will be described in detail below.

In the rotation circuits 312, 322, 332, and 342, the rotation circuit 312 is taken as an example. The rotation circuit 312 is used to perform phase rotation on each bit value of the descrambled PLC encoded data (64 bits) to map to an axis ( In this embodiment, it is the axis of the imaginary part of complex coordinates) to generate a first rotated encoded data, and then the values of the first rotated encoded data corresponding to adjacent odd-numbered points and even-numbered points are added together ( That is, the numerical value of the encoded data after the first rotation corresponding to the first bit value and the second bit value is added, and the numerical value of the encoded data after the first rotation corresponding to the third bit value and the fourth bit value is added. Adding, ... and so on, and in this embodiment, the value of the encoded data after the first rotation refers to its value on the axis of the imaginary part of the complex coordinate) to obtain a first information (1*32 matrix) , wherein the manner in which the rotation circuit 312 performs the phase rotation is related to the specification of the DVB-S2 system. The rotation circuit 322 is similar to the rotation circuit 312 in that it generates a second rotated encoded data according to each bit value of the descrambled PLC encoded data, and then encodes the second rotated encoded data corresponding to adjacent odd-numbered points and even-numbered points. The values of are subtracted to obtain a second information (1*32 matrix). Please refer to FIG. 4 , which is a schematic diagram of the rotation circuits 312 and 322 performing phase rotation, wherein "i" in the figure represents the "i" th bit, that is, "i" can be 1 to 32, and y _2i-1 represents Referring to the bit value of the odd-numbered point of the PLC encoded data after descrambling, y _2i represents the bit value of the even-numbered point of the PLC encoded data after descrambling, "I" represents the real part axis, and "Q" represents the imaginary part axis. When the bit value of the odd-numbered point of the PLC-encoded data after descrambling is "0", the rotation circuits 312 and 322 will rotate it (π/4) to obtain a value of "+1"; when the odd-numbered point of the descrambled PLC-encoded data is "0" When the bit value of the point is "1", the rotation circuit 312, 322 will rotate it (π/4) to obtain the value "-1"; when the bit value of the even-numbered point of the PLC encoded data after descrambling is "0" , the rotation circuits 312 and 322 will rotate it (-π/4) to obtain the value "+1"; and when the bit value of the even-numbered point of the PLC encoded data after descrambling is "1", the rotation circuits 312 and 322 will Rotate it (-π/4) to get the value "-1".

The rotation circuit 332 is similar to the rotation circuit 312 in that it generates a third rotated encoded data according to each bit of the descrambled PLC encoded data, and then encodes the third rotated encoded data corresponding to adjacent odd-numbered points and even-numbered points. The values of , are added to obtain a third information (1*32 matrix), which differs from the rotation circuit 312 in that the way the rotation circuit 332 performs phase rotation is related to the specifications of the DVB-S2X system; the rotation circuit 342 is similar to the rotation circuit 322 is to generate a fourth rotated encoded data according to each bit of the PLC encoded data after descrambling, and then subtract the fourth rotated encoded data corresponding to the values of adjacent odd-numbered points and even-numbered points to obtain a The fourth information (matrix of 1*32) differs from the rotation circuit 322 in that the phase rotation method of the rotation circuit 342 is performed according to the specification of the DVB-S2X system. Please refer to FIG. 5 , which is a schematic diagram of the rotation circuits 332 and 342 performing phase rotation. When the bit value of the odd-numbered point of the PLC encoded data after descrambling is “0”, the rotation circuits 332 and 342 will rotate it (-π /4) to obtain the value "+1"; when the bit value of the odd-numbered point of the PLC encoded data after descrambling is "1", the rotation circuits 332 and 342 will rotate it (-π/4) to obtain the value "- 1"; when the bit value of the even-numbered point of the PLC encoded data after descrambling is "0", the rotation circuits 332 and 342 will rotate it (π/4) to obtain the value "-1"; When the bit value of the even-numbered point of the encoded data is "1", the rotation circuits 332, 342 rotate it by (π/4) to obtain the value "+1".

Each value of the first information generated by the above-mentioned rotation circuit 312 can be represented as follows:

r _{soft_add, S2, i} = imag(y _2i-1 e ^jπ/4 )+imag(y _2i e ^-jπ/4 );

Each value in the second information generated by the rotation circuit 322 can be represented as follows:

r _{soft_sub, S2, i} = imag(y _2i-1 e ^jπ/4 )-imag(y _2i e ^-jπ/4 );

Each value in the third information generated by the rotation circuit 332 can be represented as follows:

r _{soft_sub, S2X, i} = imag(y _2i-1 e ^-jπ/4 )+imag(y _2i e ^jπ/4 );

Each value in the fourth information generated by the rotation circuit 342 can be represented as follows:

r _{soft_sub,S2X,i} =imag(y _2i-1 e ^-jπ/4 )-imag(y _2i e ^jπ/4 ).

As mentioned above, for this part of the information of any combination of bits, one of the first to fourth information will have identification (for example, a particularly high value), which is actually enough for the decision circuit 304 to use to determine which bit combination the part of the information is. Next, please refer to FIG. 6 , which is a block diagram of a decoding circuit 140 according to another embodiment of the present invention, wherein in the embodiment shown in FIG. 324, 334, 344. Regarding the operations of the superimposing circuits 314, 324, 334, and 344, please refer to FIG. 7 at the same time. The superimposing circuit 314 is used to superimpose a plurality of first information corresponding to different frames to generate a first superimposed data. Similarly, The superimposing circuits 324, 334 and 344 respectively superimpose a plurality of second, third and fourth information corresponding to different frames to generate a second superimposed data, a third superimposed data and a fourth superimposed data. Since the superimposed data further increases the difference between them, the judgment on this part of the information will be more accurate.

The conversion circuits 318 , 328 , 338 and 348 decode the first to fourth information or the PLS codes in the first to fourth superimposed data through a matrix conversion. Please note that since the first row of the generator matrix used to generate the PLS encoded signal in the transmitting end of the DVB-S2X system is not all 0, the conversion circuits 338 and 348 further include a mapping circuit (not shown) to Remove the effect of the first row of the generator matrix on the PLS encoded signal. In other words, the mapping circuits included in the conversion circuits 338 and 348 modify part of the content of the third superimposed data and the fourth superimposed data respectively, so as to remove the influence of the first row of the generation matrix. In this embodiment, the mapping circuits 336 and 346 respectively map the 0th, 3rd, 8th, 10th, 12th, 13th, 18th, 20th, 21st, 23rd, 24th, Bits 25, 27, 28, 29, and 31 perform sign conversion to remove the effect of the first row of the generator matrix. On the contrary, since the DVB-S2 system does not have the above problems, no additional mapping circuit is required to process the first and second superimposed data.

Finally, the conversion circuits 318, 328, 338, and 348 respectively perform data conversion on the first, second, third, and fourth superimposed data (wherein the third and fourth superimposed data are processed by the mapping circuit and processed) to generate the first, second, third, and fourth superimposed data respectively. 1st, 2nd, 3rd and 4th processed signals. In this embodiment, the conversion circuits 318, 328, 338, and 348 multiply the first, second, third, and fourth superimposed data by a 32*32 Hadamard matrix, respectively, to generate the first, The second, third, and fourth processed signals. The operation of the conversion circuit 318 can be expressed as follows:

A _{soft_add, S2} = r _{soft_add, S2} H _32*32

r _{soft_add, S2} = [r _{soft_add} . S2, 1 ... r _{soft_add} , S2, 31 ]

Among them, A _{soft_add, S2} is the first processed signal, r _{soft_add, S2} is used to represent the first superimposed data, and H _32*32 is the Hadamard matrix;

The operation of the conversion circuit 328 can be expressed as follows:

A _{soft_sub, S2} = r _{soft_add, S2} H _32*32

r _{soft_sub, S2} = [r _{soft_sub} . S2, 1 ... r _{soft_sub} , S2, 31 ]

where A _{soft_sub, S2} is the second processed signal, and r _{soft_sub, S2} is used to represent the second superimposed data;

The operation of the conversion circuit 328 can be expressed as follows:

A _{soft_add, S2X} = r _{soft_add, S2X} H _32*32

r _{soft_add, S2X} = [r _{soft_add. S2X, 1} ... r _{soft_add, S2, 31} ]

Among them, A _{soft_add, S2X} is the third processed signal, and r _{soft_add, S2X is} used to represent the third superimposed data processed by the mapping circuit;

The operation of the conversion circuit 348 can be expressed as follows:

A _{soft_sub, S2X} = r _{soft_add, S2X} H _32*32

r _{soft_sub, S2X} = [r _{soft_sub. S2X, 1} ... r _{soft_sub, S2X, 31} ]

A _{soft_sub, S2X} is the fourth processed signal, and r _{soft_sub, S2X is} used to represent the fourth superimposed data processed by the mapping circuit.

Finally, the determination circuit 304 determines the values of b0 and b7 in the system information according to the first, second, third and fourth processed signals, and determines other bits b1 to b6 accordingly. Specifically, the determination circuit 304 first determines the argument with the largest value in the first, second, third, and fourth processed signals as follows:

a ₀ =arg max|A _{soft_add,S2} |,A _{soft_add_S 2} ={A _0,0 ,A _0,1 ,...A _0,31 };

a ₁ =arg max|A _{soft_sub,S2} |,A _{soft_sub_S 2} ={A _1,0 ,A _1,1 ,...A _1,31 };

a ₂ =arg max|A _{soft_add, S2X} |, A _{soft_add_S 2X} = {A _2,0 , A _2,1 ,...A _2,31 };

a ₃ =arg max|A _{soft_sub,S2} |,A _{soft_sub_S 2} ={A _3,0 ,A _3,1 ,...A _3,31 };

The decision circuit 304 compares the sizes of a0, a1, a2, and a3 to determine the values of b0 and b7 in the system information, that is, when the value of a0 is the largest, b0=0, b7=0; when the value of a1 is the largest, b0=0, b7=1; when the value of a2 is the largest, b0=1, b7=1; when the value of a3 is the largest, b0=1, b7=0.

Next, assuming that the largest value among a0, a1, a2, and a3 is amax (which will be an integer between 0 and 31), then the values of b1 to b5 can be obtained by taking the binary representation of amax, that is, :

amax=(b ₅ b ₄ b ₃ b ₂ b ₁ ), a∈{0,31};

Finally _, the value of b6 in the system information is determined according to whether the values of A max_index and amax are greater than 0. When the values of A _{max_index and amax} are greater than 0, b6 is 0, and when the values of A _{max_index and amax} are not greater than 0, b6 is 1. Where max_index indicates which amax corresponds to a0, a1, a2, a3, that is, when amax is a0, max_index is "0", when amax is a1, max_index is "1"... and so on.

As mentioned above, the eight-bit system information b0~b7 can be accurately known, and this system information mainly includes information such as modulation method, symbol rate, whether there is preamble data, and the length of forward error correction data. This information can be passed to the back end for use by components of the compensation or equalizer.

It should be noted that although the above embodiment takes the decoding circuit in the DVB-S2X system as an example, the present invention is not limited to this. In other embodiments of the present invention, as long as there are multiple processing circuit modules in the decoding circuit to perform different calculations on the encoded data at the same time, and the processed signal generated by each processing circuit module can reflect part of the information in a system information a specific bit combination, the present invention can be applied to various decoding circuits. In addition, in an embodiment, when part of the information in the system information is N bits, the number of the plurality of processing circuit modules is the square of N. In addition, although the decision circuit 304 determines the values of b0 and b7 in the system information according to the first, second, third, and fourth processed signals in this case, as mentioned above, the decoding circuit 140 proposed in this case Among them, the determination circuit 304 can also directly perform the determination according to one of the first to fourth information or the data with identification (for example, a particularly high value) in the first to fourth superimposed data. However, the determination circuit 304 performs the aforementioned determination according to the first to fourth processed signals, so that the values of b1 to b6 in the system information can be determined at the same time, so it is more efficient.

Please refer to FIG. 8 , which is a block diagram of a decoding circuit 140 according to another embodiment of the present invention. As shown in FIG. 8 , the decoding circuit 140 includes a descrambling circuit 802 , a processing circuit 810 and a determination circuit 804 , wherein the processing circuit 810 includes a rotation circuit 812 and a conversion circuit 818 . The difference between the embodiment shown in FIG. 8 and the embodiment shown in FIG. 3 is only that the embodiment shown in FIG. 3 uses four different processing circuits 310 to 340 to synchronously process the descrambled PLS coded signal, while the embodiment shown in FIG. The time-division processing method is used to process the descrambled PLS coded signal. Specifically, at the first time point, the processing circuit 810 operates the same as the processing circuit 310 to generate a first processed signal, and at the second time point the processing circuit 810 operates the same as the processing circuit 320 to generate a first signal. Two processed signals, the operation of the processing circuit 810 at the third time point is the same as that of the processing circuit 330 to generate a third processed signal, and the operation of the processing circuit 810 at the fourth time point is the same as that of the processing circuit 340 to generate a Fourth processed signal. Finally, the determination circuit 304 can determine the values of b0 and b7 in the system information after collecting the first, second, third and fourth processed signals, and determine other bits b1 to b6 accordingly.

FIG. 9 is a flowchart of a decoding method applied to a display device according to an embodiment of the present invention. 1 to 7 and the content disclosed above, the flow of the decoding method is as follows:

Step 900: The process starts.

Step 902: Receive an encoded data, wherein the encoded data is obtained by encoding a system information.

Step 904: Use a plurality of processing circuits to respectively process the encoded data to generate a plurality of processed signals, wherein the plurality of processing circuits are respectively corresponding to various bit combinations of a part of the system information.

Step 906: Determine the system information according to the plurality of processed signals.

To briefly summarize the present invention, in the decoding circuit and related decoding method of the present invention, a plurality of processing circuit modules are used to perform different operations on the PLS encoded data to obtain a plurality of processed signals, wherein each processing circuit module is a A bit combination corresponding to a part of the system information corresponding to the PLS coded data, and the generated processed signal can reflect whether the PLS coded data corresponds to the bit combination. Through the present invention, the PLS coded data can be decoded accurately at one time to obtain the system information, so as to avoid the problem in the prior art that successful decoding may require multiple attempts.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be defined by the claims.

Claims (20)

1. A decoding circuit applied to a multimedia device of a digital video broadcasting system for decoding an encoded data to generate a system information, the decoding circuit comprising:

a plurality of processing circuits for processing the encoded data to generate a plurality of processed signals, respectively; wherein the plurality of processing circuits respectively correspond to a plurality of bit combinations of a portion of the system information; and

and the decision circuit is coupled with the processing circuits and used for deciding the system information according to the processed signals.

2. The decoding circuit of claim 1, wherein the portion of information comprises N bits, and the number of the plurality of processing circuits is N squared.

3. The decoding circuit of claim 1, wherein the multimedia device conforms to a Digital Video Broadcasting (DVB) system, and the encoded data is Physical Layer Signaling (PLS) encoded data.

4. The decoding circuit of claim 3, wherein the portion of information includes a first bit and a second bit, wherein the first bit indicates that the encoded data conforms to one of a second generation digital video broadcasting (DVB-S2) system and an extended second generation digital video broadcasting (DVB-S2X) system, and the second bit indicates whether the encoded data has a preamble (pilot) data.

5. The decoding circuit of claim 4, wherein one of the processing circuits is configured to process the encoded data to generate one of the processed signals, and when the first bit indicates the extended second-generation digital video broadcast and the second bit indicates that the encoded data has the preamble data, the one of the processed signals is recognizable as compared to other processed signals.

6. The decoding circuit of claim 5, wherein:

the one of the plurality of processing circuits comprises:

a rotation circuit for performing phase rotation on each bit value in the encoded data to map onto an axis to generate a plurality of rotated encoded data, and adding two rotated encoded data generated according to adjacent bit values to obtain an information; and

a conversion circuit for performing data conversion according to the information to generate the one of the processed signals.

7. The decoding circuit of claim 6, wherein:

the one of the plurality of processing circuits further comprises:

a superposition circuit for superposing a plurality of information corresponding to different frames to generate a superposed data, wherein the conversion circuit performs data conversion according to the superposed data to generate the one of the plurality of processed signals.

8. The decoding circuit of claim 6, wherein the encoded data is generated by multiplying the system information by a generator matrix, and the one of the plurality of processing circuits further comprises:

a mapping circuit for mapping the information to remove the influence of a specific content in the generated matrix.

9. The decoding circuit of claim 1, wherein the determining circuit determines the argument with the largest value in the processed signals, and obtains a portion of bit values of the system information by taking a binary representation of the argument with the largest value.

10. The decoding circuit of claim 9, wherein the determining circuit further determines a value of the processed signal according to the argument having the largest value, and further determines another bit value of the system information according to whether the value is greater than zero.

11. A decoding method applied to a multimedia device of a digital video broadcasting system for decoding an encoded data to generate a system information, the decoding method comprising the steps of:

processing the encoded data using a plurality of processing circuits, respectively, to generate a plurality of processed signals; wherein the plurality of processing circuits respectively correspond to a plurality of bit combinations of a portion of the system information; and

the system information is determined according to the processed signals.

12. The decoding method of claim 11, wherein the partial information comprises N bits, and the number of the processing circuits is N squared.

13. The decoding method of claim 11, wherein the multimedia device conforms to a Digital Video Broadcasting (DVB) system, and the encoded data is Physical Layer Signaling (PLS) encoded data; the portion of information includes a first bit indicating that the encoded data conforms to one of a second generation digital video broadcasting (DVB-S2) system and an extended second generation digital video broadcasting (DVB-S2X) system, and a second bit indicating whether the encoded data has preamble data.

14. The decoding method of claim 13, wherein one of the processing circuits is configured to process the encoded data to generate one of the processed signals, and when the first bit indicates the extended second-generation digital video broadcast and the second bit indicates that the encoded data has the preamble data, the one of the processed signals is recognizable as compared to other processed signals.

15. The decoding method of claim 14,

the step of processing the encoded data to generate one of the plurality of processed signals comprises:

performing phase rotation on each bit value in the encoded data to map the bit values onto an axis to generate a plurality of rotated encoded data, and adding two rotated encoded data generated according to adjacent bit values to obtain information; and

data conversion is performed according to the information to generate the one of the plurality of processed signals.

16. The decoding method of claim 15, wherein the step of processing the encoded data to generate one of the processed signals further comprises:

superposing a plurality of information corresponding to different frames to generate superposed data; and

the step of performing data conversion to generate the one of the processed signals according to the information comprises:

and performing data conversion according to the superimposed data to generate the one of the plurality of processed signals.

17. The decoding method of claim 15, wherein the encoded data is generated by multiplying the system information by a generator matrix, and the step of processing the encoded data to generate one of the processed signals further comprises:

the information is mapped to remove the effect of a specific content in the generator matrix.

18. The decoding method of claim 11, wherein the step of determining the system information according to the processed signals comprises:

the argument with the maximum value in the processed signals is determined, and a part of bit values of the system information is obtained by taking a binary expression of the argument with the maximum value.

19. The decoding method of claim 18, wherein the step of determining the system information according to the processed signals further comprises:

and determining a value of the processed signal according to the argument having the largest value, and determining another bit value of the system information according to whether the value is greater than zero.

20. A decoding circuit applied to a multimedia device of a digital video broadcasting system for decoding an encoded data to generate a system information, the decoding circuit comprising:

a processing circuit for processing the encoded data to generate a plurality of processed signals; wherein the plurality of processed signals are a plurality of bit combinations respectively corresponding to a portion of the system information; and

and a decision circuit, coupled to the processing circuits, for determining whether the portion of information corresponds to one of the plurality of bit combinations according to the processed signals.

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