CN109086230A - A kind of method and device promoting NandFlash bus timing allowance - Google Patents
A kind of method and device promoting NandFlash bus timing allowance Download PDFInfo
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- CN109086230A CN109086230A CN201810843342.8A CN201810843342A CN109086230A CN 109086230 A CN109086230 A CN 109086230A CN 201810843342 A CN201810843342 A CN 201810843342A CN 109086230 A CN109086230 A CN 109086230A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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Abstract
本发明公开了一种提升NandFlash总线时序裕量的方法、装置、设备及计算机可读存储介质，该方法包括：获取NandFlash总线上指定点当前时刻的当前电压值、充电前电压值、充电后电压值、总线等效电阻值及设定充电时间值，设定充电时间值为设定的指定点的电压值由充电前电压值变化至充电后电压值所需的时间；基于当前电压值、充电前电压值、充电后电压值、总线等效电阻值及设定充电时间值计算NandFlash总线的总线等效电容值；基于总线等效电容值及NandFlash总线的负载电容值计算需增加的特定电容的电容值，并将该特定电容与负载电容值对应的负载电容串联。本申请能够提升总线的时序裕量，提高运行速率。
The invention discloses a method, device, device and computer-readable storage medium for improving the timing margin of a NandFlash bus. The method includes: obtaining the current voltage value at a specified point on the NandFlash bus at the current moment, the voltage value before charging, and the voltage after charging Value, bus equivalent resistance value and set charging time value, the set charging time value is the time required for the voltage value of the specified point to change from the pre-charging voltage value to the post-charging voltage value; based on the current voltage value, charging Calculate the bus equivalent capacitance value of the NandFlash bus based on the pre-voltage value, post-charging voltage value, bus equivalent resistance value and set charging time value; calculate the specific capacitance to be added based on the bus equivalent capacitance value and the load capacitance value of the NandFlash bus Capacitance value, and connect that particular capacitance in series with the load capacitance corresponding to the load capacitance value. The application can increase the timing margin of the bus and increase the operating speed.
Description
Technical field
The present invention relates to NandFlash bussing technique fields, more specifically to a kind of promotion NandFlash bus
Method, apparatus, equipment and the computer readable storage medium of timing allowance.
Background technique
NandFlash bus is a kind of internal parallel memory bus using non-linear macroelement mode；With big data
The arriving in epoch, the demand to " memory capacity for promoting unit product unit volume " and " delay for reducing whole system " are more next
Stronger, " large capacity " means that the die quantity of carry on single channel in NandFlash bus will gradually increase, load capacitance
It is increasing；" low delay " means that the operating rate requirement of NandFlash bus also can be higher and higher.But load capacitance
Bigger, the signal edge degeneration run is more serious, meets smaller (the NandFlash bus of timing allowance window of system requirements
Timing allowance is smaller), it can be achieved that operating rate it is lower --- i.e. " large capacity " and " high-speed " be in NandFlash bus
One contradictory presence.The operating rate of NandFlash bus, which already becomes, restricts the bottleneck place that entire storage performance is promoted.
In conclusion exist in the prior art cause since load capacitance is larger the timing allowance of NandFlash bus compared with
Problem small, operating rate is lower.
Summary of the invention
The object of the present invention is to provide a kind of method, apparatus, equipment and calculating for promoting NandFlash bus timing allowance
Machine readable storage medium storing program for executing, be able to solve it is existing in the prior art cause since load capacitance is larger NandFlash bus when
The problem that sequence allowance is smaller, operating rate is lower.
To achieve the goals above, the invention provides the following technical scheme:
A method of promoting NandFlash bus timing allowance, comprising:
Obtain in NandFlash bus voltage value, charged voltage before the current voltage value at specified point current time, charging
Value, bus equivalent resistance and setting charging time value, the charging time value that sets is the voltage of the specified point set
Time needed for value is changed to charged voltage value as voltage value before charging；
Based on voltage value, charged voltage value, bus equivalent resistance and setting charging before the current voltage value, charging
Time value calculates the bus equivalent capacitance value of the NandFlash bus；
Being calculated based on the load capacitance value of the bus equivalent capacitance value and the NandFlash bus need to be increased specific
The capacitance of capacitor, and specific capacitor load capacitance corresponding with the load capacitance value is connected.
Preferably, the bus equivalent capacitance value of the NandFlash bus is calculated, comprising:
The bus equivalent capacitance value of the NandFlash bus is calculated according to the following formula:
Vt=V0+ (Vu-V0) * [1-exp (- t/RC)],
Wherein, V0 is voltage value before charging, and Vu is charged voltage value, and Vt is current voltage value, and t is the setting charging time
Value, R are bus equivalent resistance, and C is bus equivalent capacitance value；
Calculate the capacitance for needing increased specific capacitor, comprising:
The capacitance for needing increased specific capacitor is calculated according to the following formula:
C=(C1*C2)/(C1+C2),
Wherein, C1 is load capacitance value, and C2 is the capacitance of specific capacitor.
Preferably, specific capacitor load capacitance corresponding with the load capacitance value is connected, comprising:
If the specified point is located on the main line of the NandFlash bus, the specific capacitor is embedded to PCB base
In plate, connected with the load capacitance group formed with whole load capacitances of the NandFlash bus.
Preferably, specific capacitor load capacitance corresponding with the load capacitance value is connected, comprising:
If the specified point is located on each load branch of the NandFlash bus, for any specified point,
The corresponding specific capacitor calculated of any specified point is integrated into the load capacitance on the load branch that any specified point is located at
In corresponding particle encapsulation, to connect with the load capacitance in particle encapsulation.
A kind of device promoting NandFlash bus timing allowance, comprising:
Module is obtained, is used for: being obtained electric before the current voltage value at specified point current time, charging in NandFlash bus
Pressure value, charged voltage value, bus equivalent resistance and setting charging time value, the charging time value that sets is the institute of setting
State specified point voltage value charged voltage value is changed to as voltage value before charging needed for the time；
First computing module, is used for: based on voltage value, charged voltage value, bus before the current voltage value, charging etc.
Effect resistance value and setting charging time value calculate the bus equivalent capacitance value of the NandFlash bus；
Second computing module, is used for: the load capacitance based on the bus equivalent capacitance value and the NandFlash bus
Value calculates the capacitance for needing increased specific capacitor, and by specific capacitor load capacitance string corresponding with the load capacitance value
Connection.
Preferably, the first computing module includes:
First computing unit, is used for: the bus equivalent capacitance value of the NandFlash bus is calculated according to the following formula:
Vt=V0+ (Vu-V0) * [1-exp (- t/RC)],
Wherein, V0 is voltage value before charging, and Vu is charged voltage value, and Vt is current voltage value, and t is the setting charging time
Value, R are bus equivalent resistance, and C is bus equivalent capacitance value；
Second computing module includes:
Second computing unit, is used for: the capacitance for needing increased specific capacitor is calculated according to the following formula:
C=(C1*C2)/(C1+C2),
Wherein, C1 is load capacitance value, and C2 is the capacitance of specific capacitor.
Preferably, second computing module includes:
First operating unit, is used for: if the specified point is located at the main line of the NandFlash bus, by institute
It states in specific capacitor embedment PCB substrate, the load capacitance group string formed with whole load capacitances with the NandFlash bus
Connection.
Preferably, second computing module includes:
Second operating unit, is used for: if the specified point is located at each load branch of the NandFlash bus
On, then for any specified point, the corresponding specific capacitor calculated of any specified point is integrated into what any specified point was located at
In the corresponding particle encapsulation of load capacitance on load branch, to connect with the load capacitance in particle encapsulation.
A kind of equipment promoting NandFlash bus timing allowance, comprising:
Memory, for storing computer program；
Processor, when realizing the as above any one promotion NandFlash bus when for executing the computer program
The step of method of sequence allowance.
A kind of computer readable storage medium is stored with computer program on the computer readable storage medium, described
The step of the as above any one method for promoting NandFlash bus timing allowance is realized when computer program is executed by processor
Suddenly.
The method, apparatus of NandFlash bus timing allowance, equipment and computer-readable are promoted the present invention provides a kind of
Storage medium, wherein this method comprises: obtaining in NandFlash bus before the current voltage value at specified point current time, charging
Voltage value, charged voltage value, bus equivalent resistance and setting charging time value, the charging time value that sets is setting
Time needed for the voltage value of the specified point is changed to charged voltage value as voltage value before charging；Based on the current voltage
Value, the preceding voltage value that charges, charged voltage value, bus equivalent resistance and setting charging time value calculate the NandFlash
The bus equivalent capacitance value of bus；Based on the load capacitance value of the bus equivalent capacitance value and the NandFlash bus
The capacitance for needing increased specific capacitor is calculated, and specific capacitor load capacitance corresponding with the load capacitance value is connected.
In technical solution disclosed in the present application, before specified point is by charging in the NandFlash bus for meeting current demand based on setting
To the corresponding setting charging time value of charged voltage, being calculated by way of retrodicting should connect voltage change with load capacitance
Specific capacitor capacitance, and the specific capacitor is connected with load capacitance, the bus obtained after series connection can not only be made
Equivalent capacitance value meets the charging time value of current demand, and then meets the timing allowance of current demand, and passes through two capacitors
Equivalent capacity is less than the principle of any one series capacitance after series connection, can reduce the bus equivalent capacity under heavy load scene
Value, the degeneration at attenuated signal edge increase timing allowance window, promote the timing allowance of NandFlash bus to reach, mention
The purpose of high operating rate.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of flow chart of method for promoting NandFlash bus timing allowance provided in an embodiment of the present invention；
Fig. 2 is the quantity of load capacitance in the prior art when being two, the route signal of corresponding NandFlash bus
Figure；
Fig. 3 is in a kind of method for promoting NandFlash bus timing allowance provided in an embodiment of the present invention by specific electricity
Hold the conspectus of the PCB substrate of NandFlash bus shown in embedment Fig. 2；
Fig. 4 is in a kind of method for promoting NandFlash bus timing allowance provided in an embodiment of the present invention by specific electricity
Hold the conspectus for being integrated to the particle encapsulation of NandFlash bus shown in Fig. 2；
Fig. 5 is a kind of structural representation of device for promoting NandFlash bus timing allowance provided in an embodiment of the present invention
Figure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, it illustrates a kind of sides for promoting NandFlash bus timing allowance provided in an embodiment of the present invention
The flow chart of method may include:
S11: in acquisition NandFlash bus before the current voltage value at specified point current time, charging after voltage value, charging
Voltage value, bus equivalent resistance and setting charging time value, set charging time value as setting specified point voltage value by
Time needed for voltage value is changed to charged voltage value before charging.
A kind of execution subject of method promoting NandFlash bus timing allowance provided in an embodiment of the present invention can be
Corresponding device.It should be noted that specified point is a parameter value collection point in NandFlash bus, current electricity
Pressure value is the voltage value at the specified point current time acquired, and voltage value refers to that the capacitor in NandFlash bus carries out before charging
The voltage value of specified point before charging, charged voltage value refer to the electricity of the fully charged rear specified point of the capacitor in NandFlash bus
Pressure value, bus equivalent resistance are the equivalent resistance all with resistance value device for including in NandFlash bus, and setting is filled
Electric time value is the value of time needed for the voltage value of specified point is changed to charged voltage value as voltage value before charging, wherein
Current voltage value collects in real time, voltage value before charging, charged voltage value and bus equivalent resistance be with
NandFlash bus is corresponding, that is, determines that matching for NandFlash bus postpones, then after can determine that charging preceding voltage value, charging
Voltage value and bus equivalent resistance, and setting charging time value then is according to actual needs setting, the setting charging time
The specific value of value is corresponding with NandFlash bus timing allowance, i.e. the NandFlash bus timing allowance of current scene needs
It is bigger, then the smaller of charging time value setting will be set, conversely, the setting charging time value can be then arranged bigger.
S12: based on voltage value, charged voltage value, bus equivalent resistance and setting charging before current voltage value, charging
The bus equivalent capacitance value of time value calculating NandFlash bus.
Value based on above-mentioned each parameter can be calculated the bus equivalent capacitance value of NandFlash bus, and the bus
Equivalent capacitance value is then the equivalent capacitance value for whole capacitors that NandFlash bus includes, and thereby, it is possible to determine
In the case where NandFlash bus timing allowance meet demand, equivalent capacitance value that NandFlash bus should have.
S13: being calculated based on the load capacitance value of bus equivalent capacitance value and NandFlash bus needs increased specific capacitor
Capacitance, and corresponding with the load capacitance value load capacitance of the specific capacitor is connected.
The capacitance of specific capacitor, specifically, bus are calculated according to specific capacitor and the concatenated mode of load capacitance
Equivalent capacity is the equivalent capacity after specific capacitor is connected with load capacitance, as a result, in known bus equivalent capacity and load
In the case where capacitance, the capacitance of specific capacitor can be calculated, so that the specific capacitor is added to NandFlash bus
The timing allowance of NandFlash bus is enabled to meet demand.It should be noted that under normal circumstances, it is calculated specific
The capacitance of capacitor is smaller than the load capacitance value of load capacitance, if load capacitance value is 100F or so, then the electricity of specific capacitor
Capacitance may be merely illustrative herein its gap in 30F or so, certainly, specifically will also be determines according to actual conditions.In addition,
The movement that specific capacitor is added to NandFlash bus in the application can be by promoting NandFlash bus timing allowance
Device in include operation robot realize automatically.
In technical solution disclosed in the present application, specified point in the NandFlash bus for meeting current demand based on setting
By voltage change before charging to the corresponding setting charging time value of charged voltage, being calculated by way of retrodicting should be with load
The capacitance of the concatenated specific capacitor of capacitor, and the specific capacitor is connected with load capacitance, it is obtained after series connection can not only be made
To bus equivalent capacitance value meet the charging time value of current demand, and then meet the timing allowance of current demand, and pass through
Equivalent capacity is less than the principle of any one series capacitance after two capacitor series connection, can reduce the bus etc. under heavy load scene
Capacitance is imitated, the degeneration at attenuated signal edge increases timing allowance window, to reach the timing for promoting NandFlash bus
Allowance, the purpose for improving operating rate.
A kind of method promoting NandFlash bus timing allowance provided in an embodiment of the present invention, it is total to calculate NandFlash
The bus equivalent capacitance value of line may include:
The bus equivalent capacitance value of NandFlash bus is calculated according to the following formula:
Vt=V0+ (Vu-V0) * [1-exp (- t/RC)],
Wherein, V0 is voltage value before charging, and Vu is charged voltage value, and Vt is current voltage value, and t is the setting charging time
Value, R are bus equivalent resistance, and C is bus equivalent capacitance value；
The capacitance for needing increased specific capacitor is calculated, can include: with 1
The capacitance for needing increased specific capacitor is calculated according to the following formula:
C=(C1*C2)/(C1+C2),
Wherein, C1 is load capacitance value, and C2 is the capacitance of specific capacitor.
By above-mentioned two formula, the process for calculating related parameter values is quickly and effectively realized.
A kind of method promoting NandFlash bus timing allowance provided in an embodiment of the present invention, by specific capacitor and bears
The corresponding load capacitance series connection of capacitance is carried, may include:
If specified point is located on the main line of NandFlash bus, by specific capacitor be embedded to PCB substrate in, with
The load capacitance group series connection of whole load capacitances composition of NandFlash bus.
It should be noted that NandFlash bus may include main line and load branch correspondingly with each load capacitance
Road is two with the quantity of load capacitance in the application and is specifically described, corresponding NandFlash bus in the prior art
Conspectus can be as shown in Figure 2, wherein NandFlash Controller, where Rtrace, Ltrace and Ctrace
(NandFlash Controller to point a) is main line to route, and (point a is extremely for route where NandFlash IC1Cload1
NandFlash IC1Cload1) and NandFlash IC2Cload2 (point a to NandFlash IC2Cload2) where route be
The specific location of two load branch, specified point can be according to actually being set, if specified point is located at main line, the application
Middle load capacitance value is then that (corresponding diagram 2 is then for by NandFlash by the equivalent obtained capacitance of whole load capacitances
The equivalent obtained capacitance of IC1Cload1 and NandFlash IC2Cload2), this seasonal specific capacitor and whole load capacitances
The load capacitance group of composition is connected, and also specific capacitor (Cserial) can be arranged on main line, be specifically as follows Fig. 3 institute
At the position shown, and Rtrace, Ltrace and Ctrace belong to PCB substrate, therefore specific capacitor is enabled to be set as position shown in Fig. 3
Place to be set also specific capacitor is embedded in PCB substrate, this mode is simply easily realized, and only needs a specific capacitor, at
This is lower.
A kind of method promoting NandFlash bus timing allowance provided in an embodiment of the present invention, by specific capacitor and bears
The corresponding load capacitance series connection of capacitance is carried, may include:
If specified point is located on each load branch of NandFlash bus, for any specified point, this is any
The corresponding specific capacitor calculated of specified point is integrated into load capacitance corresponding on the load branch that any specified point is located at
In grain encapsulation, to connect with the load capacitance in particle encapsulation.
If specified point is located on each load branch, for any one specified point, each ginseng is obtained in the specified point
The load capacitance for the load branch that numerical value and the specific capacitor being calculated should be located at the specified point is connected, each negative as a result,
It carries capacitor and is in series with a corresponding specific capacitor, this mode enables to result more accurate, namely is effectively ensured
The timing allowance of bus is promoted, and then improves the realization of admissible operating rate.Wherein, by specific capacitor and corresponding load electricity
Hold series connection can be by specific capacitor is integrated to corresponding load capacitance particle encapsulation in, with the quantity of load capacitance be two into
Row illustrates, then is integrated to specific capacitor in the particle encapsulation of corresponding load capacitance as shown in Figure 4, naturally it is also possible to according to
Actual needs is set, within the scope of the present invention.In addition, PCB substrate and particle encapsulation are and the prior art
The meaning of middle corresponding concept is consistent, and details are not described herein.
The embodiment of the invention also provides a kind of devices for promoting NandFlash bus timing allowance, as shown in figure 5, can
To include:
Module 11 is obtained, is used for: being obtained in NandFlash bus before the current voltage value at specified point current time, charging
Voltage value, charged voltage value, bus equivalent resistance and setting charging time value, set charging time value as the specified of setting
Time needed for the voltage value of point is changed to charged voltage value as voltage value before charging；
First computing module 12, is used for: equivalent based on voltage value, charged voltage value, bus before current voltage value, charging
Resistance value and setting charging time value calculate the bus equivalent capacitance value of NandFlash bus；
Second computing module 13, is used for: being calculated based on the load capacitance value of bus equivalent capacitance value and NandFlash bus
The capacitance of increased specific capacitor is needed, and specific capacitor load capacitance corresponding with load capacitance value is connected.
A kind of device promoting NandFlash bus timing allowance provided in an embodiment of the present invention, the first computing module can
To include:
First computing unit, is used for: the bus equivalent capacitance value of NandFlash bus is calculated according to the following formula:
Vt=V0+ (Vu-V0) * [1-exp (- t/RC)],
Wherein, V0 is voltage value before charging, and Vu is charged voltage value, and Vt is current voltage value, and t is the setting charging time
Value, R are bus equivalent resistance, and C is bus equivalent capacitance value；
Second computing module may include:
Second computing unit, is used for: the capacitance for needing increased specific capacitor is calculated according to the following formula:
C=(C1*C2)/(C1+C2),
Wherein, C1 is load capacitance value, and C2 is the capacitance of specific capacitor.
A kind of device promoting NandFlash bus timing allowance provided in an embodiment of the present invention, the second computing module can
To include:
First operating unit, is used for: if specified point is located at the main line of NandFlash bus, specific capacitor being buried
Enter in PCB substrate, is connected with the load capacitance group formed with whole load capacitances of NandFlash bus.
A kind of device promoting NandFlash bus timing allowance provided in an embodiment of the present invention, the second computing module can
To include:
Second operating unit, is used for: if specified point is located at each load branch of NandFlash bus, for
The corresponding specific capacitor calculated of any specified point is integrated on the load branch that any specified point is located at by any specified point
Load capacitance corresponding particle encapsulation in, to connect with the load capacitance in particle encapsulation.
The embodiment of the invention also provides a kind of equipment for promoting NandFlash bus timing allowance, may include:
Memory, for storing computer program；
Processor realizes that as above any one promotes NandFlash bus timing allowance when for executing computer program
The step of method.
The embodiment of the invention also provides a kind of computer readable storage medium, it is stored on computer readable storage medium
It is abundant that as above any one promotion NandFlash bus timing may be implemented in computer program when computer program is executed by processor
The step of method of amount.
It should be noted that it is provided in an embodiment of the present invention it is a kind of promoted NandFlash bus timing allowance device, set
The explanation of relevant portion refers to a kind of promotion provided in an embodiment of the present invention in standby and computer readable storage medium
The detailed description of corresponding part in the method for NandFlash bus timing allowance, details are not described herein.In addition the embodiment of the present invention
In the above-mentioned technical proposal of offer with correspond to the consistent part of technical solution realization principle and unspecified in the prior art, with
Exempt from excessively to repeat.
The foregoing description of the disclosed embodiments can be realized those skilled in the art or using the present invention.To this
A variety of modifications of a little embodiments will be apparent for a person skilled in the art, and the general principles defined herein can
Without departing from the spirit or scope of the present invention, to realize in other embodiments.Therefore, the present invention will not be limited
It is formed on the embodiments shown herein, and is to fit to consistent with the principles and novel features disclosed in this article widest
Range.
Claims (10)
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| CN201810843342.8A CN109086230A (en) | 2018-07-27 | 2018-07-27 | A kind of method and device promoting NandFlash bus timing allowance |
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| CN201810843342.8A CN109086230A (en) | 2018-07-27 | 2018-07-27 | A kind of method and device promoting NandFlash bus timing allowance |
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| CN103797537A (en) * | 2011-07-29 | 2014-05-14 | 美光科技公司 | Multi-device memory serial architecture |
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| CN107301147A (en) * | 2017-06-20 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of dynamic regulating method and device of I2C bus signals quality |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060044872A1 (en) * | 2004-09-02 | 2006-03-02 | Nazarian Hagop A | NAND flash depletion cell structure |
| US20100109627A1 (en) * | 2008-10-31 | 2010-05-06 | Akira Umezawa | Power circuit including step-up circuit and stabilizing method thereof |
| CN103797537A (en) * | 2011-07-29 | 2014-05-14 | 美光科技公司 | Multi-device memory serial architecture |
| CN104239629A (en) * | 2014-09-10 | 2014-12-24 | 浪潮(北京)电子信息产业有限公司 | Calculation method and device for I2C pull-up resistance |
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