CN109086249B - Analog vector-matrix multiplication circuit - Google Patents
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Abstract
The application provides an analog vector-matrix multiplication circuit which is realized by adopting a programmable memory device array, wherein in the programmable semiconductor device array, sources of all programmable semiconductor devices of each column are connected to the same analog voltage input end, N columns of programmable semiconductor devices are correspondingly connected with N analog voltage input ends, grids of all programmable semiconductor devices of each row are connected to the same bias voltage input end, M rows of programmable semiconductor devices are correspondingly connected with M bias voltage input ends, drains of all programmable semiconductor devices of each column are connected to the same analog current output end, N columns of programmable semiconductor devices are correspondingly connected with N analog current output ends, and each programmable semiconductor device is regarded as a variable equivalent analog weight by controlling threshold voltage of the programmable semiconductor device, so that a matrix multiplication function is realized.
Description
Technical Field
The application relates to the field of signal processing, in particular to an analog vector-matrix multiplication circuit.
Background
Matrix multiplication is widely applied to the fields of image processing, recommendation systems, data dimension reduction and other data mining, however, the traditional technical architecture and a serial-based mode only by a single computer are not suitable for the current requirement of mass data processing. Therefore, the operation scale of matrix multiplication is enlarged, the operation time is reduced, and the requirement of matrix decomposition algorithm for processing large-scale data is met. However, matrix multiplication has a high time complexity, and conventional matrix multiplication solves the product of the matrices by taking the inner product of the left matrix row and the right matrix column. Such algorithms may be implemented as distributed algorithms, but their performance is not optimistic. Another form for matrix multiplication is to perform an outer-row product operation on the columns of the left matrix and the corresponding right matrix, thereby obtaining partial results of the result matrix, and finally summing the partial results. Although this algorithm has a significant improvement in efficiency over conventional algorithms in terms of parallelization, it also presents a bottleneck that cannot be calculated when the matrix size is so large that the memory of a single machine cannot hold one row of the left matrix and one column of the right matrix.
Vector-matrix multiplication is a commonly used logical computation function. In a conventional von neumann computing architecture, a memory and a processor are physically separated, and are connected through a data bus, so that when vector-matrix multiplication operation is performed, vector data and matrix data to be processed need to be read out of the memory, transmitted to the processor for logic computation, and then a computation result is stored back into the memory. This way of computation consumes a lot of data bus bandwidth and transmission power consumption. Vector-matrix multiplication operations on analog signals are more complex. Firstly, analog signals are required to be converted into digital signals by analog-to-digital conversion and the like, the digital signals are stored in a memory, vector-matrix multiplication operation is carried out according to the processing procedure, and then the digital signals are converted into analog signals by digital-to-analog conversion and the like. Such analog vector-matrix multiplication results in greater power consumption and cost overhead, and poor processing performance. These problems are further exacerbated by the transmission and processing of large amounts of data with the advent of large data applications.
Disclosure of Invention
In view of this, the embodiment of the application provides an analog vector-matrix multiplication circuit, which solves the problem of poor processing performance of the existing matrix multiplication.
In order to achieve the above purpose, the application adopts the following technical scheme:
an analog vector-matrix multiplication circuit comprising: a plurality of analog voltage inputs, a programmable semiconductor device array, a plurality of bias voltage inputs, and a plurality of analog current outputs;
in the programmable semiconductor device array, the sources of all the programmable semiconductor devices of each column are connected to the same analog voltage input end, the programmable semiconductor devices of a plurality of columns are correspondingly connected to a plurality of analog voltage input ends, the gates of all the programmable semiconductor devices of each row are connected to the same bias voltage input end, the programmable semiconductor devices of a plurality of rows are correspondingly connected to a plurality of bias voltage input ends, the drains of all the programmable semiconductor devices of each column are connected to the same analog current output end, the programmable semiconductor devices of a plurality of columns are correspondingly connected to a plurality of analog current output ends, and the threshold voltage of each programmable semiconductor device is adjustable.
In one embodiment, the analog vector-matrix multiplication circuit further comprises:
and the programming circuit is connected with the source electrode, the grid electrode and/or the substrate of each programmable semiconductor device in the programmable semiconductor device array and is used for regulating and controlling the threshold voltage of the programmable semiconductor device.
In one embodiment, a programming circuit includes: the voltage generation circuit is used for generating a programming voltage or an erasing voltage, and the voltage control circuit is used for loading the programming voltage to the source electrode of the selected programmable semiconductor device or loading the erasing voltage to the grid electrode or the substrate of the selected programmable semiconductor device so as to regulate the threshold voltage of the programmable semiconductor device.
In one embodiment, the analog vector-matrix multiplication circuit further comprises:
and the controller is connected with the programming circuit and controls the number of the programmable semiconductor devices which are put into operation and the threshold voltage of each programmable semiconductor device by controlling the operation of the programming circuit.
In one embodiment, a controller includes: and the row-column decoder is used for gating the programmable semiconductor device to be programmed.
In one embodiment, the analog vector-matrix multiplication circuit further comprises: the conversion device is connected in front of the plurality of analog voltage input ends and is used for respectively converting the plurality of analog current input signals into analog voltage input signals and outputting the analog voltage input signals to the corresponding analog voltage input ends.
In one embodiment, the conversion device includes: a plurality of operational amplifiers and a plurality of programmable semiconductor devices connected to the plurality of operational amplifiers in one-to-one correspondence;
the inverting input terminal of each operational amplifier is connected to the drain electrode of the corresponding programmable semiconductor device, the non-inverting input terminal is connected to the first fixed bias voltage,
the output end of the operational amplifier is connected with the source electrode of the programmable semiconductor device and is connected with the corresponding analog voltage input end,
the gate of the programmable semiconductor device is connected to a first fixed bias voltage.
In one embodiment, the analog vector-matrix multiplication circuit further comprises: and the current detection output circuit is connected behind the analog current output end and is used for processing and outputting an analog current output signal output by the analog current output end.
In one embodiment, a current detection output circuit includes: and the non-inverting input end of each operational amplifier is connected with the second fixed bias voltage, the inverting input end of each operational amplifier is connected with the corresponding analog current output end, and a resistor or a transistor is connected between the inverting input end and the output end.
In one embodiment, the programmable semiconductor device employs a floating gate transistor.
The application also provides a control method of the analog vector-matrix multiplication circuit, which is used for the analog vector-matrix multiplication circuit and comprises the following steps:
based on the bit number requirement of matrix multiplication operation, the controller is utilized to control the number of programmable semiconductor devices put into operation;
regulating and controlling the threshold voltage of the programmable semiconductor device through a programming circuit;
applying a plurality of analog voltage input signals to sources of all programmable semiconductor devices of a corresponding column through a plurality of analog voltage input terminals;
applying a preset bias voltage to the gates of all programmable semiconductor devices of the corresponding row through a plurality of bias voltage input ends;
and obtaining a plurality of analog current output signals through a plurality of analog current output ends corresponding to the programmable semiconductor devices in a plurality of columns.
In one embodiment, the control method further comprises, before applying the plurality of analog voltage signals to the sources of all programmable semiconductor devices of the corresponding column through the plurality of analog voltage inputs:
the plurality of analog current input signals are respectively converted into a plurality of analog voltage input signals by a conversion device.
The application also provides a storage device which comprises the analog vector-matrix multiplication circuit.
The application also provides a chip comprising the analog vector-matrix multiplication circuit.
The application provides an analog vector-matrix multiplication circuit and a control method thereof, which dynamically adjusts the threshold voltage V of each programmable semiconductor device in advance according to a certain rule TH Each programmable semiconductor device can be considered as a variable equivalent analog weight,the programmable semiconductor device array stores an analog data array corresponding to storing the analog data; when the circuit works, a row of analog voltage vectors or a row of analog voltage vectors converted by the analog current vectors through the conversion device are applied to the source electrodes of the corresponding programmable semiconductor devices, so that the source electrodes of the programmable semiconductor devices obtain a voltage signal, the drain electrodes output an analog current output signal, according to the characteristics of the programmable semiconductor devices, the analog current output signal output by the drain electrodes of each programmable semiconductor device is equal to the voltage multiplied by the weight, and because the drain electrodes of all the programmable semiconductor devices in each column are connected to the same analog current output end, according to kirchhoff law, the analog current output signal at the analog current output end is the sum of the drain currents of all the programmable semiconductor devices in the column, namely the sum of the products of the source voltages and the weights of all the programmable semiconductor devices in the column, and a plurality of analog current output ends output the sum of the products of a plurality of source voltages and the weights, so that the matrix multiplication operation function is realized; the application realizes the analog vector-matrix multiplication operation by using the programmable semiconductor device array, and the processing performance of the analog vector-matrix multiplication operation circuit realized by using the programmable semiconductor device array is improved because the programmable semiconductor device has high integration level, high response speed and low power consumption, and the cost caused by analog-digital conversion, digital-analog conversion, data transmission and the like is effectively reduced.
In addition, the analog vector-matrix multiplication circuit provided by the application can be used as a flash memory or an electrically erasable programmable read-only memory when in an idle state, so that multiplexing of electrical elements is realized, the utilization efficiency of the elements is improved, and the hardware cost of an integrated circuit is saved.
In addition, the analog vector-matrix multiplication circuit provided by the application can accurately process and output the calculated current by arranging the current detection output circuit after the analog current output end or connect the current to the input of the next programmable semiconductor device array, so that the output current precision can be effectively improved.
The analog vector-matrix multiplication circuit is integrated on the storage device, vector-matrix multiplication is directly carried out on the analog signals in the storage device, data are not required to be transmitted back and forth between the memory and the processor, processing performance is improved, and power consumption and cost are reduced.
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first embodiment of an analog vector-matrix multiplication circuit according to the present application;
FIG. 2 is a diagram of floating gate transistors in an analog vector-matrix multiplication circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a second embodiment of the analog vector-matrix multiplication circuit of the present application;
FIG. 4 is a schematic diagram of a third embodiment of an analog vector-matrix multiplication circuit according to the present application;
fig. 5 is a flowchart of a control method of an analog vector-matrix multiplication circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Vector-matrix multiplication is a commonly used logic computation function, and the performance, power consumption and cost of the existing analog vector-matrix multiplication operation are required to be improved. According to the analog vector-matrix multiplication circuit provided by the application, each programmable semiconductor device is regarded as a variable equivalent analog weight by adjusting the threshold voltage of the programmable semiconductor device, which is equivalent to analog matrix data, and analog voltage is applied to the programmable semiconductor device array, so that the matrix multiplication function is realized, the circuit structure is simple, the number of components is small, the response speed is high, the power consumption is low, the cost caused by analog-digital conversion, digital-analog conversion, data transmission and the like is greatly reduced, and the processing performance is greatly improved.
FIG. 1 is a schematic diagram of a first embodiment of an analog vector-matrix multiplication circuit according to the present application. As shown in fig. 1, the analog vector-matrix multiplication circuit includes: n analog voltage inputs, an array of M rows by N columns of programmable semiconductor devices, M bias voltage inputs, and N analog current outputs.
In the programmable semiconductor device array, the sources of all programmable semiconductor devices in each column are connected to the same analog voltage input end, N columns of programmable semiconductor devices are correspondingly connected to N analog voltage input ends, the gates of all programmable semiconductor devices in each row are connected to the same bias voltage input end, M rows of programmable semiconductor devices are correspondingly connected to M bias voltage input ends, the drains of all programmable semiconductor devices in each column are connected to the same analog current output end, N columns of programmable semiconductor devices are correspondingly connected to N analog current output ends, and the threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, M is a positive integer greater than or equal to zero, and M and N can be equal or different.
Through the circuit connection mode, a topological structure of source electrode coupling and drain electrode summation is formed.
Wherein the threshold voltage V of each programmable semiconductor device is dynamically adjusted according to a certain rule in advance TH Each programmable semiconductor device can be considered as a variable equivalent analog weight (denoted as W k,j Wherein 0 is<k<M and 0<j<N represents a row number and a column, respectivelyNumber) corresponds to storing an analog data array, and the programmable semiconductor device array stores an analog data array
When the circuit works, one row of analog voltage signals V 1 ～V N Applied to N columns of programmable semiconductor devices respectively, wherein sources of all programmable semiconductor devices in the K column obtain an analog voltage signal V k A bias voltage V is input to the grid electrode b The drains respectively output current signals I k,1 ～I k,N Wherein, depending on the programmable semiconductor device characteristics, the drain output current of each programmable semiconductor device, i=v×w, is equal to the source voltage multiplied by the weight of the programmable semiconductor device, i.e., I k,1 ＝V k W k,1 ，I k,N ＝V k W k,N Since the drains of all programmable semiconductor devices of each column are connected to the same analog current output, the current I at the analog current output is according to kirchhoff's law j The sum of the drain currents of all programmable semiconductor devices for the column isMultiple analog current outputs outputting multiple current sumsThe matrix multiplication function is realized.
The application realizes the analog vector-matrix multiplication operation by using the programmable semiconductor device array, and the processing performance of the analog vector-matrix multiplication operation circuit realized by using the programmable semiconductor device is greatly improved because the programmable semiconductor device has high integration level, high response speed and low power consumption, and the cost caused by analog-digital conversion, digital-analog conversion, data transmission and the like is effectively reduced.
In addition, due to the gate-source voltage V of the programmable semiconductor device GS Determining an output current of the programmable semiconductor device, the output current of the programmable semiconductor deviceThe current is very sensitive to the source voltage, and calculation errors can be caused, but the embodiment adopts a topological structure of gate coupling and drain summation, so that calculation errors can not be caused even if the source voltage fluctuates, and the calculation accuracy can be improved.
In an alternative embodiment, the programmable semiconductor device may be implemented by using a floating gate transistor, where the floating gate transistor includes a substrate, an insulating layer, a gate G, a source S, a drain D, and a floating gate F, the floating gate is disposed between the gate and the insulating layer, the insulating layer is disposed between the floating gate and the substrate, and is used to protect electrons in the floating gate from leakage, and the floating gate may store electrons therein; by adjusting the number of electrons in the floating gate, the threshold voltage of the floating gate transistor is dynamically adjusted, which due to its structural characteristics can be regarded as a variable equivalent analog weight, storing an analog data.
In an alternative embodiment, the analog vector-matrix multiplication circuit may further include:
and the programming circuit is connected with the source electrode, the grid electrode and/or the substrate of each programmable semiconductor device in the programmable semiconductor device array and is used for regulating and controlling the threshold voltage of the programmable semiconductor device.
In a preferred embodiment, the programming circuit comprises: the voltage generation circuit is used for generating a programming voltage or an erasing voltage, and the voltage control circuit is used for loading the programming voltage to the source electrode of the selected programmable semiconductor device or loading the erasing voltage to the grid electrode or the substrate of the selected programmable semiconductor device so as to regulate the threshold voltage of the programmable semiconductor device.
Specifically, the programming circuit applies a high voltage to the source of the programmable semiconductor device according to the programmable semiconductor device threshold voltage requirement data using a hot electron injection effect to accelerate channel electrons to a high speed to increase the threshold voltage of the programmable semiconductor device.
And, the programming circuit applies a high voltage to the gate or the substrate of the programmable semiconductor device according to the programmable semiconductor device threshold voltage requirement data by utilizing the tunneling effect, thereby reducing the threshold voltage of the programmable semiconductor device.
In the first embodiment or the second embodiment, optionally, the analog vector-matrix multiplication circuit may further include:
the controller is connected with the programming circuit, and adjusts the number of the programmable semiconductor devices which are put into operation and the threshold voltage of each programmable semiconductor device by controlling the operation of the programming circuit so as to adapt to the operation requirement of matrix multiplication.
Preferably, the controller includes: and the row-column decoder is used for gating the programmable semiconductor device to be programmed.
In the first embodiment or the second embodiment, optionally, the analog vector-matrix multiplication circuit may further include: the bias voltage generating circuit is used for generating a preset bias voltage and inputting the preset bias voltage to the bias voltage input end, and it can be understood that the analog vector-matrix multiplication operation circuit can also be used for controlling the voltage generating circuit to generate the preset bias voltage and inputting the preset bias voltage to the bias voltage input end through the voltage generating circuit in the multiplexing programming circuit without arranging the bias voltage generating circuit.
FIG. 3 is a schematic diagram of a second embodiment of the analog vector-matrix multiplication circuit of the present application, which may further include, based on the entire contents of the first embodiment shown in FIG. 1: the conversion device 5 is connected to the front of the plurality of analog voltage input terminals, and is used for respectively converting the plurality of analog current input signals into analog voltage input signals and outputting the analog voltage input signals to the corresponding analog voltage input terminals.
In an alternative embodiment the conversion means 5 comprise a plurality of operational amplifiers and a plurality of programmable semiconductor devices connected in a one-to-one correspondence with the plurality of operational amplifiers.
The inverting input terminal of each operational amplifier is connected to the drain electrode of the corresponding programmable semiconductor device, the non-inverting input terminal is connected to the first fixed bias Vd,
the output end of the operational amplifier is connected with the source electrode of the programmable semiconductor device and is connected with the corresponding analog voltage input end,
the gate of the programmable semiconductor device is connected to a first fixed bias Vd. In this embodiment, the inverting input of the operational amplifier is used to receive the analog current input signal I in1 ～I inN 。
Alternatively, the programmable semiconductor device in the conversion means 5 may employ a floating gate transistor.
When the circuit works, one row of analog current is input into the signal I in1 ～I inN Converted into a row of analog voltage input signals V by conversion means 5 n ～V N And then applied to N columns of programmable semiconductor devices, respectively. By arranging the conversion device, the analog vector-matrix multiplication circuit in the embodiment of the application is suitable for analog voltage input signals and analog current input signals, and can be increased in applicability.
It should be noted that the implementation of the above-mentioned conversion device is only an example, and any circuit structure or circuit element that can convert a current input signal into a voltage input signal may be used to implement the conversion device, and it is understood that the programmable semiconductor device in the above-mentioned conversion device may also be implemented by using a resistor, a metal semiconductor field effect transistor, or the like.
FIG. 4 is a schematic diagram of a third embodiment of the analog vector-matrix multiplication circuit of the present application. As shown in fig. 4, the analog vector-matrix multiplication circuit may further include, in addition to the whole contents described in any one of the first and second embodiments, the following steps: and a current detection output circuit 6 connected after the analog current output terminal, for processing and outputting an analog current output signal outputted from the analog current output terminal.
The current detection output circuit is used for accurately processing and outputting the operated current or receiving the input of the next programmable semiconductor array, so that the accurate current output can be effectively realized.
In an alternative embodiment, the current detection output circuit may include: and the non-inverting input end of each operational amplifier is connected with the second fixed bias Vs, the inverting input end of each operational amplifier is connected with the corresponding analog current output end, and a resistor or a transistor or the like is connected between the inverting input end and the output end.
Wherein the second fixed bias is generally high voltage, and the operational amplifier controls the voltage of the analog current output terminal to be equal to the voltage of the non-inverting input terminal for ensuring the gate-source voltage V of the programmable semiconductor device GS The output voltage of the operational amplifier is controlled by the input voltage corresponding to the programmable semiconductor device only, so that the output voltage of the operational amplifier represents the amplitude of the output current of the programmable semiconductor device of the corresponding column.
The above is merely an example of a specific structure of each module in the analog vector-matrix multiplication circuit provided in the embodiment of the present application, and the specific structure of each module is not limited to the above structure provided in the embodiment of the present application, but may be other structures known to those skilled in the art, and is not limited herein.
The embodiment of the application also provides a control method of the analog vector-matrix multiplication circuit, which can be used for controlling the analog vector-matrix multiplication circuit described in the above embodiments, as described in the following embodiments. Since the principle of the control method for solving the problem is similar to that of the above-mentioned circuit, the implementation of the control method can be referred to the implementation of the above-mentioned circuit, and the repetition is not repeated.
As shown in fig. 5, the control method of the analog vector-matrix multiplication circuit is used for controlling each analog vector-matrix multiplication circuit, and the control method includes:
step S430: a plurality of analog voltage input signals are applied to the sources of all programmable semiconductor devices of the corresponding column through a plurality of analog voltage inputs.
Step S440: a predetermined bias voltage is applied to the gates of all programmable semiconductor devices of the corresponding row through a plurality of bias voltage inputs.
Step S450: and obtaining a plurality of analog current output signals through a plurality of analog current output ends corresponding to the programmable semiconductor devices in a plurality of columns.
Optionally, if the input signal is an analog current input signal, the conversion device 5 converts the plurality of analog current input signals into a plurality of analog voltage input signals, and then outputs the analog voltage input signals to the analog voltage input terminal for matrix-multiplication operation.
Optionally, the analog current output signal obtained for each column is: the product of the analog voltage input signal applied to the column and the weight of each programmable semiconductor device of the column is summed.
Preferably, the control method of the analog vector-matrix multiplication circuit further includes:
step S420: the threshold voltage of the programmable semiconductor device is regulated by a programming circuit.
Preferably, the control method further includes:
step S410: based on the bit number requirements of the matrix multiplication operation, the number of programmable semiconductor devices put into operation is controlled by a controller.
The embodiment of the application also provides a storage device which comprises the analog vector-matrix multiplication circuit. The analog vector-matrix multiplication circuit is integrated on the storage device, vector-matrix multiplication operation is directly carried out on the analog signals in the storage device, data are not required to be transmitted back and forth between the memory and the processor, processing performance is improved, and power consumption and cost overhead are reduced.
Preferably, the memory device is a flash memory or an eeprom.
Preferably, the flash memory is a NOR type flash memory.
The embodiment of the application also provides a chip which comprises the analog vector-matrix multiplication circuit.
In the above embodiments, the floating gate transistor may be a SONOS-gate transistor (floating-gate transistor), a Split-gate transistor (Split-gate floating-gate transistor), or a Charge-floating gate transistor (Charge-trapping floating-gate transistor), including but not limited to, all transistors capable of adjusting the threshold voltage of the transistor itself by adjusting the number of electrons in the floating gate are within the scope of the embodiments of the present application.
The analog vector-matrix multiplication circuit, the control method, the storage device and the chip of the embodiment of the application can be used for executing related operations in terminals such as computers, mobile phones and tablet computers, and other essential components of the analog vector-matrix multiplication circuit are all understood by those skilled in the art, and are not described herein in detail, and are not to be taken as limitations of the application.
By adjusting the threshold voltage of the programmable semiconductor devices, each programmable semiconductor device is regarded as a variable equivalent analog weight, which is equivalent to analog matrix data, and analog voltage is applied to the programmable semiconductor device array, so that the matrix multiplication operation function is realized, the circuit structure is simple, the number of components is small, the response speed is high, the power consumption is low, the cost caused by analog-to-digital conversion, digital-to-analog conversion, data transmission and the like is greatly reduced, and the processing performance of the operation circuit is effectively improved.
In addition, the analog vector-matrix multiplication circuit provided by the application can be used as a flash memory or an electrically erasable programmable read-only memory when in an idle state, so that multiplexing of electrical elements is realized, the utilization efficiency of the elements is improved, and the hardware cost of an integrated circuit is saved.
The analog vector-matrix multiplication circuit is integrated on the storage device, vector-matrix multiplication is directly carried out on the analog signals in the storage device, data are not required to be transmitted back and forth between the memory and the processor, processing performance is improved, and power consumption and cost are reduced.
The principles and embodiments of the present application have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (15)
1. An analog vector-matrix multiplication circuit, comprising: a plurality of analog voltage inputs, a programmable semiconductor device array, a plurality of bias voltage inputs, and a plurality of analog current outputs;
in the programmable semiconductor device array, the sources of all the programmable semiconductor devices of each column are connected to the same analog voltage input end, the programmable semiconductor devices of a plurality of columns are correspondingly connected to a plurality of analog voltage input ends, the gates of all the programmable semiconductor devices of each row are connected to the same bias voltage input end, the programmable semiconductor devices of a plurality of rows are correspondingly connected to a plurality of bias voltage input ends, the drains of all the programmable semiconductor devices of each column are connected to the same analog current output end, and the programmable semiconductor devices of a plurality of columns are correspondingly connected to a plurality of analog current output ends, wherein the threshold voltage of each programmable semiconductor device is adjustable;
adjusting the threshold voltage of each programmable semiconductor device to enable each programmable semiconductor device to store an analog weight, and enabling the programmable semiconductor device array to store an analog weight array;
a row of analog voltage signals are respectively applied to the sources of a plurality of columns of programmable semiconductor devices through a plurality of analog voltage input ends, a bias voltage is input to the gates of the programmable semiconductor devices through a bias voltage input end, the drain output current of each programmable semiconductor device is equal to the source voltage multiplied by the analog weight stored in the programmable semiconductor device, the current output by the analog current output end of one column of programmable semiconductor devices is the sum of the drain currents of all the programmable semiconductor devices in the column, and a plurality of analog current output ends output a plurality of current sums, so that the matrix multiplication operation function is realized.
2. The analog vector-matrix multiplication circuit of claim 1, further comprising:
and the programming circuit is connected with the source electrode, the grid electrode and/or the substrate of each programmable semiconductor device in the programmable semiconductor device array and is used for regulating and controlling the threshold voltage of the programmable semiconductor device.
3. The analog vector-matrix multiplication circuit of claim 2, wherein the programming circuit comprises: the voltage generation circuit is used for generating a programming voltage or an erasing voltage, and the voltage control circuit is used for loading the programming voltage to the source electrode of the selected programmable semiconductor device or loading the erasing voltage to the grid electrode or the substrate of the selected programmable semiconductor device so as to regulate the threshold voltage of the programmable semiconductor device.
4. The analog vector-matrix multiplication circuit of claim 3, further comprising:
and the controller is connected with the programming circuit and controls the number of the programmable semiconductor devices which are put into operation and the threshold voltage of each programmable semiconductor device by controlling the operation of the programming circuit.
5. The analog vector-matrix multiplication circuit of claim 4, wherein said controller comprises: and the row-column decoder is used for gating the programmable semiconductor device to be programmed.
6. The analog vector-matrix multiplication circuit of claim 1, further comprising: the conversion device is connected in front of the plurality of analog voltage input ends and is used for respectively converting a plurality of analog current input signals into analog voltage input signals and outputting the analog voltage input signals to the corresponding analog voltage input ends.
7. The analog vector-matrix multiplication circuit of claim 6, wherein said converting means comprises: a plurality of operational amplifiers and a plurality of programmable semiconductor devices connected to the plurality of operational amplifiers in one-to-one correspondence;
the inverting input terminal of each operational amplifier is connected to the drain electrode of the corresponding programmable semiconductor device, the non-inverting input terminal is connected to a first fixed bias voltage,
the output end of the operational amplifier is connected with the source electrode of the programmable semiconductor device and is connected with the corresponding analog voltage input end,
the gate of the programmable semiconductor device is connected to the first fixed bias voltage.
8. The analog vector-matrix multiplication circuit of claim 1, further comprising: and the current detection output circuit is connected behind the analog current output end and is used for processing and outputting an analog current output signal output by the analog current output end.
9. The analog vector-matrix multiplication circuit of claim 8, wherein the current sense output circuit comprises: and the non-inverting input end of each operational amplifier is connected with a second fixed bias voltage, the inverting input end of each operational amplifier is connected with the corresponding analog current output end, and a resistor or a transistor is connected between the inverting input end and the output end.
10. An analog vector-matrix multiplication circuit according to any of claims 1 to 9, wherein said programmable semiconductor device employs floating gate transistors.
11. A control method of an analog vector-matrix multiplication circuit, applied to the analog vector-matrix multiplication circuit according to any one of claims 1 to 10, comprising:
applying a plurality of analog voltage input signals to sources of all programmable semiconductor devices of a corresponding column through a plurality of analog voltage input terminals;
applying a preset bias voltage to the gates of all programmable semiconductor devices of the corresponding row through a plurality of bias voltage input ends;
obtaining a plurality of analog current output signals through a plurality of analog current output ends corresponding to the programmable semiconductor devices in a plurality of columns;
wherein if the input signal of the analog vector-matrix multiplication circuit is an analog current input signal, the control method further comprises:
the plurality of analog current input signals are respectively converted into a plurality of analog voltage input signals by a conversion device.
12. The control method of an analog vector-matrix multiplication circuit according to claim 11, further comprising:
the threshold voltage of the programmable semiconductor device is regulated by a programming circuit.
13. The control method of an analog vector-matrix multiplication circuit according to claim 11, further comprising:
based on the bit number requirements of the matrix multiplication operation, the number of programmable semiconductor devices put into operation is controlled by a controller.
14. A memory device comprising the analog vector-matrix multiplication circuit of any one of claims 1 to 10.
15. A chip comprising the analog vector-matrix multiplication circuit of any one of claims 1 to 10.
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| CN201810870540.3A CN109086249B (en) | 2018-08-02 | 2018-08-02 | Analog vector-matrix multiplication circuit |
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| CN201810870540.3A CN109086249B (en) | 2018-08-02 | 2018-08-02 | Analog vector-matrix multiplication circuit |
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| CN108763163B (en) * | 2018-08-02 | 2023-10-20 | 北京知存科技有限公司 | Analog vector-matrix multiplication circuit |
| CN111611534B (en) * | 2019-02-26 | 2023-12-01 | 北京知存科技有限公司 | Dynamic bias analog vector-matrix multiplication operation circuit and operation control method thereof |
| CN111611535A (en) * | 2019-02-26 | 2020-09-01 | 北京知存科技有限公司 | Anti-process deviation analog vector-matrix multiplication circuit |
| US11194886B2 (en) * | 2019-05-09 | 2021-12-07 | Applied Materials, Inc. | Bit-ordered binary-weighted multiplier-accumulator |
| CN110276047B (en) * | 2019-05-18 | 2023-01-17 | 南京惟心光电系统有限公司 | Method for performing matrix vector multiplication operation by using photoelectric calculation array |
| KR20210001574A (en) * | 2019-06-28 | 2021-01-06 | 에스케이하이닉스 주식회사 | Computation circuit for vector-matrix multiplication and semiconductor device including the computation circuit |
| CN111128279A (en) * | 2020-02-25 | 2020-05-08 | 杭州知存智能科技有限公司 | Memory computing chip based on NAND Flash and control method thereof |
| CN111579063B (en) * | 2020-04-11 | 2022-01-28 | 复旦大学 | Flexible light sensor |
| CN120763111A (en) * | 2020-10-01 | 2025-10-10 | 杭州知存算力科技有限公司 | Output-configurable memory integrated chip and electronic device |
| CN112632460B (en) * | 2020-12-20 | 2024-03-08 | 北京知存科技有限公司 | Source coupled drain summed analog vector-matrix multiplication circuit |
| CN114282164B (en) * | 2021-12-01 | 2024-07-16 | 北京大学 | Analog calculation matrix multiplication circuit and application thereof in DFT/IDFT |
| CN114528988B (en) * | 2022-02-28 | 2025-04-15 | 中国铁建重工集团股份有限公司 | A competitive neural network chip and its use method |
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