CN109087904B - Trimming resistor and preparation method thereof - Google Patents
Trimming resistor and preparation method thereof Download PDFInfo
- Publication number
- CN109087904B CN109087904B CN201810864142.0A CN201810864142A CN109087904B CN 109087904 B CN109087904 B CN 109087904B CN 201810864142 A CN201810864142 A CN 201810864142A CN 109087904 B CN109087904 B CN 109087904B
- Authority
- CN
- China
- Prior art keywords
- metal layer
- layer
- trimming
- metal
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009966 trimming Methods 0.000 title claims abstract description 165
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 332
- 239000002184 metal Substances 0.000 claims abstract description 332
- 238000002955 isolation Methods 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000002161 passivation Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 230000002829 reductive effect Effects 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 230000001133 acceleration Effects 0.000 claims description 4
- 230000009471 action Effects 0.000 claims description 4
- 239000007795 chemical reaction product Substances 0.000 claims description 4
- 238000010891 electric arc Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims 2
- 238000012360 testing method Methods 0.000 abstract description 24
- 239000010410 layer Substances 0.000 description 460
- 239000007788 liquid Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000008018 melting Effects 0.000 description 12
- 238000002844 melting Methods 0.000 description 12
- 239000010408 film Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 230000008439 repair process Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 229910001338 liquidmetal Inorganic materials 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001369 Brass Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a trimming resistor, which comprises a fuse area, wherein the fuse area comprises a substrate, an oxide layer formed on the substrate, an isolation layer formed on the oxide layer, a dielectric layer formed on part of the substrate, part of the oxide layer and the isolation layer, and a first groove formed on the isolation layer and positioned between the dielectric layers, the fuse wire structure comprises a fuse wire window positioned above a first groove and trimming windows positioned at two sides of the fuse wire window, a first metal layer formed on a dielectric layer, a second metal layer formed on the first metal layer positioned on the side wall of the first groove, a third metal layer formed on the first metal layer and the second metal layer, a fourth metal layer formed on the upper surface of the third metal layer positioned at two sides of the fuse wire window, and a passivation layer formed on the fourth metal layer, wherein a chamfer is formed between the side wall of the first groove and the bottom of the first groove, and a projection area of the fuse wire window, which is vertical to an isolation layer, is contained in an area where the isolation layer is positioned. The invention also provides a preparation method of the trimming resistor, and the trimming efficiency and the test precision are improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a trimming resistor and a preparation method thereof.
Background
Trimming resistors are generally classified into three categories, fuse, zener diode, and thin film resistor laser trimming. The fuse trimming resistor has relatively simple requirements on process level and test precision due to the blowing technology, is beneficial to production control, and has relatively mature and widely adopted technology. The fuse trimming resistors are mainly classified into metal and polycrystalline according to materials.
At present, the test of trimming resistance generally adopts the heavy current in the twinkling of an eye, according to the physical characteristic of conductor, will arouse the displacement gradually of metal atom when current density is very high (more than 104A/cm 2), make the metal appear cavity and pile up, this kind of phenomenon is called electromigration, electromigration's appearance has aggravated the increase of current density, according to the thermal conductance theory of conductor, the electron striking metal ion can produce the heat in the in-process that the electric current flows, and the size of heat and current density is directly proportional, the more concentrated the current density is bigger, the heat that produces is bigger, when the heat reaches the melting point of metal, the metal appears melting evaporation, circuit break after the metal melts, thereby reach the effect of trimming. When the trimming resistor is trimmed, instantaneous large current is needed to fuse the fuse, but the problem of short circuit caused by incomplete fusing of the fuse of the trimming resistor can also occur, so that trimming failure is caused, and trimming test of the trimming resistor is difficult to realize.
Disclosure of Invention
In view of the above, the present invention provides a trimming resistor with high reliability, which improves trimming efficiency and testing accuracy, and avoids short circuit of the trimming circuit, so as to solve the above existing problems. On one hand, the invention is realized by adopting the following technical scheme.
The invention provides a trimming resistor which comprises a fuse area, wherein the fuse area comprises a substrate, an oxide layer formed on the substrate, an isolation layer formed on the oxide layer, a dielectric layer formed on part of the substrate, part of the oxide layer and the isolation layer, at least two first grooves vertically formed on the isolation layer and positioned between the dielectric layers, a fuse window positioned above the first groove and trimming windows positioned at two sides of the fuse window, a first metal layer formed on the dielectric layer, a second metal layer formed on the first metal layer positioned at the side wall of the first groove, third metal layers formed on the first metal layer and the second metal layer, fourth metal layers formed on the upper surfaces of the third metal layers positioned at two sides of the fuse window at intervals, and a passivation layer formed on the fourth metal layer, and a chamfer is formed between the side wall of the first groove and the bottom of the first groove, the thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, and the projection area of the fuse window, which is vertical to the isolation layer, is contained in the area where the isolation layer is located.
The invention provides a trimming resistor which has the beneficial effects that: forming an oxide layer on a substrate, forming an isolation layer on the oxide layer, forming dielectric layers on part of the substrate, part of the oxide layer and the isolation layer, forming at least two first trenches vertically arranged at intervals on the isolation layer and between the dielectric layers, forming a fuse window above the first trenches and trimming windows on two sides of the fuse window, forming a first metal layer on the dielectric layers, forming a second metal layer on the first metal layer on the side wall of the first trenches, forming a third metal layer on the first metal layer and the second metal layer, forming a fourth metal layer on the upper surface of the third metal layer on two sides of the fuse window at intervals, forming a passivation layer on the fourth metal layer, and forming a chamfer between the side wall of the first trench and the bottom of the first trench, the thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, and a projection area of the fuse window, which is perpendicular to the isolation layer, is included in an area where the isolation layer is located. The isolation layer is formed on the oxide layer, the first groove is formed on the isolation layer, the substrate and the first groove are separated by the isolation layer, the phenomenon that when the fuse wire area is repaired subsequently, metal in the fuse wire area is melted into liquid to flow or splash to the oxide layer and the substrate to cause short circuit and repair failure is avoided, heat is generated in the repair process, the isolation layer prevents the liquid metal in the first groove from being conducted with the substrate, the substrate and a repair circuit are prevented from being damaged, and therefore reliability and repair efficiency of the repair resistor are improved. The third metal layer below the fuse window and located at the chamfer position is preferentially fused, and the thickness of the third metal layer is minimum, so that the required energy is less when the trimming resistor is trimmed, the trimming resistor is performed under low heat, the trimming test of the trimming resistor is easy to operate and realize, and the stability and the test precision of the trimming resistor are improved.
On the other hand, the invention also provides a preparation method of the trimming resistor, which comprises the following process steps:
s701: providing a substrate, and forming an oxide layer on the substrate;
s702: forming an isolation layer on the upper surface of the oxide layer;
s703: forming a dielectric layer on part of the substrate, the oxide layer and the isolation layer, photoetching the dielectric layer on the upper surface of the isolation layer, exposing the isolation layer at corresponding positions and forming at least two first grooves arranged at intervals and a fuse window positioned above the first grooves;
s704: forming a first metal layer on the dielectric layer, forming a second metal layer on the first metal layer on the side wall of the first trench, and forming a third metal layer on the first metal layer and the second metal layer;
s705: forming a fourth metal layer on the upper surface of the third metal layer positioned at two sides of the fuse window;
s706: forming a passivation layer on the upper surface of the fourth metal layer, photoetching the passivation layers on two sides of the fuse wire window, removing the fourth metal layer at a corresponding position, and exposing the third metal layer to form a trimming window;
s707: and photoetching the passivation layer below the fuse window, removing the fourth metal layer in the first groove to expose the third metal layer, forming a chamfer between the side wall of the first groove and the bottom of the first groove, wherein the thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, and the projection area of the fuse window, which is vertical to the isolation layer, is contained in the area where the isolation layer is located, and finally forming a trimming resistor.
The invention provides a preparation method of a trimming resistor, which comprises the steps of forming an oxide layer on a substrate, forming an isolation layer on the oxide layer, forming at least two first grooves arranged at intervals on the isolation layer, increasing a conducting path of a fuse wire area by changing the internal structure of the trimming resistor so that a third metal layer at the chamfer angle is preferentially fused when the trimming resistor is trimmed, wherein the metal in the fuse wire area is fused to generate liquid flowing or splashing to the isolation layer below the first grooves, and the isolation layer separates the metal in the first grooves from the substrate, so that the first metal layer and the third metal layer are prevented from being fused into the liquid state to be conducted with the substrate to generate short circuit and failure in trimming. The thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, so that the energy required during trimming test of the trimming resistor is less than that required during conventional test, and the thermal damage to the trimming circuit is reduced. The third metal layer in the first groove is melted preferentially to generate heat, the isolation layer can isolate a heat conduction path between the third metal layer and the substrate, the first metal layer at the bottom of the first groove is melted into liquid to flow or splash onto the isolation layer, the substrate is effectively prevented from being damaged by metal in the fuse wire area during trimming, a trimming circuit is prevented from being short-circuited, trimming efficiency and testing precision of the trimming resistor are improved, and preparation cost is reduced.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a top view of a trimming resistor according to the present invention;
FIG. 2 is a cross-sectional view taken along line A-A' of the trimming resistor of the present invention shown in FIG. 1;
FIGS. 3 to 11 are diagrams illustrating a process for manufacturing the trimming resistor according to the present invention;
FIG. 12 is a flow chart of a method for manufacturing the trimming resistor according to the present invention.
In the figure: trimming the resistor 1; a fuse region 2; a substrate 10; an oxide layer 20; an isolation layer 30; a dielectric layer 40; the first trench 41; a fuse window 42; a first metal layer 51; a second metal layer 52; the third metal layer 53; a fourth metal layer 54; a passivation layer 60; trimming window 61; chamfering 65; a circuit area 70; the second trench 72.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
Referring to fig. 1 and fig. 2, in one aspect, the invention provides a trimming resistor 1 including a fuse region 2, where the fuse region 2 includes a substrate 10, an oxide layer 20 formed on the substrate 10, an isolation layer 30 formed on the oxide layer 20, a dielectric layer 40 formed on a portion of the substrate 10, a portion of the oxide layer 20, and the isolation layer 30, at least two first trenches 41 vertically formed on the isolation layer 20 and between the dielectric layers 40, a fuse window 42 located above the first trench 41, and trimming windows 61 located at two sides of the fuse window 42, a first metal layer 51 formed on the dielectric layer 40, a second metal layer 52 formed on the first metal layer 51 at a sidewall of the first trench 41, a third metal layer 53 formed on the first metal layer 51 and the second metal layer 52, and a third metal layer 53 formed on the first metal layer 51 and the second metal layer 52, A fourth metal layer 54 formed on the upper surface of the third metal layer 53 at two sides of the fuse window 42 at intervals, a passivation layer 60 formed on the fourth metal layer 54, a chamfer 65 is formed between the sidewall of the first trench 41 and the bottom of the first trench 41, the thickness of the third metal layer 53 at the position of the chamfer 65 is smaller than that of the third metal layer 53 below the trimming window 61, and a projection area of the fuse window 42 perpendicular to the isolation layer 30 is included in an area where the isolation layer 30 is located.
The invention forms an oxide layer 20 on the substrate 10, forms an isolation layer 30 on the oxide layer 20, forms a dielectric layer 40 on a part of the substrate 10 and a part of the oxide layer 20 and the isolation layer 30, forms at least two first trenches 41 vertically arranged at intervals on the isolation layer 30 and between the dielectric layers 40, forms a fuse window 42 above the first trench 41 and forms trimming windows 61 at two sides of the fuse window 42, forms a first metal layer 51 on the dielectric layer 40, forms a second metal layer 52 on the first metal layer 51 at the side wall of the first trench 41, forms a third metal layer 53 on the first metal layer 51 and the second metal layer 52, forms a fourth metal layer 54 on the upper surface of the third metal layer 53 at two sides of the fuse window 42 at intervals, and forms a passivation layer 60 on the fourth metal layer 54, a chamfer 65 is formed between the sidewall of the first trench 41 and the bottom of the first trench 41, the thickness of the third metal layer 53 at the position of the chamfer 65 is smaller than the thickness of the third metal layer 53 below the trimming window 61, and the projection area of the fuse window 42 perpendicular to the isolation layer 30 is included in the area where the isolation layer 30 is located. The isolation layer 30 is formed on the oxide layer 20, the first trench 41 is formed on the isolation layer 30, the isolation layer 30 separates the substrate 10 from the first trench 41, so that when the trimming resistor 1 is subsequently trimmed, the metal in the fuse region 2 is prevented from being melted into a liquid state and flowing or splashing to the oxide layer 20 and the substrate 10 to cause short circuit and trimming failure, and meanwhile, heat is generated in the trimming process, the isolation layer 30 prevents the liquid metal in the first trench 41 from being conducted with the substrate 10, so that the substrate 10 and a trimming circuit are prevented from being damaged, and the reliability and the trimming efficiency of the trimming resistor 1 are improved. The third metal layer 53 below the fuse window 42 and located at the chamfer 65 is preferentially fused, and because the thickness of the third metal layer 53 is the smallest, the energy required for trimming the trimming resistor 1 is less, so that the trimming resistor 1 is performed under low heat, the trimming test of the trimming resistor 1 is easily realized, and the stability and the test precision of the trimming resistor 1 are improved.
Further, the trimming resistor 1 further includes a circuit area 70 located at one side of the fuse area 2 and connected to the fuse area 2, where the circuit area 70 includes at least two second trenches 72 disposed at intervals in the dielectric layer 40, a first metal layer 51 formed on the dielectric layer 40 and on an inner surface of the second trench 72, a second metal layer 52 filling the second trench 72, a third metal layer 53 formed on surfaces of the first metal layer 51 and the second metal layer 52, a fourth metal layer 54 formed on an upper surface of the third metal layer 53, and a passivation layer 60 formed on an upper surface of the fourth metal layer 54.
Further, the first metal layer 51, the third metal layer 53 and the fourth metal layer 54 in the circuit region 70 are separated from the first metal layer 51, the third metal layer 53 and the fourth metal layer 54 in the fuse region 2 by the passivation layer 60. When the trimming resistor 1 is trimmed, trimming failure caused by short circuit between the fuse area 2 and the circuit area 70 can be prevented, current is added to the third metal layer 53 below the trimming window of the fuse area 2, the third metal layer 53 below the fuse window 42 is melted, operation and implementation of subsequent trimming test are facilitated, and reliability of the trimming resistor 1 is improved.
The first trench 41 and the second trench 72 are preferably formed simultaneously, and the manufacturing processes of the circuit region 70 and the fuse region 2 are substantially the same, so that the manufacturing process flow can be reduced, and the manufacturing cost can be reduced. Preferably, the width of the second metal layer 52 in the second trench 72 is twice the width of the second metal layer 52 on one sidewall of the first trench 41 in a direction parallel to the upper surface of the substrate 10, so that when the second metal layer 52 is filled in the second trench 72 and the first trench 41, the second trench 72 is preferably filled, and the thickness of the second metal layer 52 on the sidewall of the first trench 41 is just the required thickness, so as to improve the efficiency and yield of the manufacturing by controlling the deposition into the first trench 41 to refer to controlling the manufacturing of the second metal layer 52. After the filling, the second metal layer 52 at the bottom of the first trench 41 is removed, and the second metal layer 52 formed on the sidewall of the first trench 41 is retained, so as to promote the poor step coverage of the third metal layer 53 deposited subsequently, so that the thickness of the third metal layer 53 in the first trench 41 is smaller than the thickness of the third metal layer 53 outside the first trench 41, and when the trimming resistor 1 is trimmed, the third metal layer 53 in the first trench 41 needs to be melted, because the thickness of the third metal layer 53 is relatively thin, the required energy is relatively small, and the trimming test of the trimming resistor 1 is easily realized.
Further, the area of the projection area of the isolation layer 30 in the direction perpendicular to the substrate 10 is smaller than the area of the projection area of the oxidation layer 20 in the direction perpendicular to the substrate 10. It can be understood that the isolation layer 30 serves as an etching barrier layer when the first trench 41 is formed, so as to prevent the substrate 10 from being damaged in the preparation process, meanwhile, the isolation layer 30 isolates the third metal layer 53 from the substrate 10, when the trimming resistor 1 is trimmed, the third metal layer 53 at the position of the chamfer 65 is melted and volatilized preferentially, so that the first metal layer 51 connected with the third metal layer 53 is melted into a liquid state and flows or splashes onto the isolation layer 30, and the isolation layer 30 blocks heat generated by melting of the first metal layer 51 from affecting the substrate 10, thereby improving the stability of the trimming resistor 1.
Further, the thickness of the third metal layer 53 under the trimming window 61 is ten times the thickness of the third metal layer 53 at the position of the chamfer 65. In this embodiment, the number of the first trenches 41 is preferably two, the coverage of depositing the third metal layer 53 into the first trenches 41 is poor, the side wall of the first trench 41 and the bottom of the first trench 41 form a chamfer 65, the thickness of the third metal layer 53 under the trimming window 61 is ten times of the thickness of the third metal layer 53 at the position of the chamfer 65, according to the physical characteristics of the conductor, the resistance value of the third metal layer 53 at the position of the chamfer 65 is ten times that of the third metal layer 53 below the trimming window 61, so that the energy required by the subsequent trimming test of the trimming resistor 1 is reduced, compared with the conventional trimming, only one tenth of energy is required to be provided to fuse the third metal layer 53 below the fuse window 42, and the condition that excessive heat is brought to surrounding components by high-energy trimming to cause component parameter drift is avoided. Moreover, because the thickness of the third metal layer 53 corresponding to the fuse window 42 is small, almost all the third metal layer 53 is evaporated and volatilized after being blown, and the situation that the third metal layer 53 is difficult to fuse due to backflow is effectively prevented.
Referring to fig. 3 to 11 and 12, in another aspect, the present invention further provides a method for manufacturing the trimming resistor 1, which includes the following steps:
s701: providing a substrate 10, and forming an oxide layer 20 on the substrate 10;
specifically, referring to fig. 3, a substrate 10 is provided, and an oxide layer 20 is formed on the substrate 10. The substrate 10 may be a silicon substrate, a silicon germanium substrate, a iii-v compound substrate 10, or other semiconductor material substrates 10 known to those skilled in the art, and silicon is used as the material of the substrate 10 in this embodiment. More specifically, a MOS field effect silicon-containing material, a silicon compound, or the like may be formed in the substrate 10 used in this embodiment, and the substrate 10 provided for a bipolar circuit is generally a substrate 10 of P (111) crystal orientation. There are various techniques for forming the oxide layer 20 on the surface of the substrate 10: thermal oxidation growth, thermal decomposition deposition, epitaxial growth, vacuum evaporation, reactive sputtering, anodic oxidation, and the like. The thermal growth oxidation is common in the integrated circuit process, the operation is simple, the oxide layer is dense, the oxide layer can be used as a diffusion masking layer, a localized or diffusion pattern and the like can be easily formed through photoetching, and the thermal growth oxidation is preferably used for forming the oxide layer 20 on the substrate 10 in the embodiment.
It can be understood that the oxide layer 20 grown on the substrate 10 can be used as a mask layer for preparing etching, and in the preparation process, the surface of the substrate 10 is also protected from the surrounding atmosphere, and the effect of protecting the substrate 10 in the subsequent preparation process improves the driving performance of the trimming resistor 1.
S702: forming an isolation layer 30 on the upper surface of the oxide layer 20;
specifically, referring to fig. 4, an isolation layer 30 is deposited on the oxide layer 20, and then both ends of the isolation layer 30 are etched, so that the isolation layer 30 in the middle of the oxide layer 20 is remained. In the present embodiment, the isolation layer 30 is silicon nitride, which is a high-temperature insoluble compound, has no melting point, and has strong high-temperature creep resistance, and since silicon nitride is a covalent compound with high bond strength and can form an oxide protective film in air, it also has good chemical stability, and is difficult to be oxidized at 1200 ℃ or below, and the formation of the protective film at 1200-1600 ℃ can prevent further oxidation and is difficult to be infiltrated or corroded by many molten metals or alloys such as aluminum, lead, tin, silver, brass, nickel, and the like, so that the isolation layer 30 isolates the third metal layer 53 from the substrate 10 when the third metal layer 53 is trimmed, and prevents the substrate 10 from being damaged by heat generated when the third metal layer 53 is melted, thereby improving the reliability and the test precision of the trimming resistor 1.
It can be understood that, in the present embodiment, the isolation layer 30 is formed on the oxide layer 20, the isolation layer 30 is located between the dielectric layer 40 and the oxide layer 20, the isolation layer 30 is made of silicon nitride with high stability, the oxide layer 20 and the substrate 10 are prevented from being damaged by over etching in a subsequent manufacturing process, the substrate 10 is isolated from the third metal layer 53 in the trimming test process of the trimming resistor 1, the third metal layer 53 is fused to be melted into a liquid state to flow or splash to the isolation layer 30 during trimming, the third metal layer 53 is prevented from being conducted with the substrate 10 to cause a short circuit and damage to the substrate 10, and reliability and driving performance of the trimming resistor 1 are enhanced.
S703: forming a dielectric layer 40 on the substrate 10, the oxide layer 20 and the upper surface of the isolation layer 30, and then performing photolithography on the dielectric layer 40 on the upper surface of the isolation layer 30 to expose the isolation layer 30 at corresponding positions and form at least two first trenches 41 and a fuse window 42 located above the first trenches 41;
specifically, referring to fig. 5, a dielectric layer 40 is formed on the upper surfaces of the substrate 10, the oxide layer 20 and the isolation layer 30, and then the dielectric layer 40 is planarized. In this embodiment, the dielectric layer 40 on the upper surface of the isolation layer 30 is subjected to photolithography by using a dry etching technique to form two first trenches 41 arranged at intervals and perpendicular to the isolation layer 30, the first trenches 41 are arranged at intervals to facilitate subsequent deposition of the third metal layer 53, and the third metal layer 53 meeting the requirements is prepared. The specific process of forming the first trench 41 is as follows: forming an etching barrier layer (not shown) on the dielectric layer 40 corresponding to the isolation layer 30, then coating a photoresist (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask having the first trench 41 pattern, and then developing to obtain the photoresist layer having the first trench 41 pattern. And etching the etching barrier layer by using the photoresist having the first trench 41 pattern as a mask and using an etching method such as a reactive ion etching method to form a pattern opening (not shown) of the first trench 41. And then, removing the area of the dielectric layer 40 which is not covered by the etching barrier layer by using the etching barrier layer with the first trench 41 pattern opening as a mask and adopting methods such as wet etching or dry etching and the like, thereby forming the first trench 41 in the dielectric layer 40. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, in order to ensure the exposure accuracy, an anti-reflection layer may be further formed between the photoresist layer and the etch stopper layer. In this embodiment, second trench 72 of circuit region 70 connected to dielectric layer 40 is formed when first trench 41 is formed, and in a direction parallel to substrate 10, width of second trench 72 is smaller than width of first trench 41, so as to facilitate subsequent formation of second metal layer 52 and formation of chamfer 65.
The dielectric layer 40 is mainly made of silicon dioxide, the silicon dioxide has good isolation performance compared with the common silicon dioxide, and the growth process of the dielectric layer 40 is as follows: the boron phosphorus silicon glass (CVD BPSG) film deposited by a chemical method replaces a conventional Phosphorus Silicon Glass (PSG) film to be used as the backflow dielectric layer 40, the backflow temperature can be reduced to be within 1000 ℃ and reach 800-950 ℃, so that redundant impurity diffusion and various defects caused by high temperature can be minimized, the boron phosphorus silicon glass has the characteristics of low backflow temperature, low internal stress and good insulation, cracks are difficult to occur even if a thicker film layer is subjected to subsequent heat treatment, and the corrosion rate is lower than that of the phosphorus silicon glass, so that the stability of the trimming resistor 1 is improved.
It can be understood that, in the embodiment, the dielectric layer 40 covers the isolation layer 30, the dielectric layer 40 is etched to form the first trench 41 perpendicular to the isolation layer 30, so as to facilitate subsequent preparation and deposition of the third metal layer 53 in the first trench 41, meanwhile, the dielectric layer 40 protects the substrate 10 from being damaged during the etching process, and the open fuse window 42 is arranged above the first trench 41, so that the fuse window 42 manufactured in the conventional process is saved, and the efficiency of the manufacturing process of the trimming resistor 1 is improved.
S704: forming a first metal layer 51 on the dielectric layer 40, forming a second metal layer 52 on the first metal layer 51 on the sidewall of the first trench 41, and forming a third metal layer 53 on the first metal layer 51 and the second metal layer 52;
specifically, referring to fig. 6, 7 and 8, a first metal layer 51 is formed on the dielectric layer 40 by using a physical vapor deposition technique, a second metal layer 52 is formed in the first trench 41 by using a chemical vapor deposition technique, the second metal layer 52 at the bottom of the first trench 41 is removed by etching, and the second metal layer 52 on the sidewall of the first trench 41 is remained. In this embodiment, the first metal layer 51 is titanium nitride, the second metal layer 52 is tungsten, and the specific process of forming the first metal layer 51 is as follows: under the vacuum condition, the low-voltage and large-current arc discharge technology is adopted, the evaporated titanium nitride is evaporated by utilizing the gas discharge target material and ionized with the gas, and the evaporated titanium nitride and the reaction product thereof are deposited on the dielectric layer 40 by utilizing the acceleration action of the electric field. When depositing the second metal layer 52 in the first trench 41, depositing the second metal layer 52 in the second trench 72 located on the dielectric layer 40, where the width of the second trench 72 is smaller than the width of the first trench 41 in a direction parallel to the substrate 10, so that when filling the second metal layer 52, the second trench 72 is preferably filled, but the first trench 41 is not filled. The second metal layer 52 is formed in the first trench 41 and the second trench 72 by using a chemical vapor deposition technique, and the thickness of the second metal layer 52 deposited in the first trench 41 is approximately equal to the width of the second trench 72, and is typically less than 0.5 μm, so as to facilitate the subsequent formation of the chamfer 65. In this embodiment, the number of the first trenches 41 is preferably two, and then a third metal layer 53 is deposited into the first trench 41 by using a physical vapor deposition technique, where the third metal layer 53 is aluminum, the third metal layer 53 is deposited at room temperature, and the aluminum has poor step coverage at room temperature, and the step coverage of the third metal layer 53 on the sidewall of the first trench 41 and the bottom of the first trench 41 is worse, and the thickness of the third metal layer 53 on the sidewall of the first trench 41 and the bottom of the first trench 41 is one tenth of the thickness of the corresponding third metal layer 53 on the dielectric layer 40, so that the subsequent control of the trimming energy and time of the trimming resistor 1 is facilitated, and the trimming efficiency of the trimming resistor 1 is improved.
It is understood that, in the present embodiment, the first metal layer 51 is titanium nitride, the second metal layer 52 is tungsten, the third metal layer 53 is aluminum, the thickness of the first metal layer 51 is 100-500A, the thickness of the second metal layer 52 is less than or equal to 0.5 μm, and the thickness of the third metal layer 53 is 0.3-0.6 μm. According to the different sizes of the first trench 41 and the second trench 72, the second metal layer 52 is chemically deposited, the second trench 72 is completely filled, and the first trench 41 is not filled, so that the time of the preparation process is conveniently controlled. Tungsten is a refractory metal with the highest melting point, and as a refractory metal, tungsten is good in high-temperature strength, has good corrosion resistance to molten alkali metal and steam, and the tungsten has oxide volatilization and liquid phase oxide only at the temperature of over 1000 ℃, so physical deposition is adopted at room temperature, titanium nitride has higher hardness than aluminum, has relatively stable compounds, and is difficult to react with common metals at high temperature, so that, when the trimming resistor 1 is trimmed, the third metal layer 53 on the second metal layer 52 melts to generate heat, and the second metal layer 52 on the sidewall of the first trench 41 separates the first metal layer 51 from the third metal layer 53, so that the dielectric layer 40 is prevented from being damaged by the molten third metal layer 53, the stability of the trimming circuit of the trimming resistor 1 is improved, and the reliability of the trimming resistor 1 is also improved.
S705: forming a fourth metal layer 54 on the upper surface of the third metal layer 53 at both sides of the fuse window 42;
specifically, referring to fig. 9 and 10, a fourth metal layer 54 is deposited on the upper surface of the third metal layer 53 on both sides of the fuse window 42 by using a physical vapor deposition technique, in this embodiment, the fourth metal layer 54 is titanium nitride, and the process of depositing the fourth metal layer 54 is as follows: under vacuum conditions, by adopting a low-voltage and large-current arc discharge technology, the evaporated titanium nitride and the gas are ionized by using the evaporation of the gas discharge target, and the evaporated titanium nitride and the reaction product thereof are deposited on the third metal layer 53 by using the acceleration action of the electric field. After the fourth metal layer 54 is formed, the fourth metal layer 54 of the circuit region 70, which is located on one side of the fuse region 2 and connected to the fuse region 2, is subjected to photolithography, the first metal layer 51, the third metal layer 53 and the fourth metal layer 54 at corresponding positions are removed, and the dielectric layer 40 is exposed at corresponding positions.
It can be understood that the fuse window 42 is located above the first trench 41, and the fourth metal layer 54 is formed on the third metal layer 53 on both sides of the fuse window 42 by using a physical vapor deposition technique, in this embodiment, the third metal layer 53 is aluminum, the fourth metal layer 54 is titanium nitride, aluminum is an active metal in the air and is easily oxidized, and titanium nitride is a metal compound with high stability, which effectively prevents aluminum from being oxidized or corroded, so as to improve the working performance of the trimming resistor 1, and the fourth metal layer 54 between the circuit region 70 and the fuse region 2 is etched, so as to prevent the fuse region 2 from being conducted with the circuit region 70 during trimming to cause a short circuit, which affects the trimming process.
S706: forming a passivation layer 60 on the upper surface of the fourth metal layer 54, performing photolithography on the passivation layers 60 on the two sides of the fuse window 42, removing the fourth metal layer 54 at the corresponding position, and exposing the third metal layer 53 to form a trimming window 61;
specifically, referring to fig. 11, a passivation layer 60 is formed on the fourth metal layer 54, and then the passivation layer 60 on both sides of the fuse window 42 is dry etched. In this embodiment, the process of forming the passivation layer 60 is as follows: the fourth metal layer 54 is reacted with an oxidizing substance to form a very thin, dense, well-covered passivation film on the surface of the fourth metal layer 54, which is a separate phase, typically a compound of an oxidized metal, that acts to completely separate the metal from the corrosive medium, preventing the metal from contacting the corrosive medium, thereby substantially stopping the dissolution of the fourth metal layer 54 to form a passive state, thereby protecting the metal from corrosion. In this embodiment, the specific process of forming the trimming window 61 is as follows: forming an etching barrier layer (not shown) on the passivation layer 60, then forming a photoresist layer (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask having the trimming window 61 pattern, and then developing to obtain the photoresist layer having the trimming window 61 pattern. And etching the etching barrier layer by using the photoresist with the pattern of the trimming window 61 as a mask and using an etching method such as a reactive ion etching method to form a pattern opening (not shown) of the trimming window 61. And then, removing the passivation layer 60 region which is not covered by the etching barrier layer by using the etching barrier layer with the pattern opening of the trimming window 61 as a mask through methods of wet etching, dry etching and the like, and further forming the trimming window 61 in the passivation layer 60. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, in order to ensure the exposure accuracy, an anti-reflection layer may be further formed between the photoresist layer and the etch stopper layer.
It is understood that the passivation layer 60 may be an oxide layer, or an oxide layer doped with phosphorus or boron, or silicon nitride, etc. as a protective layer. The passivation layer 60 is basically required to prevent the influence of harmful impurities on the device surface for a long time, the thermal expansion coefficient is matched with that of the silicon substrate, the growth temperature of the film is low, the uniformity of the components and the thickness of the passivation film is good, the pinhole density is low, and a gradual step is easily obtained after photoetching, so that the stability of the trimming resistor 1 is enhanced.
S707: and photoetching the passivation layer 60 positioned below the fuse window 42, removing the fourth metal layer 54 in the first trench 41 to expose the third metal layer 53, forming a chamfer 65 between the side wall of the first trench 41 and the bottom of the first trench 41, wherein the thickness of the third metal layer 53 positioned at the position of the chamfer 65 is smaller than that of the third metal layer 53 positioned below the trimming window 61, and the projection area of the fuse window 42, which is perpendicular to the isolation layer 30, is included in the area where the isolation layer 30 is positioned, and finally forming the trimming resistor 1.
Specifically, referring to fig. 11 again, it should be noted that in the present embodiment, the passivation layer 60 under the fuse window 42 is formed in the first trench 41 and between the sidewalls of the first trench 41, and the corresponding positions in the drawing are irregular patterns, so that those skilled in the art can understand the pattern. Firstly, photoresist is coated on two sides of the fuse window 42 to form a photoresist etching barrier layer, then, the passivation layer 60 below the fuse window 42 is subjected to dry etching to remove the fourth metal layer 54 in the first trench 41, and the passivation layer 60 and the fourth metal layer 54 between the first trenches 41 are also removed. In this embodiment, a corresponding metal layer is reserved between the bottom of the first trench 41 and the sidewall of the first trench 41 to form a chamfer 65, and the thickness of the third metal layer 53 at the position of the chamfer 65 is smaller than that of the third metal layer 53 outside the first trench 41, so as to facilitate the subsequent trimming test of the trimming resistor 1, and after the trimming resistor 1 is formed, all the photoresist is removed.
It can be understood that, in the embodiment, the passivation layer 60 and the fourth metal layer 54 under the fuse window 42 are removed, a chamfer 65 is formed between the bottom of the first trench 41 and the sidewall of the first trench 41, and the thickness of the third metal layer 53 at the position of the chamfer 65 is the smallest, so that trimming energy can be reduced to fuse the third metal layer 53 in a subsequent trimming test, thereby implementing the trimming test of the trimming resistor 1 and improving the trimming efficiency of the trimming resistor 1.
According to the physical characteristics of the conductor, the relationship between the current and the resistance follows ohm's law in the case of low current density, but when the current density is high (104A/cm)2Above), the transmission of mobile carriers will cause the gradual displacement of metal atoms in the third metal layer 53, so that the third metal layer 53 will have voids and accumulation to generate electromigration. When the material of the third metal layer 53 is aluminum, the current density is close to 5E104A/cm2The electromigration becomes obvious, and due to the occurrence of the electromigration, metal atoms gradually move out of the original crystal grain position, so that gaps are formed between adjacent crystal grains, the effective cross-sectional area of the lead is reduced, the current is concentrated to the rest part of the connecting line, the current density is increased, the electromigration also occurs to the rest part of the lead without the electromigration, and the more gaps occur until the lead is cut off. According to the thermal conduction theory of the conductor, in the process of current flowing, heat is generated due to electrons impacting metal ions, the heat is in direct proportion to the current density, the larger the current density is, the more concentrated the heat is, and when the heat reaches the melting point of the metal, the third metal layer 53 is melted and evaporated.
According to the simulation conclusion of the conductor, when the trimming resistor 1 is trimmed, the condition of instantaneous large current is generally adopted, along with the conduction of the instantaneous large current, when the electromigration conducting wire generates holes and accumulation in a very short time, the temperature is rapidly increased and reaches the melting point of the third metal layer 53 along with the rapid increase of heat, the electromigration rapidly occurs and reaches the melting point at the position where the current density is higher, the current of the third metal layer 53 is transferred to the adjacent un-fused area, the current density in the un-fused area is rapidly increased, and the electromigration and the rapid increase of the temperature are also generated immediately until the section of the third metal layer 53 is fused, so that the effect of trimming test is achieved.
In addition, according to the physical characteristics of the conductor and the conclusion of simulation, the trend and the density of the current are changed, the current is transmitted one by one, the transmission of the current is accumulated in the third metal layer 53, and the current density in the third metal layer 53 is maximum. Taking a two-dimensional simulation as an example, assuming that the width and thickness of the third metal layer 53 represented by an aluminum material are 1 μm, the current density on both sides of the third metal layer 53 is 1E106A/cm when the passing current is 10mA2The current density of the third metal layer 53 reached 5E106A/cm2Left and right. When the passing current is 100mA, the current density on both sides of the third metal layer 53 is 9E106A/cm2The current density of the third metal layer 53 reached 1.8E107A/cm2Left and right. Therefore, the adopted metals are often multi-layer composite titanium nitride, metal aluminum and the like, and the melting point of some refractory metals is even up to more than 2000 ℃. During the trimming of the trimming resistor 1, it often happens that aluminum is fused and refractory metal is still connected, or the third metal layer 53 is blown at the moment of trimming, but molten liquid aluminum may flow back to cause the two ends of the third metal layer 53 to be re-bridged and cause trimming failure. In this embodiment, the first metal layer 51 and the fourth metal layer 54 are made of titanium nitride, the second metal layer 52 is made of tungsten, the third metal layer is made of aluminum 53, the resistivity and the melting point of the third metal layer 53 are both lower than those of the first metal layer 51, the third metal layer 53 is preferably fused into a liquid state, and the third metal layer 53 flows or splashes to the first metal layer 51On the isolation layer 30, the isolation layer 30 isolates the conductive and thermal paths between the third metal layer 53 and the substrate 10, and then the first metal layer 51 melts into a liquid state under the heat generated by the third metal layer 53 and also flows or splashes to the isolation layer 30, because the isolation layer 30 is made of silicon nitride, the heat generated by melting the third metal layer 53 is prevented from affecting the substrate 10 and the trimming circuit, and therefore, the isolation layer 30 below the fuse window 42 can effectively prevent the substrate 10 from being damaged by the splashed liquid metal, and the manufacturing cost of the trimming resistor 1 is reduced.
According to the invention, the oxide layer 20 is formed on the substrate 10, the isolation layer 30 is formed on the oxide layer 20, at least two first trenches 41 arranged at intervals are formed on the isolation layer 30, and meanwhile, when the first trenches 41 are prepared, the fuse window 42 with an opening is arranged above the first trenches 41, so that the process flow for preparing the fuse window 42 is saved, and the preparation cost is reduced. By changing the structure inside the trimming resistor 1 and increasing the conductive path of the fuse region 2, when the trimming resistor 1 is trimmed, the third metal layer 53 at the position of the chamfer 65 is preferentially melted, the metal in the fuse region 2 melts and flows or splashes to the isolation layer 30 below the first trench 41, the isolation layer 30 separates the metal in the first trench 41 from the substrate 10, and the first metal layer 51 and the third metal layer 53 are prevented from melting into liquid state and being conducted with the substrate 10 to cause short circuit and failure in trimming. The thickness of the third metal layer 53 at the position of the chamfer 65 is smaller than that of the third metal layer 53 below the trimming window 61, so that the energy required during the trimming test of the trimming resistor 1 is less than that required in the conventional test, and the thermal damage to the trimming circuit is reduced. The third metal layer 53 in the first trench 41 is preferentially melted to generate heat, the isolation layer 30 can isolate a heat conduction path between the third metal layer 53 and the substrate 10, and the first metal layer 51 at the bottom of the first trench 41 is also melted into a liquid state to flow or splash onto the isolation layer 30, so that the substrate 10 is effectively prevented from being damaged by the third metal layer 53 during trimming, and the trimming efficiency and the test precision of the trimming resistor 1 are enhanced.
The above examples are merely representative of preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, various changes, modifications and substitutions can be made without departing from the spirit of the present invention, and these are all within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (4)
1. The preparation method of the trimming resistor is characterized by comprising the following process steps of:
s701: providing a substrate, and forming an oxide layer on the substrate;
s702: forming an isolation layer on the upper surface of the oxide layer;
s703: forming a dielectric layer on part of the substrate, the oxide layer and the isolation layer, photoetching the dielectric layer on the upper surface of the isolation layer, exposing the isolation layer at corresponding positions and forming at least two first grooves arranged at intervals and a fuse window positioned above the first grooves; the growth process of the dielectric layer is as follows: the boron-phosphorus-silicon glass film deposited by a chemical method is used as a reflux dielectric layer, and the reflux temperature is reduced to 800-950 ℃;
s704: forming a first metal layer on the dielectric layer, forming a second metal layer on the first metal layer on the side wall of the first groove by adopting a chemical vapor deposition technology, etching to remove the second metal layer at the bottom of the first groove, and reserving the second metal layer on the side wall of the first groove; forming a third metal layer on the first metal layer and the second metal layer by adopting a physical vapor deposition technology; the first metal layer is titanium nitride, the second metal layer is tungsten, and the third metal layer is aluminum; the thickness of the third metal layer on the side wall of the first groove and the bottom of the first groove is one tenth of that of the corresponding third metal layer on the dielectric layer; the specific process for forming the first metal layer is as follows: under the vacuum condition, adopting the low-voltage and high-current arc discharge technology, evaporating by using a gas discharge target material, ionizing the evaporated titanium nitride and gas, and depositing the evaporated titanium nitride and reaction products thereof on the dielectric layer by using the acceleration action of an electric field;
s705: forming a fourth metal layer on the upper surface of the third metal layer positioned at two sides of the fuse window; the fourth metal layer is titanium nitride; the process of depositing and forming the fourth metal layer comprises the following steps: under the vacuum condition, adopting the low-voltage and high-current arc discharge technology, evaporating by using a gas discharge target material, ionizing the evaporated titanium nitride and gas, and depositing the evaporated titanium nitride and reaction products thereof on the third metal layer by using the acceleration action of an electric field;
s706: forming a passivation layer on the upper surface of the fourth metal layer, photoetching the passivation layers on two sides of the fuse wire window, removing the fourth metal layer at a corresponding position, and exposing the third metal layer to form a trimming window; the specific process for forming the trimming window comprises the following steps: forming an etching barrier layer on the passivation layer, then forming a photoresist layer on the etching barrier layer, then exposing the photoresist layer by adopting a mask plate with the trimming window pattern, and then developing to obtain the photoresist layer with the trimming window pattern; etching the etching barrier layer to form a pattern opening of the trimming window by using the photoresist with the trimming window pattern as a mask and adopting a reactive ion etching method; then, taking the etching barrier layer with the trimming window pattern opening as a mask, and removing the passivation layer region which is not covered by the etching barrier layer by adopting a wet etching or dry etching method so as to form the trimming window in the passivation layer;
s707: photoetching the passivation layer below the fuse window, removing the fourth metal layer in the first groove to expose the third metal layer, forming a chamfer between the side wall of the first groove and the bottom of the first groove, wherein the thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, the projection area of the fuse window, which is vertical to the isolation layer, is included in the area where the isolation layer is located, and finally forming a trimming resistor;
the preparation method further comprises the steps of forming at least two second grooves which are arranged on the dielectric layer at intervals, wherein the second grooves are formed simultaneously with the first grooves, the first metal layer and the second metal layer are deposited in the first grooves and the second grooves simultaneously, and the width of the second metal layer in the second grooves is twice as large as that of the second metal layer on one side wall of the first grooves in the direction parallel to the upper surface of the substrate;
the trimming resistor prepared according to the method comprises a fuse area, wherein the fuse area comprises a substrate, an oxide layer formed on the substrate, an isolation layer formed on the oxide layer, a dielectric layer formed on part of the substrate, part of the oxide layer and the isolation layer, at least two first grooves vertically formed on the isolation layer and positioned between the dielectric layers, a fuse window positioned above the first groove and trimming windows positioned at two sides of the fuse window, a first metal layer formed on the dielectric layer, a second metal layer formed on the first metal layer on the side wall of the first groove, third metal layers formed on the first metal layer and the second metal layer, fourth metal layers formed on the upper surfaces of the third metal layers at two sides of the fuse window at intervals, and a passivation layer formed on the fourth metal layer, and a chamfer is formed between the side wall of the first groove and the bottom of the first groove, the thickness of the third metal layer at the chamfer position is smaller than that of the third metal layer below the trimming window, and the projection area of the fuse window, which is vertical to the isolation layer, is contained in the area where the isolation layer is located.
2. A trimming resistor made according to the method of claim 1, wherein: the trimming resistor further comprises a circuit area which is located on one side of the fuse area and connected with the fuse area, and the circuit area comprises at least two second grooves which are arranged on the dielectric layer at intervals, a first metal layer which is formed on the dielectric layer and on the inner surface of the second groove, a second metal layer which fills the second grooves, a third metal layer which is formed on the surfaces of the first metal layer and the second metal layer, a fourth metal layer which is formed on the upper surface of the third metal layer and a passivation layer which is formed on the upper surface of the fourth metal layer.
3. The trimming resistor according to claim 2, characterized in that: the first metal layer, the third metal layer and the fourth metal layer in the circuit area are separated from the first metal layer, the third metal layer and the fourth metal layer in the fuse area by the passivation layer.
4. The trimming resistor according to claim 2, characterized in that: the area of a projection area of the isolation layer in the direction perpendicular to the substrate is smaller than the area of a projection area of the oxidation layer in the direction perpendicular to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810864142.0A CN109087904B (en) | 2018-08-01 | 2018-08-01 | Trimming resistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810864142.0A CN109087904B (en) | 2018-08-01 | 2018-08-01 | Trimming resistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109087904A CN109087904A (en) | 2018-12-25 |
| CN109087904B true CN109087904B (en) | 2021-02-09 |
Family
ID=64831161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810864142.0A Expired - Fee Related CN109087904B (en) | 2018-08-01 | 2018-08-01 | Trimming resistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109087904B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094188A (en) * | 2011-10-31 | 2013-05-08 | 北大方正集团有限公司 | Method for manufacturing fuse wire window on core and fuse wire window |
| CN103337492A (en) * | 2013-06-21 | 2013-10-02 | 杭州士兰集成电路有限公司 | Trimming structure for reducing fuse wire hillocks and manufacturing method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672905A (en) * | 1992-08-26 | 1997-09-30 | At&T Global Information Solutions Company | Semiconductor fuse and method |
| US6160302A (en) * | 1998-08-31 | 2000-12-12 | International Business Machines Corporation | Laser fusible link |
| JP3275875B2 (en) * | 1999-04-16 | 2002-04-22 | 日本電気株式会社 | Semiconductor device |
| CN100388436C (en) * | 2002-05-15 | 2008-05-14 | 台湾积体电路制造股份有限公司 | metal fuse structure of semiconductor component and manufacturing method thereof |
| US6753210B2 (en) * | 2002-09-17 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company | Metal fuse for semiconductor devices |
-
2018
- 2018-08-01 CN CN201810864142.0A patent/CN109087904B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094188A (en) * | 2011-10-31 | 2013-05-08 | 北大方正集团有限公司 | Method for manufacturing fuse wire window on core and fuse wire window |
| CN103337492A (en) * | 2013-06-21 | 2013-10-02 | 杭州士兰集成电路有限公司 | Trimming structure for reducing fuse wire hillocks and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109087904A (en) | 2018-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6910907B2 (en) | Contact for use in an integrated circuit and a method of manufacture therefor | |
| US8383507B2 (en) | Method for fabricating air gap interconnect structures | |
| US10361115B2 (en) | Reducing contact resistance in vias for copper interconnects | |
| US12266568B2 (en) | Interconnect wires including relatively low resistivity cores | |
| TWI449156B (en) | Semiconductor device and method of forming same | |
| US10643887B2 (en) | Method of manufacturing damascene thin-film resistor (TFR) in poly-metal dielectric | |
| JPH08330504A (en) | Method of manufacturing integrated circuit having embedded conductor | |
| US5414404A (en) | Semiconductor device having a thin-film resistor | |
| CN109065522A (en) | Trim resistance and preparation method thereof | |
| CN109087904B (en) | Trimming resistor and preparation method thereof | |
| KR100250744B1 (en) | Forming method of the polycide layer in a semiconductor device | |
| CN109037191B (en) | Trimming resistor and method of making the same | |
| US6228735B1 (en) | Method of fabricating thin-film transistor | |
| US7537969B2 (en) | Fuse structure having reduced heat dissipation towards the substrate | |
| KR100517350B1 (en) | Method for fabricating hybrid metal interconnect | |
| KR100338092B1 (en) | Manufacturing method of semiconductor device | |
| US20040063295A1 (en) | One-mask process flow for simultaneously constructing a capacitor and a thin film resistor | |
| US20170207209A1 (en) | Integrated circuits with high voltage and high density capacitors and methods of producing the same | |
| JPH088223B2 (en) | Integrated circuit manufacturing method | |
| KR20110033491A (en) | Fuse in semiconductor device and manufacturing method thereof | |
| JP2003258104A (en) | Semiconductor device and method of manufacturing the same | |
| KR20020046690A (en) | method for forming dual damascene semiconductor device | |
| JPH088342A (en) | Semiconductor device and manufacturing method thereof | |
| KR19990025398A (en) | Metal wiring formation method of semiconductor device | |
| KR20000070047A (en) | Method of forming low temperature metal fill regions for ohmic contacts and for via openings between spaced apart metal layers and semiconductor structure fabricated |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20210105 Address after: No.29, 4th floor, unit 1, building 1, No.28 Jinji South Road, Wuhou District, Chengdu, Sichuan 610000 Applicant after: Chengdu Guangqi electromechanical equipment Engineering Co.,Ltd. Address before: 518000 building 902, block 8, sijiyu garden, Liantang street, Luohu District, Shenzhen City, Guangdong Province Applicant before: SHENZHEN NANSHUO MINGTAI TECHNOLOGY Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210209 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |