CN109103173A - The encapsulating structure and preparation method thereof that filter chip is embedded and set on pin - Google Patents
The encapsulating structure and preparation method thereof that filter chip is embedded and set on pin Download PDFInfo
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- CN109103173A CN109103173A CN201810909243.5A CN201810909243A CN109103173A CN 109103173 A CN109103173 A CN 109103173A CN 201810909243 A CN201810909243 A CN 201810909243A CN 109103173 A CN109103173 A CN 109103173A
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- layer
- cofferdam
- insulating layer
- package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
本发明揭示了一种滤波器芯片内嵌且引脚上置的封装结构及其制作方法，封装结构包括：封装基板，其具有腔室，且基板上表面的一侧具有若干外部引脚；滤波器芯片，设置于腔室内，第一上表面与基板上表面位于同侧，且第一上表面具有第一电极；功能芯片，设置于封装基板的上方，第二下表面与基板上表面面对面设置，且第二上表面具有第二电极；若干互连结构，用于导通第一电极、第二电极及外部引脚。本发明利用封装技术将两个芯片封装于同一封装基板，实现多芯片的高度集成；滤波器芯片及功能芯片呈上下分布，位于封装基板上方的功能芯片并不占用封装基板的空间，提高基板利用率，简化互连结构；滤波器芯片内嵌设置于腔室中，使得封装结构更加轻薄。
The invention discloses a packaging structure with built-in filter chips and pins on top and a manufacturing method thereof. The packaging structure includes: a packaging substrate with a cavity, and a plurality of external pins on one side of the upper surface of the substrate; The device chip is arranged in the chamber, the first upper surface and the upper surface of the substrate are located on the same side, and the first upper surface has a first electrode; the functional chip is arranged above the packaging substrate, and the second lower surface is arranged face to face with the upper surface of the substrate , and the second upper surface has a second electrode; several interconnection structures are used to connect the first electrode, the second electrode and the external pin. The present invention uses packaging technology to package two chips in the same packaging substrate to achieve high integration of multiple chips; the filter chip and the functional chip are distributed up and down, and the functional chip located above the packaging substrate does not occupy the space of the packaging substrate, which improves the utilization of the substrate. High efficiency, simplifying the interconnection structure; the filter chip is embedded in the cavity, making the package structure lighter and thinner.
Description
Technical field
The encapsulation knot set on embedded and pin the present invention relates to field of semiconductor package more particularly to a kind of filter chip
Structure and preparation method thereof.
Background technique
To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component, receiving unit are needed
It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with
Reduce the size of hardware system.
For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry
More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips
Layout etc..
Summary of the invention
The encapsulating structure set on embedded and pin the purpose of the present invention is to provide a kind of filter chip and its production side
Method.
One of for achieving the above object, an embodiment of the present invention provides that a kind of filter chip is embedded and on pin
The encapsulating structure set, comprising:
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber, and
The side of the upper surface of base plate has several external pins；
Filter chip is set in the chamber, the filter chip have the first upper surface for being oppositely arranged and
First lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several the
One electrode；
Functional chip, is set to the top of the package substrate, and the functional chip has table on second be oppositely arranged
Face and the second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface has
Several second electrodes；
Several interconnection structures, for several first electrodes, several second electrodes and several external pins to be connected.
As the further improvement of an embodiment of the present invention, the external pin is located at the functional chip far from described
The side of package substrate.
As the further improvement of an embodiment of the present invention, the interconnection structure includes metal column and electroplated layer structure,
The metal column is connected the second electrode, and the first electrode, the metal column and described outer is connected in the electroplated layer structure
Portion's pin.
As the further improvement of an embodiment of the present invention, the electroplated layer structure includes the upper rewiring of mutual conduction
Layer, top reroute layer and connecting column, and the top reroutes the top that layer is located at second upper surface, and top weight
The metal column is connected in wiring layer and the external pin, the upper rewiring layer are located at second lower surface and the substrate
Between upper surface, the first upper surface, and the first electrode is connected in the upper rewiring layer, and the connecting column connection is described heavy
Wiring layer and the top reroute layer.
As the further improvement of an embodiment of the present invention, the encapsulating structure include positioned at the upper surface of base plate,
The upper heavy of the first electrode is connected by the hole on first insulating layer in the first insulating layer above first upper surface
Wiring layer, the second insulating layer for connecting first insulating layer and second lower surface, the second insulating layer have fluting,
The fluting exposes the upper rewiring layer and the connecting column is supplied to connect.
As the further improvement of an embodiment of the present invention, first insulating layer and the second insulating layer cooperate shape
At cofferdam, the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, and the cofferdam includes being located at
The first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, first cofferdam with it is described
Second lower surface, first upper surface cooperate and enclose to set to form cavity, and second cofferdam is enclosed towards far from described first
The lateral border that the direction on weir extends up to second cofferdam is flushed with the lateral border of the package substrate.
As the further improvement of an embodiment of the present invention, it includes that the first top reroutes layer that the top, which reroutes layer,
And second top reroute layer, the encapsulating structure further include coat the second insulating layer be exposed to outer surface area,
The functional chip, the metal column and the connecting column and with first through slot and second through slot the first plastic packaging layer,
The upper first top weight for rerouting layer, the metal column is connected through slot through slot, described second by described first
Wiring layer, cladding the first plastic packaging layer and first top reroute the third insulating layer of layer, insulate by the third
The hole of layer and be connected first top reroute layer the second top reroute layer and the cladding third insulating layer and
Second top reroutes the 4th insulating layer of layer, and external pin connection second top reroutes layer, and described
External pin described in 4th insulating layer exposing, wherein described first through the slot connection fluting and for accommodating the connection
Column, described second is used to accommodate the metal column through slot, and the first plastic packaging layer is located at the package substrate far from the base
The side of plate lower surface.
It is the gap of the filter chip and the chamber, described as the further improvement of an embodiment of the present invention
Base lower surface and first lower surface are provided with the second plastic packaging layer, and first upper surface and the upper surface of base plate are neat
It is flat.
One of for achieving the above object, an embodiment of the present invention provides that a kind of filter chip is embedded and on pin
The production method for the encapsulating structure set, comprising steps of
S1: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S2: in forming chamber on the package substrate；
S3: providing filter chip, and the filter chip has the first upper surface and the first lower surface being oppositely arranged,
First upper surface has several first electrodes；
S4: the filter chip is loaded to the chamber, first upper surface is located at the upper surface of base plate
It is ipsilateral；
S5: in forming the first interconnection structure on the package substrate, the first electrode is connected in first interconnection structure；
S6: providing functional chip, and the functional chip has the second upper surface and the second lower surface being oppositely arranged, and institute
The second upper surface is stated with several second electrodes；
The functional chip: being loaded into the top of the package substrate by S7, on second lower surface and the substrate
Surface is arranged face-to-face, and forms the second interconnection structure that the second electrode and first interconnection structure is connected；
S8: forming the third interconnection structure of conducting external pin and first interconnection structure, and the external pin is located at
The side of the upper surface of base plate.
As the further improvement of an embodiment of the present invention, step S4 is specifically included:
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The filter chip is loaded to the chamber, first upper surface and the upper surface of base plate are located at together
Side；
Form gap, the base lower surface and first lower surface for coating the filter chip and the chamber
The second plastic packaging layer；
Remove the interim jointing plate；
Invert the package substrate；
Step S5 is specifically included:
The first insulating layer is laid in the upper surface of base plate；
It is formed in the top of first insulating layer and the first electrode is connected by the hole on first insulating layer
Upper rewiring layer；
In first insulating layer, it is described it is upper reroute layer top lay second insulating layer, first insulating layer and
The second insulating layer cooperatively forms cofferdam, and the cofferdam includes the first cofferdam and the second cofferdam, and first cofferdam is located at sky
The lateral border of the periphery of chamber, second cofferdam is flushed with the lateral border of the package substrate, and the cofferdam, which has, exposes institute
State the fluting for rerouting layer；
In forming connecting column in the fluting；
Step S7, S8 is specifically included:
Metal column is formed in the upper surface of the second electrode；
The functional chip is loaded into the top of the package substrate, second lower surface and the upper surface of base plate
Setting face-to-face, first cofferdam and second lower surface, first upper surface mutual cooperation and enclosing set to be formed it is corresponding
The cavity of the protection zone；
The first plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the first plastic packaging layer is same
When coat second cofferdam and be exposed to outer surface area, the functional chip, the metal column and the connecting column；
It grinds the first plastic packaging layer and exposes the metal column and the connecting column；
The first top rewiring that the metal column and the connecting column is connected is formed in the top of the first plastic packaging layer
Layer；
Third insulating layer is formed in the top that the first plastic packaging layer and first top reroute layer；
It is formed above the third insulating layer by hole conducting the first top weight on the third insulating layer
Second top of wiring layer reroutes layer；
Form the 4th insulating layer for coating the third insulating layer and the second top rewiring layer, the 4th insulation
Layer exposes second top and reroutes layer；
Layer, which is rerouted, in the second top for being exposed to outer forms ball grid array.
Compared with prior art, the beneficial effects of the present invention are: an embodiment of the present invention using encapsulation technology by two
The highly integrated of multi-chip may be implemented in same package substrate in a different chip package, improves the utilization rate of package substrate,
And then realize the miniaturization of encapsulating structure；In addition, filter chip and functional chip are located above package substrate in distribution up and down
Functional chip and be not take up the space of package substrate, can be further improved the utilization rate of package substrate, and filter chip
And the spacing between functional chip becomes smaller, the interconnection being easy to implement between filter chip and functional chip, simplifies interconnection structure；
It is set in chamber moreover, filter chip is embedded, so that encapsulating structure is more frivolous.
Detailed description of the invention
Fig. 1 is an exemplary RF front-end module of the invention；
Fig. 2 is another exemplary RF front-end module of the present invention；
Fig. 3 is the cross-sectional view of the encapsulating structure of an embodiment of the present invention；
Fig. 4 is the schematic diagram of the cofferdam cooperation first electrode of an embodiment of the present invention；
The step of Fig. 5 is the production method of the encapsulating structure of an embodiment of the present invention figure；
Fig. 6 a to Fig. 6 z-16 is the flow chart of the production method of the encapsulating structure of an embodiment of the present invention.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1 and Fig. 2, an embodiment of the present invention provides a kind of general RF front-end module, and RF front-end module can
For in the mobile devices such as mobile phone, computer either other electronic equipments.
In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200
Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list
Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.
In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower
Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.
In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module
Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected
(LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low noise
It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301,
Device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 are separately connected
Second amplifier unit 3011 and the 2nd RF filter cell 302.
In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal
For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise
It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.
It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects
Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize
Various functions.
Present embodiment is said by taking RF switch chip, amplifier chip, the encapsulating structure of filter chip, technique as an example
It is bright.
Join Fig. 3, the filter chip for an embodiment of the present invention is embedded and pin on the section view of encapsulating structure 100 set
Figure.
Encapsulating structure 100 includes package substrate 10, filter chip 20, functional chip 30 and several interconnection structures 50.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and package substrate 10 has chamber
101, and the side of upper surface of base plate 11 has several external pins 121.
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
Chamber 101 can be the through hole through package substrate 10, and but not limited to this.
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical
Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121
For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
In addition, here by taking several external pins 121 are located at side of the functional chip 30 far from package substrate 10 as an example, but not
As limit, external pin 121 may be alternatively located at other regions.
Filter chip 20 is set in chamber 101, filter chip 20 have the first upper surface 21 for being oppositely arranged and
First lower surface 22, the first upper surface 21 and upper surface of base plate 11 are located at ipsilateral, and the first upper surface 21 has several first electricity
Pole 211.
First electrode 211 protrudes out the first upper surface 21 towards the direction far from the first lower surface 22, and but not limited to this.
Filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or volume
Acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the active region on 20 surface of filter chip
Domain (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs are filtering
The lower section of device chip 20 forms a cavity to protect the active region.
Functional chip 30 is set to the top of package substrate 10, and functional chip 30 has the second upper surface 31 being oppositely arranged
And second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and the second upper surface 31 has several the
Two electrodes 311.
Second electrode 311 protrudes out the second upper surface 31 towards the direction far from the second lower surface 32, and but not limited to this.
Functional chip 30 is amplifier chip or RF switch chip, and but not limited to this.
Several interconnection structures 50 are for being connected several first electrodes 211 and several second electrodes 311.
Here, " several interconnection structures 50 are for being connected several first electrodes 211 and several second electrodes 311 " refers to first
It is electrically connected between electrode 211 and second electrode 311, that is, realizes the interconnection of filter chip 20 and functional chip 30.
Present embodiment is encapsulated two different chips (filter chip 20 and functional chip 30) using encapsulation technology
In same package substrate 10, the highly integrated of multi-chip may be implemented, improve the utilization rate of package substrate 10, and then realize encapsulation
The miniaturization of structure 100.
In addition, filter chip 20 and functional chip 30 are distributed in upper and lower, the functional chip above package substrate 10
30 and be not take up the space of package substrate 10, can be further improved the utilization rate of package substrate 10, and filter chip 20 and
Spacing between functional chip 30 becomes smaller, the interconnection being easy to implement between filter chip 20 and functional chip 30, simplifies interconnection
Structure.
It is set in chamber 101 moreover, filter chip 20 is embedded, so that encapsulating structure 100 is more frivolous, several outsides
Pin 121 is located at the side of upper surface of base plate 11, can effectively reduce the number of plies that is electrically connected reduced between electrode, external pin, thus
The thickness of encapsulating structure 100 is effectively reduced, and reduces technology difficulty.
It should be noted that the encapsulating structure 100 of present embodiment is with a filter chip 20 and a functional chip
30 are loaded into for package substrate 10, it is possible to understand that, in practice, referring to Figure 1 and Figure 2, it may include multiple filtering
Device chip 20 and multiple functional chips 30, (including up and down all around three-dimensional) can for example, around filter chip 20
It is electrically connected with multiple functional chips 30 etc..
In the present embodiment, functional chip 30 is located at the top of chamber 101, several first electrodes 211 and several second
Electrode 311 is in face of back setting.
That is, filter chip 20 and about 30 functional chip are correspondingly arranged, first electrode 211 and the second electricity
Pole 311 is located at the opposite two sides of package substrate 10, in this way, the setting of filter chip 20 can't mistake in the horizontal direction
The spaces for occupying 10 horizontal direction of package substrate, the size of package substrate 10 can be done small more.
Here, the size of functional chip 30 is greater than the size of filter chip 20, and functional chip 30 covers chamber 101
Upper area.
That is, chamber 101 is completely covered in the upright projection on package substrate 10 in the outer profile of functional chip 30.
In the present embodiment, interconnection structure 50 includes metal column 51 and electroplated layer structure 53.
Second electrode 311 is connected in metal column 51, at this point, metal column 51 is set to the top of second electrode 311.
First electrode 211, metal column 51 and external pin 121 is connected in electroplated layer structure 53.
Electroplated layer structure 53 includes the upper rewiring layer 531 of mutual conduction, top rewiring layer 532 and connecting column 533.
Top reroutes layer 532 and is located at the top of the second upper surface 31, and top reroute the conducting metal column 51 of layer 532 and
External pin 121.
Upper rewiring layer 531 is between the second lower surface 32 and upper surface of base plate 11, the first upper surface 21, and upper heavy cloth
First electrode 211 is connected in line layer 531.
Layer 531 is rerouted in the connection of connecting column 533 and top reroutes layer 532.
Specifically, encapsulating structure 100 includes the first insulating layer positioned at upper surface of base plate 11,21 top of the first upper surface
70, be connected by the hole of the first insulating layer 70 first electrode 211 upper rewiring layer 531, connection the first insulating layer 70 and
The second insulating layer 71 of second lower surface 32, second insulating layer 71 have fluting 43, fluting 43 expose reroute layer 531 and
It is connected for connecting column 533.
It includes that the first top rewiring layer 5321 and the second top reroute layer 5322 that top, which reroutes layer 532,.
Encapsulating structure 100 further includes coating second insulating layer 71 to be exposed to outer surface area, functional chip 30, connection
Column 533 and metal column 51 and with first through slot 601 and second through slot 602 the first plastic packaging layer 60, run through by first
Slot 601, second is connected through slot 602 and reroutes layer 531, the first top of second electrode 311 reroutes layer 5321, cladding
First plastic packaging layer 61 and the first top reroute the third insulating layer 72 of layer 5321, are connected by the hole of third insulating layer 72
The second top that first top reroutes layer 5321 reroutes layer 5322 and cladding third insulating layer 72 and the second top weight cloth
4th insulating layer 73 of line layer 5322, second top of the connection of external pin 121 reroute layer 5322, and the exposure of the 4th insulating layer 73
External pin 121.
Here, first through the connection of slot 601 fluting 43 and for accommodating connecting column 533, and first through slot 601 and fluting 43
It is mutually matched, second is used to accommodate metal column 51 through slot 602.
The setting that second top reroutes layer 5322 can not only expand rewiring range, improve subsequent external pin 121
The freedom degree of laying, the outer shifting of acceptable further accessory external pin 121.
Metal column 51 and connecting column 533 are copper post, and it is layers of copper that upper rewiring layer 531 and top, which reroute layer 532,.
Present embodiment realizes first electrode 211, second electrode 311 and outer using succinct rewiring (RDL) scheme
Electric connection between portion's pin 121, process stabilizing and high reliablity.
The metal line materials of rewiring are copper (above rerouting layer 531 and top rewiring layer 532 are layers of copper), are rerouted
Enhancing can be set between copper and chip electrode (including first electrode 211 and second electrode 311) and reroute copper and chip electrode
It is attached to each other the metal or alloy film of power, which can be nickel, titanium, nickel chromium triangle, titanium tungsten etc..
Package substrate 10, upper rewiring layer 531 and top reroute and are folded with the first insulating layer 70, second between layer 532
Insulating layer 71 and third insulating layer 72, to realize the electrical isolation between all parts.
It should be understood that the upper rewiring layer 531 in rewiring scheme is not limited with above-mentioned one layer, top reroutes layer
532 are not also limited with above-mentioned two layers, can according to the actual situation depending on.
In addition, the first plastic packaging layer 60 can be EMC (Epoxy Molding Compound) plastic packaging layer, due to this embodiment party
Formula can stop external substance to enter cavity S using cofferdam 40, without considering whether the first plastic packaging layer 60 can be because of problem of materials
And the protection zone in cavity S is influenced, therefore, the range of choice of 60 material of the first plastic packaging layer expands significantly, and then can evade
The selection of specific capsulation material is substantially widened plastic packaging making technology window and is effectively reduced cost.
In the present embodiment, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, cofferdam 40 and second
Lower surface 32, the first upper surface 21 cooperate and enclose to set to form cavity S, the active region on 20 surface of cavity S respective filter chip
Domain.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100.
In the present embodiment, cavity S is located at the inside of several first electrodes 211.
Cofferdam 40 includes positioned at the first cofferdam 41 of several 211 insides of first electrode and outside several first electrodes 211
Second cofferdam 42 of side, the first cofferdam 41 and the second lower surface 32 and the first upper surface 21 cooperate and enclose and set to form cavity S.
Since cofferdam 40 has certain height, when the lower surface area when cofferdam 40 is too small, this may can not be supported
There is collapsing phenomenon so as to cause cofferdam 40 in the cofferdam 40 of height, and the cofferdam 40 of present embodiment includes the first cofferdam 41 and the
Two cofferdam 42, cofferdam 40 have sufficiently large lower surface, improve the stability in entire cofferdam 40；In addition, 40 lower surface of cofferdam
It can combine with the 20 upper surface whole region of filter chip outside the 20 upper surface region cavity S of filter chip, further mention
The forming stability of high cavity S.
In conjunction with Fig. 4, several first electrodes 211 are in array distribution in upper surface of base plate 11, and between adjacent first electrode 211
With interval, there is a space between two column first electrodes 211, cavity S is located in the space, and the first cofferdam 41 is located at the first electricity
The inside of pole 211, the second cofferdam 42 slot 43 positioned at the upper of cofferdam 40 by extending outward close to 211 region of first electrode
Side, fluting 43 are located at the outside of functional chip 30.
In addition, the second cofferdam 42 extends up to lateral border and the encapsulation in the second cofferdam 42 towards the direction far from the first cofferdam 41
The lateral border of substrate 10 flushes.
Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after
Side lateral margin, the second cofferdam 42 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also
To be the structure of other shapes.
It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam
41 be the first cyclic structure, and the first cyclic structure is located at the inside of several first electrodes 211, and the second cofferdam 42 is the second cyclic annular knot
Structure, the second cyclic structure are located at the outside of several first electrodes 211.
Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and
Between two cofferdam 42 by third cofferdam 45 realize interconnection, third cofferdam 45 between adjacent first electrode 211 either
Other regions, that is to say, that cofferdam 40 at this time is covered with the removing region cavity S above upper surface of base plate 11 and the first upper surface 21
Other whole regions.
In the present embodiment, the second lower surface 32 of functional chip 30 covers the upper surface in the first cofferdam 41, and second
Lower surface 32 is Chong Die with the upper surface portion in the second cofferdam 42, and the first upper surface 21 and upper surface of base plate 11 cover first together and enclose
The lower surface in the lower surface on weir 41 and the second cofferdam 42.
Cofferdam 40 is made of the insulating materials of photaesthesia, and but not limited to this.
In the present embodiment, the first upper surface 21 of filter chip 20 is flushed with upper surface of base plate 11, moreover, filtering
Gap, base lower surface 12 and the first lower surface 22 of device chip 20 and chamber 101 are provided with the second plastic packaging layer 61.
Other explanations of second plastic packaging layer 61 can refer to the explanation of the first plastic packaging layer 60, and details are not described herein.
Here, pass through the setting of the second plastic packaging layer 61, on the one hand, can with compensating filter chip 20 and package substrate 10 it
Between difference in thickness, thus realize the first upper surface 21 flushed with upper surface of base plate 11, in order to subsequent first insulating layer 70 etc.
The molding of structure；On the other hand, the second plastic packaging layer 61 can play protecting filter chip 20 and fixed filters chip 20
With the effect of the relative position of chamber 101.
An embodiment of the present invention also provides a kind of production method of encapsulating structure 100, in conjunction with aforementioned encapsulation structure 100
Illustrate and Fig. 5, Fig. 6 a to Fig. 6 z-16, production method comprising steps of
S1: ginseng Fig. 6 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S2: ginseng Fig. 6 b, in formation chamber 101 on package substrate 10；
S3: ginseng Fig. 6 c provides filter chip 20, and filter chip 20 has the first upper surface 21 being oppositely arranged and the
A lower surface 22, the first upper surface 21 have several first electrodes 211；
S4: ginseng Fig. 6 d to Fig. 6 j loads filter chip 20 to chamber 101, the first upper surface 21 and upper surface of base plate
11 positioned at ipsilateral；
Step S4 is specific as follows:
Join Fig. 6 d, an interim jointing plate 90 is provided；
Join Fig. 6 e, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate 90；
Join Fig. 6 f, filter chip 20 is loaded to chamber 101, the first upper surface 21 is located at same with upper surface of base plate 11
Side；
Here, the first upper surface 21 also fits in interim jointing plate 90, so, it can be achieved that on the first upper surface 21 and substrate
Surface 11 flushes.
Join Fig. 6 g, forms gap, base lower surface 12 and the first lower surface 22 of cladding filter chip 20 and chamber 101
The second plastic packaging layer 61；
Join Fig. 6 h, removes interim jointing plate 90；
Join Fig. 6 i, inverts package substrate 10.
S5: ginseng Fig. 6 j to Fig. 6 u, in forming the first interconnection structure on package substrate 10, the first interconnection structure conducting first is electric
Pole 211；
Step S5 is specific as follows:
Join Fig. 6 j, lays the first insulating layer 70 in upper surface of base plate 11；
Join Fig. 6 k to Fig. 6 o, is formed in the top of the first insulating layer 70 by the hole conducting first on the first insulating layer 70
The upper rewiring layer 531 of electrode 211；
It is specific as follows:
Join Fig. 6 k, forms the first hole 701 in 70 exposure and imaging of the first insulating layer, the first hole 701 exposes first
Electrode 211 and protection zone, protection zone is located at the first upper surface 21, and protection zone is located at the interior of several first electrodes 211
Side；
Join Fig. 6 l, forms the first photoresist layer 81 in the top of the first insulating layer 70；
Join Fig. 6 m, forms the first aperture 811 in 81 exposure and imaging of the first photoresist layer, the first aperture 811 exposes the
One electrode 211 and the first insulating layer 70；
Join Fig. 6 n, reroutes layer 531 in being formed in the first aperture 811；
Join Fig. 6 o, removes the first photoresist layer 81.
Join Fig. 6 p and Fig. 6 q, in the first insulating layer 70, it is upper reroute layer 531 top lay second insulating layer 71, first
Insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 includes the first cofferdam 41 and the second cofferdam 42, and first encloses
Weir 41 is located at the periphery of cavity S, and the lateral border in the second cofferdam 42 is flushed with the lateral border of package substrate 10, and cofferdam 40 has exposure
The upper fluting 43 for rerouting layer 531 out；
It is specific as follows:
Join Fig. 6 p, lays second insulating layer 71 in the first insulating layer 70, the upper top for rerouting layer 531 and protection zone；
Join Fig. 6 q, forms the second hole 711 in 71 exposure and imaging of second insulating layer, the second hole 711 exposes heavy
Wiring layer 531 and protection zone, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 is enclosed including first
Weir 41 and the second cofferdam 42, the first cofferdam 41 are located at the periphery of protection zone, the lateral border and package substrate 10 in the second cofferdam 42
Lateral border flush, cofferdam 40 have expose reroute layer 531 fluting 43；
It should be noted that cofferdam 40 may include the third cofferdam 45 for connecting the first cofferdam 41 and the second cofferdam 42,
That is removing the other surfaces region outside the corresponding region cavity S in upper surface of base plate 11 at this time is respectively formed cofferdam 40.
In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when forming cofferdam 40
With the multiple cofferdam 40 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 40
A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic on functional chip 30.
Join Fig. 6 r to Fig. 6 u, in formation connecting column 533 in fluting 43；
It is specific as follows:
Join Fig. 6 r, lays the second photoresist layer 82 in the top of second insulating layer 71 and protection zone；
Join Fig. 6 s, and form the second aperture 821 in 82 exposure and imaging of the second photoresist layer, the second aperture 821 is connected to simultaneously
Matching fluting 43；
Join Fig. 6 t, in formation connecting column 533 in the second aperture 821 and fluting 43；
Join Fig. 6 u, removes the second photoresist layer 82.
S6: ginseng Fig. 6 v, functional chip 30 is provided, functional chip 30 has under the second upper surface 31 and second being oppositely arranged
Surface 32, and the second upper surface 31 has several second electrodes 311；
S7: ginseng Fig. 6 w to Fig. 6 z-13 is loaded into functional chip 30 top of package substrate 10, the second lower surface 32 with
Upper surface of base plate 11 is arranged face-to-face, and forms the second interconnection structure of conducting second electrode 311 and the first interconnection structure；
S8: ginseng Fig. 6 z-14 to Fig. 6 z-16, the third for forming conducting external pin 121 and the first interconnection structure mutually link
Structure, external pin 121 are located at the side of upper surface of base plate 11.
Step S7, S8 is specific as follows:
Join Fig. 6 w to Fig. 6 z, forms metal column 51 in the upper surface of second electrode 311；
It is specific as follows:
Join Fig. 6 w, forms third photoresist layer 83 in the second upper surface 31；
Join Fig. 6 x, forms third aperture 831 in 83 exposure and imaging of third photoresist layer, third aperture 831 exposes the
Two electrodes 311；
Join Fig. 6 y, in formation metal column 51 in third aperture 831；
Join Fig. 6 z, removes third photoresist layer 83.
Join Fig. 6 z-1, functional chip 30 is loaded into the top of package substrate 10, the second lower surface 32 and upper surface of base plate
11 settings face-to-face, the first cofferdam 41 cooperate with the second lower surface 32, the first upper surface 21 and enclose to set to form corresponding protection
The cavity S in region.
Join Fig. 6 z-2, forms the first plastic packaging layer 60, the first plastic packaging far from the side of base lower surface 12 in package substrate 10
Layer 60 coats the second cofferdam 42 simultaneously and is exposed to outer surface area, functional chip 30, metal column 51 and connecting column 533；
Join Fig. 6 z-3, grinds the first plastic packaging layer 60 and expose metal column 51 and connecting column 533；
Join Fig. 6 z-4 to Fig. 6 z-7, forms the of conducting metal column 51 and connecting column 533 in the top of the first plastic packaging layer 60
One top reroutes layer 5321；
It is specific as follows:
Join Fig. 6 z-4, in the 4th photoresist layer 84 of formation on the first plastic packaging layer 60；
Join Fig. 6 z-5, forms the 4th aperture 841, the 4th aperture 841 exposure in exposure and imaging on the 4th photoresist layer 84
Metal column 51, connecting column 533 and the first plastic packaging layer 61 out；
Join Fig. 6 z-6, reroutes layer 5321 in forming the first top in the 4th aperture 841, the first top reroutes layer 5321
Metal column 51 and connecting column 533 is connected；
Join Fig. 6 z-7, removes the 4th photoresist layer 84.
Join Fig. 6 z-8, forms third insulating layer 72 in the top that the first plastic packaging layer 60 and the first top reroute layer 5321；
Join Fig. 6 z-9 to Fig. 6 z-13, is formed above third insulating layer 72 by the hole conducting on third insulating layer 72
The second top that first top reroutes layer 5321 reroutes layer 5322；
It is specific as follows:
Join Fig. 6 z-9, forms third hole 721 in 72 exposure and imaging of third insulating layer, third hole 721 exposes the
Three insulating layers 72；
Join Fig. 6 z-10, forms the 5th photoresist layer 85 in the top of third insulating layer 72；
Join Fig. 6 z-11, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes
Third hole 721 and third insulating layer 72；
Join Fig. 6 z-12, reroutes layer 5322 in forming the second top in the 5th aperture 851；
Join Fig. 6 z-13, removes the 5th photoresist layer 85.
Join Fig. 6 z-14 and Fig. 6 z-15, is formed and coat the reroute layer 5322 at the top of third insulating layer 72 and second the 4th absolutely
Edge layer 73, the 4th insulating layer 73 expose the second top and reroute layer 5322；
It is specific as follows:
Join Fig. 6 z-14, forms the 4th insulating layer 73 in the top that the second top reroutes layer 5322 and third insulating layer 72；
Join Fig. 6 z-15, forms the 4th hole 731 in 73 exposure and imaging of the 4th insulating layer, the 4th hole 731 exposes the
Two tops reroute layer 5322.
Join Fig. 6 z-16, reroutes layer 5322 in the second top for being exposed to outer and form ball grid array 121, i.e., in the 4th hole
Ball grid array 121 is formed in hole 731.
Other explanations of the production method of the encapsulating structure 100 of present embodiment can be with reference to above-mentioned encapsulating structure 100
Illustrate, details are not described herein.
Cofferdam 40 of the invention is located at the inside and outside of first electrode 211, and the lateral border in the second cofferdam 42 and encapsulation
The lateral border of substrate 10 flushes, and in other embodiments, cofferdam 40 may be alternatively located at the inside of first electrode 211, alternatively, second
The lateral border in cofferdam 42 is flushed with the lateral border of functional chip 30, or, the lateral border in the second cofferdam 42 is located at functional chip
Between 30 lateral border and the lateral border of package substrate 10 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process,
To improve the overall performance of encapsulating structure 100.
In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 20 and functional chip 30)
It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, and then realize
The miniaturization of encapsulating structure 100.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (10)
1. the encapsulating structure that a kind of filter chip is embedded and set on pin characterized by comprising
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber, and described
The side of upper surface of base plate has several external pins；
Filter chip is set in the chamber, and the filter chip has the first upper surface and first being oppositely arranged
Lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several first electricity
Pole；
Functional chip, is set to the top of the package substrate, the functional chip have the second upper surface being oppositely arranged and
Second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface is with several
Second electrode；
Several interconnection structures, for several first electrodes, several second electrodes and several external pins to be connected.
2. encapsulating structure according to claim 1, which is characterized in that it is separate that the external pin is located at the functional chip
The side of the package substrate.
3. encapsulating structure according to claim 1, which is characterized in that the interconnection structure includes metal column and electroplated layer knot
Structure, the metal column are connected the second electrode, and the first electrode, the metal column and described is connected in the electroplated layer structure
External pin.
4. encapsulating structure according to claim 3, which is characterized in that the electroplated layer structure includes the upper heavy of mutual conduction
Wiring layer, top reroute layer and connecting column, and the top reroutes the top that layer is located at second upper surface, and the top
Portion reroutes layer and is connected the metal column and the external pin, and the upper rewiring layer is located at second lower surface and described
Between upper surface of base plate, the first upper surface, and the upper rewiring layer is connected the first electrode, described in the connecting column connection
Upper rewiring layer and the top reroute layer.
5. encapsulating structure according to claim 4, which is characterized in that the encapsulating structure includes being located at table on the substrate
The first electrode is connected by the hole on first insulating layer in the first insulating layer above face, the first upper surface
The upper second insulating layer for rerouting layer, connecting first insulating layer and second lower surface, the second insulating layer have
Fluting, the fluting expose the upper rewiring layer and the connecting column are supplied to connect.
6. encapsulating structure according to claim 5, which is characterized in that first insulating layer and the second insulating layer are matched
Conjunction forms cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, and the cofferdam includes
The first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, first cofferdam with
Second lower surface, first upper surface cooperate and enclose to set to form cavity, and second cofferdam is towards far from described the
The lateral border that the direction in one cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate.
7. encapsulating structure according to claim 5, which is characterized in that it includes the first top weight cloth that the top, which reroutes layer,
Line layer and the second top reroute layer, and the encapsulating structure further includes coating the second insulating layer to be exposed to outer upper surface region
Domain, the functional chip, the metal column and the connecting column and the first plastic packaging for running through slot through slot and second with first
Upper first top for rerouting layer, the metal column is connected through slot through slot, described second by described first in layer
Rewiring layer coats the third insulating layer of rewiring layer at the top of the first plastic packaging layer and described first, is exhausted by the third
The hole of edge layer and first top be connected reroute the second top of layer and reroute layer and the cladding third insulating layer
And second top reroutes the 4th insulating layer of layer, external pin connection second top reroutes layer, and institute
State external pin described in the 4th insulating layer exposing, wherein described first through the slot connection fluting and for accommodating the company
Column is connect, described second is located at the package substrate far from described for accommodating the metal column, the first plastic packaging layer through slot
The side of base lower surface.
8. encapsulating structure according to claim 1, which is characterized in that the gap of the filter chip and the chamber,
The base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and the upper surface of base plate
It flushes.
9. a kind of filter chip is embedded and pin on the production method of encapsulating structure set, which is characterized in that comprising steps of
S1: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S2: in forming chamber on the package substrate；
S3: filter chip is provided, the filter chip has the first upper surface and the first lower surface being oppositely arranged, described
First upper surface has several first electrodes；
S4: the filter chip is loaded to the chamber, first upper surface is located at ipsilateral with the upper surface of base plate；
S5: in forming the first interconnection structure on the package substrate, the first electrode is connected in first interconnection structure；
S6: providing functional chip, and the functional chip has the second upper surface and the second lower surface that are oppositely arranged, and described the
Two upper surfaces have several second electrodes；
S7: the functional chip is loaded into the top of the package substrate, second lower surface and the upper surface of base plate
Setting face-to-face, and form the second interconnection structure that the second electrode and first interconnection structure is connected；
S8: forming the third interconnection structure of conducting external pin and first interconnection structure, and the external pin is located at described
The side of upper surface of base plate.
10. the production method of encapsulating structure according to claim 9, which is characterized in that step S4 is specifically included:
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The filter chip is loaded to the chamber, first upper surface is located at ipsilateral with the upper surface of base plate；
Form the of the gap for coating the filter chip and the chamber, the base lower surface and first lower surface
Two plastic packaging layers；
Remove the interim jointing plate；
Invert the package substrate；
Step S5 is specifically included:
The first insulating layer is laid in the upper surface of base plate；
It is formed in the top of first insulating layer and the upper of the first electrode is connected by the hole on first insulating layer
Reroute layer；
Second insulating layer, first insulating layer and described are laid in first insulating layer, the upper top for rerouting layer
Second insulating layer cooperatively forms cofferdam, and the cofferdam includes the first cofferdam and the second cofferdam, and first cofferdam is located at cavity
The lateral border of periphery, second cofferdam is flushed with the lateral border of the package substrate, and the cofferdam, which has, to be exposed on described
Reroute the fluting of layer；
In forming connecting column in the fluting；
Step S7, S8 is specifically included:
Metal column is formed in the upper surface of the second electrode；
The functional chip is loaded into the top of the package substrate, second lower surface is faced with the upper surface of base plate
Face setting, first cofferdam and second lower surface, first upper surface mutual cooperation and enclosing set to be formed it is corresponding described in
The cavity of protection zone；
The first plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the first plastic packaging layer wraps simultaneously
It covers second cofferdam and is exposed to outer surface area, the functional chip, the metal column and the connecting column；
It grinds the first plastic packaging layer and exposes the metal column and the connecting column；
The first top rewiring layer that the metal column and the connecting column is connected is formed in the top of the first plastic packaging layer；
Third insulating layer is formed in the top that the first plastic packaging layer and first top reroute layer；
It is formed above the third insulating layer and is rerouted by hole conducting first top on the third insulating layer
Second top of layer reroutes layer；
The 4th insulating layer for coating the third insulating layer and the second top rewiring layer is formed, the 4th insulating layer is sudden and violent
Expose second top and reroutes layer；
Layer, which is rerouted, in the second top for being exposed to outer forms ball grid array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810909243.5A CN109103173B (en) | 2018-08-10 | 2018-08-10 | Packaging structure with filter chip embedded and pins placed on top and manufacturing method thereof |
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|---|---|---|---|
| CN201810909243.5A CN109103173B (en) | 2018-08-10 | 2018-08-10 | Packaging structure with filter chip embedded and pins placed on top and manufacturing method thereof |
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| CN109103173A true CN109103173A (en) | 2018-12-28 |
| CN109103173B CN109103173B (en) | 2024-04-16 |
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| CN111555734A (en) * | 2020-05-13 | 2020-08-18 | 北京航天微电科技有限公司 | Surface acoustic wave switch filtering module based on RF-SiP technology and electronic equipment |
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| CN109103173B (en) | 2024-04-16 |
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