CN109148298B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109148298B CN109148298B CN201710499070.XA CN201710499070A CN109148298B CN 109148298 B CN109148298 B CN 109148298B CN 201710499070 A CN201710499070 A CN 201710499070A CN 109148298 B CN109148298 B CN 109148298B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 125
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000002019 doping agent Substances 0.000 claims abstract description 45
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 238000005280 amorphization Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 36
- 238000002513 implantation Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000004151 rapid thermal annealing Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- -1 arsenic ions Chemical class 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000009826 distribution Methods 0.000 description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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Abstract
本发明公开了一种半导体器件及其制造方法，涉及半导体技术领域。该制造方法包括：提供半导体结构，该半导体结构包括：半导体衬底和在该半导体衬底上的栅极结构；在该半导体衬底上且在该栅极结构的至少一侧形成多晶材料层；对该多晶材料层执行非晶化处理，使得该多晶材料层变为非晶材料层；对该非晶材料层执行掺杂，以在该非晶材料层中掺入掺杂物；以及执行退火处理，使得该掺杂物进入半导体衬底以在非晶材料层下方形成源极和/或漏极。本发明可以将使得掺杂物在扩散的过程中更加均匀，因此可以提高SRAM器件的维持电流的均匀性。
The invention discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The manufacturing method includes: providing a semiconductor structure, the semiconductor structure comprising: a semiconductor substrate and a gate structure on the semiconductor substrate; forming a polycrystalline material layer on the semiconductor substrate and on at least one side of the gate structure ; performing an amorphization process on the polycrystalline material layer, so that the polycrystalline material layer becomes an amorphous material layer; performing doping on the amorphous material layer to incorporate a dopant into the amorphous material layer; and performing an annealing process such that the dopant enters the semiconductor substrate to form source and/or drain electrodes under the amorphous material layer. The present invention can make the dopant more uniform in the process of diffusion, and thus can improve the uniformity of the maintaining current of the SRAM device.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
In SRAM design, the holding current (standby current) is a very important factor, which corresponds to the leakage current of the device when it is not in operation. The smaller the current value of the sustain current, the better. In addition to the current value, the more uniform the distribution of the sustain current of the SRAM is, the better.
Currently, the SRAM generally uses NMOS (N-channel Metal Oxide Semiconductor) devices as PD (Pull Down) transistors and PG (Pass Gate) transistors. In the prior art, during the fabrication of NMOS devices, a thin polysilicon layer may be formed over the source and drain regions, and then phosphorus is diffused from the polysilicon layer into the silicon to form the source and drain. But such a manufacturing process would result in non-uniformity of the sustain current of the SRAM.
For example, as shown in fig. 10, in a conventional NMOS device, a gate dielectric layer 911, a gate 912, and a spacer layer 913 are formed on a silicon substrate 90. A polysilicon layer 940 is formed on both sides of the gate, wherein phosphorus diffuses from the polysilicon layer 940 into the silicon substrate 90 to form a source 91 and a drain 92. The polysilicon layer 940 may serve as a connection portion of the source 91 and drain 92 with contacts (not shown). However, the distribution of the holding current of the SRAM manufactured by the NMOS device shown in fig. 10 is relatively poor. For example, as shown in fig. 9, fig. 9 shows a distribution diagram of a sustain current of an SRAM having 4M (mega), wherein a curve (1) shows a distribution of a sustain current of an SRAM manufactured using an existing semiconductor device (e.g., NMOS device). As can be seen from the curve (1), the uniformity of the holding current of the conventional SRAM is relatively poor.
Disclosure of Invention
The inventors of the present invention have found that there are problems in the above-mentioned prior art, and thus have proposed a new technical solution to at least one of the problems.
One of the objectives of an embodiment of the present invention is: provided is a method for manufacturing a semiconductor device, whereby the uniformity of the holding current of the device can be improved.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: providing a semiconductor structure, the semiconductor structure comprising: the semiconductor device comprises a semiconductor substrate and a gate structure on the semiconductor substrate; forming a polycrystalline material layer on the semiconductor substrate and on at least one side of the gate structure; performing amorphization on the polycrystalline material layer so that the polycrystalline material layer becomes an amorphous material layer; performing doping on the amorphous material layer to dope a dopant in the amorphous material layer; and performing an annealing process so that the dopant enters the semiconductor substrate to form a source and/or a drain below the amorphous material layer.
In one embodiment, the step of performing an amorphization process on the layer of polycrystalline material comprises: performing a first ion implantation on the polycrystalline material layer to amorphize the polycrystalline material layer; wherein the ions implanted by the first ion implantation comprise: arsenic ions.
In one embodiment, in performing the first ion implantation, an implantation energy of the first ion implantation is determined according to a thickness of the polycrystalline material layer such that the first ion implantation is capable of amorphizing the polycrystalline material layer and is implanted to a depth not exceeding the polycrystalline material layer.
In one embodiment, the first ion implantation has an implantation energy in a range of 5KeV to 50 KeV; the first ion implantation has an implantation dose in the range of 1 × 1013atom/cm2To 1X 1016atom/cm2。
In one embodiment, the layer of polycrystalline material has a thickness of
To
In one embodiment, the annealing process is a rapid thermal annealing process.
In one embodiment, the rapid thermal annealing process has an annealing temperature in a range of 950 ℃ to 1100 ℃; the annealing time of the rapid thermal annealing process ranges from 5 seconds to 20 seconds.
In one embodiment, the layer of polycrystalline material is polycrystalline silicon; the amorphous material layer is amorphous silicon.
In one embodiment, the step of forming a layer of polycrystalline material on the semiconductor substrate and on at least one side of the gate structure comprises: forming polycrystalline material layers on the semiconductor substrate and on two sides of the gate structure respectively; the step of performing an annealing process so that the dopants enter the semiconductor substrate to form a source and/or drain below the layer of amorphous material comprises: and performing annealing treatment so that the dopant is diffused into the semiconductor substrate to form a source electrode and a drain electrode below the amorphous material layer, in the semiconductor substrate and on two sides of the gate structure respectively.
In one embodiment, in the step of providing the semiconductor structure, the gate structure includes: a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and spacer layers on sides of both sides of the gate, respectively; wherein, in the step of forming the polycrystalline material layer, the spacer layer isolates the polycrystalline material layer from the gate electrode.
In one embodiment, the step of performing doping on the amorphous material layer comprises: performing a second ion implantation on the amorphous material layer to implant dopants in the amorphous material layer.
In one embodiment, in the step of providing the semiconductor structure, the semiconductor substrate includes: a well region, wherein the gate structure is over the well region; the well region is of a P type, and the dopant is an N type dopant; or the well region is of an N type, and the dopant is a P type dopant.
In the above-described manufacturing method of an embodiment of the present invention, amorphization processing is performed on a polycrystalline material layer formed on a semiconductor substrate so that the polycrystalline material layer becomes an amorphous material layer, and then doping is performed on the amorphous material layer to dope a dopant in the amorphous material layer. During the annealing process, the dopant enters the semiconductor substrate through the diffusion path of the amorphous material layer to form the source and the drain. Since the amorphous material layer has smaller crystal grains and more grain boundaries than the polycrystalline material layer, the grain boundaries serve as diffusion paths for the dopant and thus the diffusion paths are more. This will make the dopant more uniform during diffusion and thus may improve the uniformity of the device's holding current.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate structure on the semiconductor substrate; an amorphous material layer on the semiconductor substrate and on at least one side of the gate structure; and a source and/or drain under the amorphous material layer and in the semiconductor substrate.
In one embodiment, the amorphous material layer comprises: arsenic.
In one embodiment, the layer of amorphous material has a thickness of
To
In one embodiment, the amorphous material layer is amorphous silicon.
In one embodiment, the amorphous material layer includes: the amorphous material layers are arranged on the semiconductor substrate and on two sides of the grid structure respectively; the source and/or the drain includes: a source and a drain in the semiconductor substrate below the amorphous material layer and on either side of the gate structure.
In one embodiment, the gate structure includes: a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and spacer layers on sides of both sides of the gate, respectively; wherein the spacer layer isolates the polycrystalline material layer from the gate.
In one embodiment, the semiconductor substrate includes: a well region, wherein the gate structure is over the well region; the well region is of a P type, and the source electrode and the drain electrode are of an N type; or the well region is of an N type, and the source electrode and the drain electrode are of a P type.
In the semiconductor device according to the embodiment of the invention, since the amorphous material layer is used on the source and the drain, the diffusion of the dopant can be more uniform, and thus the uniformity of the holding current of the device can be improved.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 8 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a semiconductor device according to an embodiment of the present invention.
Fig. 9 is a graph showing the distribution of the detected holding current of the SRAM, where curve (1) shows the distribution of the holding current of the SRAM manufactured by using the conventional semiconductor device, and curve (2) shows the distribution of the holding current of the SRAM manufactured by using the semiconductor device according to the embodiment of the present invention.
Fig. 10 is a cross-sectional view schematically showing a related art semiconductor device.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The inventors of the present invention found that, during the manufacturing process of the existing semiconductor device, the polysilicon layer over the source and drain regions has relatively large grains, which causes phosphorus to be diffused along grain boundaries between the grains during the subsequent process of diffusing phosphorus into silicon, but the grain boundaries act as diffusion paths, the number of which is relatively limited and the distribution is not uniform, which causes poor uniformity of phosphorus diffusion, resulting in non-uniform doping, and thus the holding current of the SRAM manufactured using such a semiconductor device is also not uniform.
Fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 2 through 8 are cross-sectional views schematically illustrating structures at several stages in the fabrication of a semiconductor device according to one embodiment of the present invention. A manufacturing process of a semiconductor device according to an embodiment of the present invention is described in detail below with reference to fig. 1 and fig. 2 to 8.
As shown in fig. 1, in step S101, a semiconductor structure is provided, the semiconductor structure comprising: the semiconductor device includes a semiconductor substrate and a gate structure on the semiconductor substrate. Regarding this step S101, detailed description may be made in conjunction with fig. 2 to 4.
First, the step S101 may include: providing an initial structure as shown in fig. 2, which may include: a semiconductor substrate (which may comprise silicon, for example) 20, a gate dielectric layer (silicon dioxide, for example) 211 on the semiconductor substrate 20, and a gate (polysilicon, for example) 212 on the gate dielectric layer. In one embodiment, the semiconductor substrate may include a well region 201. For example, the conductivity type of the well 201 may be P-type (the P-type well may be used to form an NMOS device) or N-type (the N-type well may be used to form a PMOS (P-channel Metal Oxide Semiconductor) device). Optionally, the semiconductor substrate 20 may further include a trench isolation portion 202 formed around the well region 201. The trench isolation portion 202 is used to isolate the well 201 from other well regions. For example, the trench isolation 202 may include: a trench around the well region and a trench insulator layer (e.g., silicon dioxide) filling the trench.
Next, optionally, the step S101 may further include: as shown in fig. 3, a first doped region 31 and a second doped region 32 are formed in the well 201 and on both sides of the gate 202, respectively. The first and second Doped regions 31 and 32 may be formed, for example, by an LDD (Lightly Doped Drain) ion implantation process. The conductivity type of the first doped region 31 and the second doped region 32 is opposite to the conductivity type of the well region 201. For example, the conductivity type of the well region is P-type, and the conductivity types of the first doped region 31 and the second doped region 32 are N-type; alternatively, the conductivity type of the well region is N-type, and the conductivity types of the first doped region 31 and the second doped region 32 are P-type.
Next, the step S101 may further include: as shown in fig. 4, a spacer layer (e.g., silicon dioxide and/or silicon nitride) 213 is formed on the semiconductor substrate 20 and on the sides of the gate electrode 212 on both sides, respectively.
To this end, a semiconductor structure according to one embodiment of the present invention is formed.
As shown in fig. 4, the semiconductor structure may include: a semiconductor substrate 20 and a gate structure 21 on the semiconductor substrate 20. In one embodiment, the semiconductor substrate may include a well region 201, wherein the gate structure 21 is over the well region 201. Optionally, the semiconductor substrate 20 may further include a trench isolation portion 202 formed around the well region 201.
Optionally, the semiconductor substrate 20 may further include: a first doped region 31 and a second doped region 32 in the well 201 and on both sides of the gate 212, respectively.
In one embodiment, as shown in fig. 4, the gate structure 21 may include: a gate dielectric layer 211 on the semiconductor substrate 20, a gate electrode 212 on the gate dielectric layer 211, and spacer layers 213 on sides of both sides of the gate electrode 212, respectively.
Returning to fig. 1, in step S102, a polycrystalline material layer is formed on the semiconductor substrate and on at least one side of the gate structure.
Fig. 5 is a cross-sectional view schematically showing the structure of one embodiment at step S102. As shown in fig. 5, the step S102 may include: a polycrystalline material layer 40 is formed on the semiconductor substrate 20 and on both sides of the gate structure 21, respectively. For example, the layer of polycrystalline material may be polycrystalline silicon. For example, the thickness of the polycrystalline material layer 40 may be
To
(e.g. in
Or
Etc.).
In one embodiment, as shown in fig. 5, the polycrystalline material layer 40 may be formed over the first doped region 31 and the second doped region 32. Optionally, the polycrystalline material layer 40 may also be formed over the trench isolation 202. In the step of forming the polycrystalline material layer, a spacer layer 213 separates the polycrystalline material layer 40 from the gate electrode 212, as shown in fig. 5.
Although fig. 5 illustrates the formation of the polycrystalline material layer on both sides of the gate structure, the scope of the present invention is not limited thereto, and the polycrystalline material layer may be formed on only one side of the gate structure, for example.
Returning to fig. 1, in step S103, an amorphization process is performed on the polycrystalline material layer so that the polycrystalline material layer becomes an amorphous material layer.
Fig. 6 is a cross-sectional view schematically showing the structure of one embodiment at step S103. As shown in fig. 6, the step S103 may include: a first ion implantation 61 is performed on the polycrystalline material layer 40 to amorphize the polycrystalline material layer 40, thereby causing the polycrystalline material layer 40 to become an amorphous material layer 50. For example, the amorphous material layer may be amorphous silicon. In one embodiment, the ions implanted by the first ion implantation 61 may include: arsenic ions, and the like.
In one embodiment, during the first ion implantation 61, the implantation energy of the first ion implantation 61 may be determined according to the thickness of the polycrystalline material layer 40, such that the first ion implantation is capable of amorphizing the polycrystalline material layer 40 and the implantation depth is not more than the polycrystalline material layer 40. Preferably, the implantation energy of the first ion implantation 61 may range from 5KeV to 50 KeV. For example, the implantation energy of the first ion implantation 61 may be 10KeV, 20KeV, 30KeV, 40KeV, or the like. In one embodiment, the implantation dose of the first ion implantation 61 may range from 1 × 1013atom/cm2To 1X 1016atom/cm2. For example, the first ion implantation 61 may have an implantation dose of 1 × 1014atom/cm2Or 1X 1015atom/cm2And the like.
In another embodiment, the first ion implantation may also be performed such that a portion of the ions implanted by the first ion implantation pass beyond the layer of polycrystalline material and into the semiconductor substrate.
Returning to fig. 1, in step S104, doping is performed on the amorphous material layer to dope the amorphous material layer with dopants.
Fig. 7 is a cross-sectional view schematically showing the structure of one embodiment at step S104. As shown in fig. 7, the step S104 may include: a second ion implantation 62 is performed on the amorphous material layer 50 to implant dopants in the amorphous material layer 50. In one embodiment, the well region 201 may be P-type, and the dopant may be an N-type dopant (e.g., phosphorus). That is, in the case where an NMOS device needs to be formed, the second ion implantation implants an N-type dopant into the amorphous material layer. In another embodiment, the well 201 may be N-type and the dopant may be P-type dopant (e.g., boron). I.e., where it is desired to form a PMOS device, the second ion implantation implants P-type dopants into the amorphous material layer. For example, the implantation energy of the second ion implantation may be 3KeV to 10KeV (e.g., 5 KeV).
Returning to fig. 1, in step S105, an annealing process is performed so that dopants enter the semiconductor substrate to form a source and/or drain under the amorphous material layer.
Fig. 8 is a cross-sectional view schematically showing the structure of one embodiment at step S105. As shown in fig. 8, the step S105 may include: an annealing process is performed so that dopants (i.e., dopants doped by performing doping on the amorphous material layer 50) are diffused into the semiconductor substrate 20 to form a source 71 and a drain 72 below the amorphous material layer 50, in the semiconductor substrate 20, and on both sides of the gate structure 21, respectively. As shown in fig. 8, the annealing process causes dopants to diffuse into the first doped region 31, the second doped region 32 and the well region 201,
thereby forming a source electrode 71 and a drain electrode 72. The conductivity type of the source 71 and the drain 72 is opposite to that of the well region. In addition, the annealing process may also activate dopants (e.g., phosphorous ions) in the source and drain.
In one embodiment, the Annealing process may be a Rapid Thermal Annealing (RTA) process. In one embodiment, the annealing temperature range of the rapid thermal annealing process may be 950 ℃ to 1100 ℃. For example, the annealing temperature may be 1000 ℃. In one embodiment, the annealing time of the rapid thermal annealing process may range from 5 seconds to 20 seconds. For example, the annealing time may be 10 seconds, 15 seconds, or the like.
Thus, a method of manufacturing a semiconductor device according to an embodiment of the present invention is provided. In the above-described manufacturing method, amorphization processing is performed on a polycrystalline material layer formed on a semiconductor substrate so that the polycrystalline material layer becomes an amorphous material layer, and then doping is performed on the amorphous material layer to dope a dopant in the amorphous material layer. During the annealing process, the dopant enters the semiconductor substrate through the diffusion path (i.e., grain boundary) of the amorphous material layer to form the source and drain electrodes. Compared with a polycrystalline material layer, the amorphous material layer has smaller crystal grains and more grain boundaries, and the grain boundaries can be used as diffusion paths of the dopant (such as phosphorus), so that the diffusion paths are more, the dopant is more uniform in the diffusion process, and the uniformity of the holding current of the device can be improved.
The above-described manufacturing method of the present invention can be applied to a MOS device, and particularly, can be applied to an NMOS device which can be a PD transistor or a PG transistor.
In one embodiment, before performing the first ion implantation on the polycrystalline material layer, the manufacturing method may further include: a mask layer (not shown), such as silicon nitride, may be formed on the gate and then removed after the first ion implantation is performed. In this way, during the process of performing the first ion implantation, the ions of the first ion implantation can be prevented from being implanted into the gate electrode, so that the device performance can be prevented from being affected as much as possible.
In another embodiment, the ratio of the implantation doses of the first ion implanted ions (e.g., arsenic ions) and the second ion implanted dopants (e.g., phosphorus) may be adjusted to minimize the impact on the gate performance. For example, the arsenic to phosphorus implant dose ratio may be 1:4 to 3: 4.
By the manufacturing method of the invention, a semiconductor device is also formed. As shown in fig. 8, for example, the semiconductor device may include: a semiconductor substrate 20 and a gate structure 21 on the semiconductor substrate 20. For example, the gate structure 21 may include: a gate dielectric layer 211 on the semiconductor substrate 20, a gate electrode 212 on the gate dielectric layer 211, and spacer layers 213 on sides of both sides of the gate electrode 212, respectively.
In one embodiment, as shown in fig. 8, the semiconductor substrate 20 may include a well region 201, wherein the gate structure 21 is above the well region 201. Optionally, the semiconductor substrate 20 may further include a trench isolation portion 202 formed around the well region 201. Optionally, the semiconductor substrate 20 may further include: a first doped region 31 and a second doped region 32 in the well 201 and on both sides of the gate 202, respectively.
As shown in fig. 8, the semiconductor device may further include: an amorphous material layer 50 on the semiconductor substrate 20 and on at least one side of the gate structure 21. Preferably, as shown in fig. 8, the amorphous material layer may include: an amorphous material layer 50 on the semiconductor substrate 20 and on both sides of the gate structure 21, respectively. A spacer layer 213 isolates the polycrystalline material layer 50 from the gate electrode 212. The amorphous material layer 50 may include: arsenic. For example, the amorphous material layer 50 may have a thickness of
To
(e.g. in
Or
Etc.). For example, the amorphous material layer may be amorphous silicon.
As shown in fig. 8, the semiconductor device may further include: a source and/or drain under the amorphous material layer 50 and in the semiconductor substrate 20. Preferably, as shown in fig. 8, the source and/or drain may include: a source electrode 71 and a drain electrode 72 below the amorphous material layer 50, in the semiconductor substrate 20, and on both sides of the gate structure 21, respectively. In one embodiment, the doping concentration of the source 71 and the drain 72 is greater than the doping concentration of the first doping region 31 and the second doping region 32, respectively. In one embodiment, the well 201 may be P-type, and the source 71 and the drain 72 may be N-type. In another embodiment, the well 201 may be N-type, and the source 71 and the drain 72 may be P-type.
In the semiconductor device according to the embodiment of the invention, since the amorphous material layer is used on the source and the drain, the diffusion of the dopant can be more uniform, and thus the uniformity of the holding current of the device can be improved.
Fig. 9 is a graph showing the distribution of the detected holding current of the SRAM, where curve (1) shows the distribution of the holding current of the SRAM manufactured using the conventional semiconductor device, and curve (2) shows the distribution of the holding current of the SRAM manufactured using the semiconductor device according to the embodiment of the present invention (e.g., an NMOS device formed by implanting arsenic into a polysilicon layer and passing through other steps). The two curves in fig. 9 are the distribution plots of the total sustain current measured using the 4M SRAM, respectively. Comparing the two curves, it is found that the distribution of the curve (2) is more concentrated than that of the curve (1), which indicates that the distribution of the holding current of the SRAM manufactured using the semiconductor device of the embodiment of the present invention converges more uniformly.
Thus far, the method of manufacturing a semiconductor device and the resulting semiconductor device according to the present invention have been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor structure, the semiconductor structure comprising: the semiconductor device comprises a semiconductor substrate and a gate structure on the semiconductor substrate;
forming a polycrystalline material layer on the semiconductor substrate and on at least one side of the gate structure;
performing an amorphization process on the polycrystalline material layer such that the polycrystalline material layer becomes an amorphous material layer, wherein the step of performing an amorphization process on the polycrystalline material layer comprises: performing a first ion implantation on the polycrystalline material layer to amorphize the polycrystalline material layer; wherein the ions implanted by the first ion implantation comprise: arsenic ions;
performing doping on the amorphous material layer to dope a dopant in the amorphous material layer; and
and performing an annealing treatment so that the dopant enters the semiconductor substrate to form a source electrode and/or a drain electrode below the amorphous material layer.
2. The method of claim 1,
in performing the first ion implantation, an implantation energy of the first ion implantation is determined according to a thickness of the polycrystalline material layer so that the first ion implantation can amorphize the polycrystalline material layer and a depth of the implanted ions does not exceed the polycrystalline material layer.
3. The method of claim 1,
the implantation energy of the first ion implantation ranges from 5KeV to 50 KeV;
the first ion implantation has an implantation dose in the range of 1 × 1013atom/cm2To 1X 1016atom/cm2。
4. The method of claim 1,
the thickness of the polycrystalline material layer is
To
5. The method of claim 1,
the annealing treatment is a rapid thermal annealing process.
6. The method of claim 5,
the annealing temperature range of the rapid thermal annealing process is 950 ℃ to 1100 ℃;
the annealing time of the rapid thermal annealing process ranges from 5 seconds to 20 seconds.
7. The method of claim 1,
the polycrystalline material layer is polycrystalline silicon;
the amorphous material layer is amorphous silicon.
8. The method of claim 1,
the step of forming a layer of polycrystalline material on the semiconductor substrate and on at least one side of the gate structure comprises: forming polycrystalline material layers on the semiconductor substrate and on two sides of the gate structure respectively;
the step of performing an annealing process so that the dopants enter the semiconductor substrate to form a source and/or drain below the layer of amorphous material comprises: and performing annealing treatment so that the dopant is diffused into the semiconductor substrate to form a source electrode and a drain electrode below the amorphous material layer, in the semiconductor substrate and on two sides of the gate structure respectively.
9. The method of claim 1,
in the step of providing the semiconductor structure, the gate structure includes: a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and spacer layers on sides of both sides of the gate, respectively;
wherein, in the step of forming the polycrystalline material layer, the spacer layer isolates the polycrystalline material layer from the gate electrode.
10. The method of claim 1, wherein the step of doping the amorphous material layer comprises:
performing a second ion implantation on the amorphous material layer to implant dopants in the amorphous material layer.
11. The method of claim 10,
in the step of providing the semiconductor structure, the semiconductor substrate includes: a well region, wherein the gate structure is over the well region;
the well region is of a P type, and the dopant is an N type dopant; or the well region is of an N type, and the dopant is a P type dopant.
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| JPH05291290A (en) * | 1992-04-07 | 1993-11-05 | Nippon Precision Circuits Kk | Manufacture of semiconductor device |
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