CN109215719B - Multifunctional voltage switching circuit for OTP programming - Google Patents
Multifunctional voltage switching circuit for OTP programming Download PDFInfo
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- CN109215719B CN109215719B CN201811398968.9A CN201811398968A CN109215719B CN 109215719 B CN109215719 B CN 109215719B CN 201811398968 A CN201811398968 A CN 201811398968A CN 109215719 B CN109215719 B CN 109215719B
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- 238000006243 chemical reaction Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 11
- 230000006870 function Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000004075 alteration Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application discloses a multifunctional voltage switching circuit for OTP programming, which comprises: the high-voltage switching circuit comprises a high-voltage selection circuit, a switching control circuit, a first PMOS switch, a second PMOS switch and a logic judgment circuit; the pin of the switching circuit comprises: VPP, VDD, PRGM, VPRG and SLG; the switching function of the programming/non-programming voltage of the OTP programming pin is integrated into the chip for implementation, so that an external voltage switching circuit of the chip is not needed during termination, and the design is simplified; meanwhile, when the programming pin of the OTP is not programmed, the OTP can be multiplexed into a logic control pin, so that the pin resource of a chip is saved.
Description
Technical Field
The application relates to the field of digital-analog hybrid integrated circuits, in particular to a multifunctional voltage switching circuit for OTP programming.
Background
Many chips, especially sensor related chips, require an internal integration of OTP (one time programmable non-volatile memory) for calibration, parameter configuration, etc. Such chips require an OTP programming pin to input a high level during OTP programming and a fixed high or low level during non-programming. The miniaturization requirement of the chip is higher and higher, the chip packaging pins are required to be smaller and smaller, and the chip pin resources are short.
Disclosure of Invention
The multifunctional voltage switching circuit integrates the switching function of the programming/non-programming voltage of the OTP programming pin into the chip to realize, so that the external voltage switching circuit of the chip is not needed during the termination, and the design is simplified. Meanwhile, when the programming pin of the OTP is not programmed, the OTP can be multiplexed into a logic control pin, so that the pin resource of a chip is saved.
In order to achieve the above object, the present application provides a multifunctional voltage switching circuit for OTP programming, which realizes two functions:
1, finishing switching of OTP programming/non-programming voltage in a chip;
2, the function multiplexing of the OTP programming pin is realized, and the OTP programming pin can be used for the input of OTP programming high voltage and can also be used as logic control input.
The application provides a multifunctional voltage switching circuit for OTP programming, which comprises: the high-voltage switching circuit comprises a high-voltage selection circuit, a switching control circuit, a first PMOS switch, a second PMOS switch and a logic judgment circuit; the pins of the circuit include: VPP, VDD, PRGM, VPRG and SLG.
VPP is a multiplexing pin, which can be used as OTP programming high voltage input or logic signal; VDD is a low voltage power supply; PRGM is OTP programming control pin; VPRG is the programming voltage output pin; SLG is a logic output signal.
The high-voltage selection circuit is connected with VPP and VDD, and the output pin VO of the high-voltage selection circuit is connected with the high-voltage power supply VDDH of the switch control circuit; the input of the switch control circuit is PRGM, and the output K1 and the output K2 are respectively connected with the grid electrodes of the first PMOS switch and the second PMOS switch to control the PMOS switch to be closed and opened; the drain electrode of the first PMOS switch is connected with VDD, the source electrode of the first PMOS switch is connected with VPRG, and the substrate of the first PMOS switch can be suspended or connected with VPRG; the drain electrode of the second PMOS switch is connected with VPP, the source electrode of the second PMOS switch is connected with VPRG, and the substrate of the second PMOS switch is suspended; the input of the logic judgment circuit is connected with the VPP, and the logic judgment circuit outputs a logic signal according to the VPP level;
the high voltage selection circuit includes: third PMOS switch and fourth PMOS switch. The source electrode of the third PMOS switch is connected with VPP, and the drain electrode of the third PMOS switch is connected with the output pin VO of the high-voltage selection circuit; the fourth PMOS switch has a source connected to VDD and a drain connected to the high voltage select circuit output pin VO.
The switch control circuit comprises a first inverter, a first level conversion circuit and a second level conversion circuit; the programming control pin PRGM is an input end and is connected with the input of the first inverter and the input of the first level conversion circuit, the output of the first inverter is connected with the input of the level conversion circuit, the output of the level conversion circuit is connected with the output K1 of the switch control circuit, the output of the second level conversion circuit is connected with the output K2 of the switch control circuit, and the high-voltage power supplies of the first level conversion circuit and the second level conversion circuit are connected with VDDH.
Wherein the level shift circuit includes: a fifth PMOS switch, a sixth PMOS switch, a seventh PMOS switch, an eighth PMOS switch, a first NMOS switch and a second NMOS switch; the source electrode and the substrate of the fifth PMOS switch are connected to the VDDH, the grid electrode of the fifth PMOS switch is connected with the drain electrode of the sixth PMOS switch and is connected to the output OH of the level converter, the grid electrode of the sixth PMOS switch is connected with the drain electrode of the fifth PMOS switch, the grid electrodes of the seventh PMOS switch and the eighth PMOS switch are connected to a bias voltage VB, the source electrode of the seventh PMOS switch is connected with the drain electrode of the fifth PMOS switch, the source electrode of the eighth PMOS switch is connected with the drain electrode of the sixth PMOS switch and is connected to the output OH of the level converter, the drain electrode of the seventh PMOS switch is connected with the drain electrode of the first NMOS switch, the drain electrode of the eighth PMOS switch is connected with the drain electrode of the second NMOS switch, the grid electrode of the first NMOS switch (15) is connected with the input IL of the level converter, the grid electrode of the second NMOS switch is connected with the output IL of the second inverter, the source electrode of the first NMOS switch and the substrate are connected with the ground, and the input IL of the second inverter is connected with the input IL of the level converter.
The logic judgment circuit converts the level signal of the VPP into a logic signal, and the output pin of the logic signal is SLG; the logic signal conversion function may be implemented with inverters, comparators, etc.
The one or more technical schemes provided by the application have at least the following technical effects or advantages:
the multifunctional voltage switching circuit integrates the switching function of the programming/non-programming voltage of the OTP programming pin into the chip for implementation, so that the external voltage switching circuit of the chip is not needed in the final process, and the design is simplified. Meanwhile, when the programming pin of the OTP is not programmed, the OTP can be multiplexed into a logic control pin, so that the pin resource of a chip is saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application;
FIG. 1 is a schematic diagram of a multi-functional voltage switching circuit for OTP programming according to the present application;
FIG. 2 is a schematic diagram of a high voltage selection circuit according to the present application;
FIG. 3 is a schematic diagram of a switch control circuit according to the present application;
fig. 4 is a schematic diagram of an implementation of the level shifter circuit of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced in other ways than within the scope of the description, and the scope of the application is therefore not limited to the specific embodiments disclosed below.
Referring to fig. 1-3, the circuit provided by the present application includes: a high voltage selection circuit 1, a switch control circuit 2, a first PMOS switch 3, a second PMOS switch 4, and a logic judgment circuit 5.
The pins of the circuit include: VPP, VDD, PRGM, VPRG and SLG.
VPP is a multiplexing pin, which can be used as OTP programming high voltage input or logic signal; VDD is a low voltage power supply; PRGM is OTP programming control pin; VPRG is the programming voltage output pin; SLG is a logic output signal.
The high voltage selection circuit 1 is connected with VPP and VDD, and the output pin VO of the high voltage selection circuit 1 is connected with the high voltage power supply VDDH of the switch control circuit; the input of the switch control circuit 2 is PRGM, and the outputs K1 and K2 are respectively connected with the grid electrodes of the first PMOS switch 3 and the second PMOS switch 4 to control the PMOS switch to be closed and opened; the drain electrode of the first PMOS switch 3 is connected with VDD, the source electrode is connected with VPRG, and the substrate of the first PMOS switch 3 can be suspended or connected with VPRG; the drain electrode of the second PMOS switch 4 is connected with VPP, the source electrode is connected with VPRG, and the substrate of the second PMOS switch 4 is suspended; the input of the logic judgment circuit 5 is connected with VPP, and the logic judgment circuit 5 outputs a logic signal according to the VPP level;
in order for the first PMOS switch 3 and the second PMOS switch 4 to be properly turned off, the gate voltage of the PMOS switch must be equal to or greater than the source voltage. The PMOS switch gate voltage can ensure that the PMOS switch is properly turned off when it reaches the higher of VPP and VDD. Therefore, the application adopts the high voltage selection circuit 1 to select the higher voltage of VPP and VDD to be input into the switch control circuit, so that the high level of the switch control signal is the higher voltage of VPP and VDD.
The high voltage selection circuit 1 includes: a third PMOS switch 6 and a fourth PMOS switch 7. The source electrode of the third PMOS switch 6 is connected with VPP, and the drain electrode is connected with the output pin VO of the high-voltage selection circuit 1; the source of the fourth PMOS switch 7 is connected to VDD, and the drain is connected to the output pin VO of the high voltage selection circuit 1.
With this circuit, not only can a higher level be selected for input into the switch control circuit, but also the circuit allows the VPP voltage to be varied from 0V to the high voltage required for OTP programming. Therefore, VPP can be multiplexed as a logic control pin, so that pin resources of a chip are saved.
The switch control circuit 2 is composed of a first inverter 8, a first level shift circuit 9, and a second level shift circuit 10; the programming control pin PRGM is an input terminal connected to the input of the first inverter 8 and the input of the first level shifter circuit 9, the output of the first inverter 8 is connected to the input of the second level shifter circuit 10, the output of the first level shifter circuit 9 is connected to the output K1 of the switch control circuit 2, the output of the second level shifter circuit 10 is connected to the output K2 of the switch control circuit 2, and the high voltage power supplies of the first level shifter circuit 9 and the second level shifter circuit 10 are connected to VDDH.
The purpose of the switch control circuit is to generate the correct switch control signal. The high voltage power supply of the first level shifter circuit 7 and the second level shifter circuit 8 is connected to VDDH, which is connected to the output of the high voltage selector circuit, so that the high level of the switch control signals K1 and K2 is the higher one of VPP and VDD, which can ensure the proper turn-off of the PMOS switches 3 and 4.
Referring to fig. 4, the level shift circuit includes: a fifth PMOS switch 11, a sixth PMOS switch 12, a seventh PMOS switch 13, an eighth PMOS switch 14, and a first NMOS switch 15, a second NMOS switch 16; the source and substrate of the fifth PMOS switch 11, the sixth PMOS switch 12 are connected to VDDH, the gate of the fifth PMOS switch 11 and the drain of the sixth PMOS switch 12 are connected to the output OH of the level shifter, the gate of the sixth PMOS switch 12 and the drain of the fifth PMOS switch 11 are connected, the gates of the seventh PMOS switch 13 and the eighth PMOS switch 14 are connected to a bias voltage VB, the source of the seventh PMOS switch 13 and the drain of the fifth PMOS switch 11 are connected, the source of the eighth PMOS switch 14 and the drain of the sixth PMOS switch 12 are connected to the output OH of the level shifter, the drain of the seventh PMOS switch 13 is connected to the drain of the first NMOS switch 15, the drain of the eighth PMOS switch 14 is connected to the drain of the second NMOS switch 16, the gate of the first NMOS switch 15 is connected to the input IL of the level shifter, the gate of the second NMOS switch 16 is connected to the output of the second inverter 17, the source of the first NMOS switch 15 and the substrate are connected to ground, and the input of the second inverter 17 is connected to the input IL of the level shifter. Wherein, the PMOS13 and PMOS14 function to limit the drain voltages of PMOS11 and PMOS 12; the gates of PMOS13 and PMOS14 are connected to a suitable voltage VB such that the voltage difference between the drains of PMOS11 and PMOS12 and VB is approximately equal to the threshold voltage.
The input signal PRGM of the switch control circuit can be generated directly on-chip, thus switching the OTP program/non-program voltage is accomplished directly on-chip.
The logic judgment circuit converts the level signal of the VPP into a logic signal, the logic signal output pin is SLG, and the logic signal conversion function can be realized by using an inverter, a comparator and the like.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (4)
1. A multifunctional voltage switching circuit for OTP programming, the switching circuit comprising:
the high-voltage switching circuit comprises a high-voltage selection circuit (1), a switch control circuit (2), a first PMOS switch (3), a second PMOS switch (4) and a logic judgment circuit (5); the pin of the switching circuit comprises: VPP, VDD, PRGM, VPRG and SLG;
VPP is a multiplexing pin used as an OTP programming high voltage input or logic control signal input; VDD is a low voltage power supply pin; PRGM is OTP programming control pin; VPRG is the programming voltage output pin; SLG is a logic output pin;
the high-voltage selection circuit (1) is connected with VPP and VDD, and an output pin VO of the high-voltage selection circuit (1) is connected with a high-voltage power supply VDDH of the switch control circuit; the input of the switch control circuit (2) is PRGM, the output K1 is connected with the grid electrode of the first PMOS switch (3), the grid electrode of the second PMOS switch (4) of the output K2 is connected, and the first PMOS switch (3) and the second PMOS switch (4) are respectively controlled to be closed and opened; the drain electrode of the first PMOS switch (3) is connected with VDD, the source electrode is connected with VPRG, and the substrate of the first PMOS switch (3) is suspended or connected with VPRG; the drain electrode of the second PMOS switch (4) is connected with VPP, the source electrode of the second PMOS switch (4) is connected with VPRG, and the substrate of the second PMOS switch (4) is suspended; the input of the logic judging circuit (5) is connected with the VPP, and the logic judging circuit (5) outputs a logic signal according to the VPP level;
the high voltage selection circuit (1) includes: a third PMOS switch (6) and a fourth PMOS switch (7); the source electrode of the third PMOS switch (6) is connected with VPP, the drain electrode is connected with the output pin VO of the high-voltage selection circuit (1), and the grid electrode is connected with VDD; the source electrode of the fourth PMOS switch (7) is connected with VDD, the drain electrode is connected with the output pin VO of the high-voltage selection circuit (1), and the grid electrode is connected with VPP;
the switch control circuit (2) comprises a first inverter (8), a first level conversion circuit (9) and a second level conversion circuit (10); the programming control pin PRGM is used as an input end and is connected with the input of the first inverter (8) and the input of the first level conversion circuit (9), the output of the first inverter (8) is connected with the input of the second level conversion circuit (10), the output of the first level conversion circuit (9) is connected with the output K1 of the switch control circuit (2), the output of the second level conversion circuit (10) is connected with the output K2 of the switch control circuit (2), and the high-voltage power supplies of the first level conversion circuit (9) and the second level conversion circuit (10) are connected with VDDH.
2. A multifunctional voltage switching circuit for OTP programming as claimed in claim 1 wherein the switching circuit is capable of functioning as an OTP programming voltage input and is capable of sharing as a logic control signal input.
3. The multifunctional voltage switching circuit for OTP programming of claim 1 wherein the level shifter circuit comprises: a fifth PMOS switch (11), a sixth PMOS switch (12), a seventh PMOS switch (13), an eighth PMOS switch (14), a first NMOS switch (15) and a second NMOS switch (16); the source and the substrate of the fifth PMOS switch (11), the sixth PMOS switch (12) are connected to VDDH, the grid of the fifth PMOS switch (11) and the drain of the sixth PMOS switch (12) are connected to the output OH of the level shifter, the grid of the sixth PMOS switch (12) and the drain of the fifth PMOS switch (11) are connected, the grid of the seventh PMOS switch (13) and the grid of the eighth PMOS switch (14) are connected to a bias voltage VB, the source of the seventh PMOS switch (13) and the drain of the fifth PMOS switch (11) are connected, the source of the eighth PMOS switch (14) and the drain of the sixth PMOS switch (12) are connected to the output OH of the level shifter, the drain of the seventh PMOS switch (13) is connected to the drain of the first NMOS switch (15), the drain of the eighth PMOS switch (14) is connected to the drain of the second NMOS switch (16), the grid of the first NMOS switch (15) is connected to the input IL of the level shifter, the grid of the second NMOS switch (16) is connected to the output IL of the second inverter (17), the source of the second NMOS switch (16) is connected to the input IL of the second inverter (17).
4. The multifunctional voltage switching circuit for OTP programming according to claim 1, characterized in that the logic judging circuit (5) converts a level signal of VPP into a logic signal, and the logic signal output pin is SLG.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811398968.9A CN109215719B (en) | 2018-11-22 | 2018-11-22 | Multifunctional voltage switching circuit for OTP programming |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811398968.9A CN109215719B (en) | 2018-11-22 | 2018-11-22 | Multifunctional voltage switching circuit for OTP programming |
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| CN109215719A CN109215719A (en) | 2019-01-15 |
| CN109215719B true CN109215719B (en) | 2023-08-25 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331245B (en) * | 2020-11-05 | 2022-11-08 | 湘潭大学 | Voltage selection circuit suitable for nonvolatile memory |
| CN113077826A (en) * | 2021-03-26 | 2021-07-06 | 江苏银河芯微电子有限公司 | Voltage selection circuit and method and memory chip |
| CN113659978B (en) * | 2021-08-26 | 2022-05-20 | 上海芯圣电子股份有限公司 | Multiplexing circuit of VPP port and VPP port reusable chip |
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| JP5110247B2 (en) * | 2006-07-31 | 2012-12-26 | ミツミ電機株式会社 | Semiconductor integrated circuit device |
| US9076513B2 (en) * | 2010-11-03 | 2015-07-07 | Shine C. Chung | Low-pin-count non-volatile memory interface with soft programming capability |
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| CN104851461A (en) * | 2015-05-26 | 2015-08-19 | 矽力杰半导体技术(杭州)有限公司 | Once time programmable storage circuit and operation method thereof |
| CN209000545U (en) * | 2018-11-22 | 2019-06-18 | 四川知微传感技术有限公司 | Voltage switching circuit |
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