CN109216467A - JFET device and its manufacturing method - Google Patents
JFET device and its manufacturing method Download PDFInfo
- Publication number
- CN109216467A CN109216467A CN201710534151.9A CN201710534151A CN109216467A CN 109216467 A CN109216467 A CN 109216467A CN 201710534151 A CN201710534151 A CN 201710534151A CN 109216467 A CN109216467 A CN 109216467A
- Authority
- CN
- China
- Prior art keywords
- region
- doping
- channel
- jfet device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 8
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 210000002186 septum of brain Anatomy 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/051—Manufacture or treatment of FETs having PN junction gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/83—FETs having PN junction gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates
Landscapes
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明涉及一种JFET器件及其制造方法。该JFET器件包括：第一阱区，形成于衬底上，具有第一掺杂类型；第二阱区，形成于衬底上，并具有第二掺杂类型；所述第二阱区设有依次排列的源极区、沟道区和漂移区；其中，所述沟道区设有属于第一阱区的间隔区；所述间隔区将沟道区间隔为至少两段相互间隔的自源极区向漂移区延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压；所述间隔区引出为所述JFET器件的栅极，所述源极区引出为所述JFET器件的源极，所述漂移区表面还形成漏极区并引出为所述JFET器件的漏极。该制造方法用于制造该JFET器件。上述JFET器件及其制造方法成本和工艺复杂度更低。
The present invention relates to a JFET device and a manufacturing method thereof. The JFET device includes: a first well region formed on a substrate and having a first doping type; a second well region formed on the substrate and having a second doping type; the second well region is provided with The source region, the channel region and the drift region are arranged in sequence; wherein, the channel region is provided with a spacer region belonging to the first well region; the spacer region separates the channel region into at least two mutually spaced self-source regions A channel extending from the pole region to the drift region, the width of the channel can adjust the pinch-off voltage of the JFET device; the spacer region is drawn out as the gate of the JFET device, and the source region is drawn out as the JFET device The surface of the drift region also forms a drain region and leads to the drain of the JFET device. The fabrication method is used to fabricate the JFET device. The above-mentioned JFET device and its manufacturing method have lower cost and process complexity.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of JFET device and its manufacturing method.
Background technique
High pressure JFET (Junction Field-Effect Transistor, junction field effect transistor) device is in power supply
It has a wide range of applications in managing chip, facilitates circuit and realize high efficiency, the application demand of low-power consumption.In High voltage BCD process
In production process, be frequently the problem that: conventional high-pressure JFET structure, with same high pressure trap formed device channel region and
Drift region, it is difficult to while meeting pressure resistance and the design requirement of blanking voltage (pitch-off voltage).In order to reach cut-off electricity
The design object of pressure needs specially to increase by one piece of Mask (mask plate), and it is dense that channel region doping is adjusted in such a way that impurity injects
Degree increases the cost and complexity of technique to realize.
Summary of the invention
Based on this, it is necessary to provide and a kind of not need additional mask plate the JFET device of blanking voltage can be adjusted.
In addition, also providing a kind of manufacturing method of JFET device.
A kind of JFET device, comprising:
First well region, is formed on substrate, has the first doping type；
Second well region, is formed on substrate, and has the second doping type；Second well region is equipped with the source being arranged successively
Polar region, channel region and drift region；
Wherein, the channel region is equipped with the spacer region for belonging to the first well region；The spacer region will be divided at least between channel region
Two sections of channels extended from source area to drift region being spaced apart from each other, the width of channel can adjust the pinch off electricity of the JFET device
Pressure；
The spacer region leads to the grid of the JFET device, and the source area leads to the source of the JFET device
Pole, the drift region surface also form drain region and lead to the drain electrode of the JFET device.
The quantity of the spacer region is two or more in one of the embodiments, and is spaced apart from each other.
More than two spacer regions are parallel to each other interval in one of the embodiments,.
The spacer region is upwardly extended in the first party for being directed toward drift region from channel region in one of the embodiments, and
There is fixed width in the second direction vertical with the first direction.
First doping type is n-type doping in one of the embodiments, and second doping type is mixed for p-type
It is miscellaneous；Or first doping type is p-type doping, second doping type is n-type doping.
A kind of manufacturing method of JFET device, comprising:
The first well region is formed on the substrate, first well region has the first doping type；It is equipped in first well region
Spacer region；
The second well region is formed on the substrate, second well region has the second doping type；Second well region be equipped with according to
Source area, channel region and the drift region of secondary arrangement；
The spacer region will be divided into at least two sections channels extended from source area to drift region being spaced apart from each other between channel region,
The width of channel can adjust the pinch-off voltage of the JFET device.
It is in one of the embodiments, two or more in the quantity of the spacer region, and is spaced apart from each other.
More than two spacer regions are parallel to each other interval in one of the embodiments,.
The spacer region is upwardly extended in the first party for being directed toward drift region from channel region in one of the embodiments, and
There is fixed width in the second direction vertical with the first direction.
First doping type is n-type doping in one of the embodiments, and second doping type is mixed for p-type
It is miscellaneous；Or first doping type is p-type doping, second doping type is n-type doping.
The manufacturing method of above-mentioned JFET device, the second well region form the channel region of device, and spacer region forms device
Grid；The width of second well area increases, and device channel region impurity increases, and needing to increase grid voltage could consume completely it
To the greatest extent, i.e., channel is closed；So the width of the second well region of adjustment is the purpose that can reach adjustment blanking voltage.Meanwhile this adjustment
It is not to be realized by the additional impurities injection adjustment doping concentration to channel region, therefore reduce a procedure, namely not
Additional mask plate is needed to cooperate and complete the process.The cost and complexity of technique have corresponding reduction.
Detailed description of the invention
Fig. 1 is the top view that the JFET device of an embodiment is laid out；
Fig. 2 is the section B-B figure in Fig. 1；
Fig. 3 is the Section A-A figure in Fig. 1；
Fig. 4 a is one of arrangement schematic diagram of the channel spacer region of the JFET device of an embodiment；
Fig. 4 b is the wherein another arrangement schematic diagram of the channel spacer region of the JFET device of an embodiment；
Fig. 5 is the JFET device manufacturing method flow chart of an embodiment.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is the top view that the JFET device of an embodiment is laid out.The JFET device includes the first well region 100 and the second trap
Area 200.First well region 100 has the first doping type, and the second well region 200 has the second doping type.Second well region 200
Equipped with the source area 230, channel region 210 and drift region 220 being arranged successively.Wherein, the channel region 210 is equipped with spacer region 300.
The spacer region 300 have the first doping type, spacer region 300 by be divided between channel region 210 at least two sections be spaced apart from each other from
The channel that source area 230 extends to drift region 220, the width of channel can adjust the pinch-off voltage of the JFET device.Described
Septal area 300 leads to the grid of the JFET device, and the source area 230 leads to the source electrode of the JFET device, the drift
220 surface of area is moved also to form drain region 240 and lead to the drain electrode of the JFET device.
Specifically, as shown in Figure 1, multiple spacer regions 300 are from the first direction that channel region 210 is directed toward drift region 220
Extend, and there is fixed width x1 in the second direction vertical with the first direction, corresponding channel region 210 is divided into more
A channel being spaced apart from each other, with the second doping type, and there is width x2.
Channel region 210 is the channel for transporting hole or electronics, and the grid that spacer region 300 is formed is used to control the unlatching of channel
And cut-off.Fig. 2 is the section B-B figure in Fig. 1.Figure it is seen that channel region 210 is connected to drift region 220, in channel region
When 210 well region is not depleted, hole or electronics can enter drift region 220 by channel.
By taking channel region 210 is n-type doping as an example, the N trap at multiple intervals forms the channel for transporting electronics, the control of p-well grid
The unlatching and cut-off of channel.When work, if grid voltage Vgs < 0V, N/P trap knot is reverse-biased, when depletion layer is expanded to N trap fully- depleted,
Channel is closed, and grid voltage at this time is JFET blanking voltage；If grid voltage Vgs > 0V, channel N/P trap knot positively biased, source electrode electricity
Son eventually arrives at drain electrode under drain electric effect, device is in the conductive state at this time by channel pass to drift region.
When the width of N-type well region is larger, channel dopant increases, and needs bigger grid voltage to exhaust channel region impurity
Channel is turned off, blanking voltage is bigger.Therefore, the width of N trap determines the blanking voltage of JFET device.By adjusting N trap
Width is the purpose that can reach adjustment blanking voltage.
Meanwhile this adjustment is realized by the additional impurities injection adjustment doping concentration to channel region 210, because
This does not need to increase additional channel region impurity injection mask plate, reduces process costs and complexity.
In one embodiment, the width of spacer region 300 is uniform, and the width of the N-type trap being separated out is also uniform
's.It is more easier to control when forming spacer region 300 in this way and adjusts.
In the present embodiment, the quantity of the spacer region 300 is multiple, and is spaced apart from each other.In other embodiments, it is spaced
The quantity in area 300 is also possible to two.
More specifically, Fig. 3 is Section A-A figure in Fig. 1, in conjunction with Fig. 3, more than two spacer regions 300 are parallel to each other interval.
In other embodiments, or non-flat row interval.
In the embodiment shown in fig. 1, edge of the length direction of spacer region 300 substantially with drift region is mutually perpendicular to, in this way
It more convenient can make.But the arrangement of spacer region 300 is not limited to that, in other embodiments, can also be it
His arrangement.As shown in fig. 4 a, spacer region 300 is slanting parallel arrangement；As shown in Figure 4 b, spacer region 300 is oblique
Arrangement, but it is not parallel between each other.These arrangements can play the purpose of adjustment blanking voltage.
In a particular embodiment, first doping type is n-type doping, and second doping type is p-type doping；Then
The JFET device is P-channel JFET.Or first doping type is p-type doping, second doping type is mixed for N-type
It is miscellaneous；Then the JFET device is N-channel JFET.
Fig. 5 is the manufacturing method flow chart of the JFET device of an embodiment.It include following step in conjunction with FIG. 1 to FIG. 4 b this method
Rapid S110~S130.
Step S110: being formed on the substrate the first well region 100, and first well region 100 has the first doping type.It is described
First well region 100 includes spacer region 300.
Step S120: being formed on the substrate the second well region 200, and second well region 200 has the second doping type；It is described
Second well region 200 is equipped with source area 230, channel region 210 and the drift region 220 being arranged successively.
The spacer region 300 by be divided between channel region 210 at least two sections be spaced apart from each other prolong from source area 230 to drift region
The channel stretched, the width of channel can adjust the pinch-off voltage of the JFET device.
Specifically, referring to Fig.1, multiple spacer regions 300 prolong from the first direction that channel region 210 is directed toward drift region 220
It stretches, and there is fixed width xp in the second direction vertical with the first direction, corresponding channel region 210 is divided into multiple
The channel being spaced apart from each other, and there is width xn.
Channel region 210 is the channel for transporting hole or electronics, and the grid that spacer region 300 is formed is used to control the unlatching of channel
And cut-off.Fig. 2 is the section B-B figure in Fig. 1.Figure it is seen that channel region 210 is connected to drift region 220, in channel region
When 210 well region is not depleted, hole or electronics can enter drift region 220 by channel.
By taking channel region 210 is n-type doping as an example, the N-type trap at multiple intervals forms the channel for transporting electronics, the grid of p-type
Control the unlatching and cut-off of channel.When work, if grid voltage Vgs < 0V, N/P trap knot is reverse-biased, depletion layer is expanded to N trap and consumes entirely
When to the greatest extent, channel is closed, and grid voltage at this time is JFET blanking voltage；If grid voltage Vgs > 0V, channel N/P trap knot positively biased,
Source electron eventually arrives at drain electrode under drain electric effect, device is on shape at this time by channel pass to drift region
State.
When the width of N-type well region is larger, channel dopant increases, and needs bigger grid voltage to exhaust channel region impurity
Channel is turned off, blanking voltage is bigger.Therefore, the width of N trap determines the blanking voltage of JFET device.By adjusting N trap
Width is the purpose that can reach adjustment blanking voltage.
Meanwhile this adjustment is realized by the additional impurities injection adjustment doping concentration to channel region 210, because
This reduces a procedure, does not need additional mask plate also to cooperate and complete the process.
In one embodiment, the width of spacer region 300 is uniform, and the width of the N-type trap being separated out is also uniform
's.It is more easier to control when forming spacer region 300 in this way and adjusts.
In the present embodiment, the quantity of the spacer region 300 is multiple, and is spaced apart from each other.In other embodiments, it is spaced
The quantity in area 300 is also possible to one or two.
In step s 130, more than two spacer regions are parallel to each other interval.More specifically, Fig. 3 is Section A-A in Fig. 1
Figure, in conjunction with Fig. 3, more than two spacer regions 300 are parallel to each other interval.In other embodiments, or non-flat row interval.
In step s 130, make the spacer region from channel region be directed toward drift region first party upwardly extend, and with
There is fixed width in the vertical second direction of the first direction.In the embodiment shown in fig. 1, the length side of spacer region 300
It is mutually perpendicular to the edge substantially with drift region, more convenient can make in this way.But the arrangement of spacer region 300 and not only
It is limited to this, in other embodiments, can also be other arrangements.As shown in fig. 4 a, spacer region 300 is slanting parallel cloth
It sets；As shown in Figure 4 b, spacer region 300 is diagonally disposed, but not parallel between each other.These arrangements can play
Adjust the purpose of blanking voltage.
In a particular embodiment, first doping type is n-type doping, and second doping type is p-type doping；Then
The JFET device is P-channel JFET.Or first doping type is p-type doping, second doping type is mixed for N-type
It is miscellaneous；Then the JFET device is N-channel JFET.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of JFET device, comprising:
First well region, is formed on substrate, has the first doping type；
Second well region, is formed on substrate, and has the second doping type；Second well region is equipped with the source electrode being arranged successively
Area, channel region and drift region；
Wherein, the channel region is equipped with the spacer region for belonging to the first well region；The spacer region will be divided at least two sections between channel region
The channel extended from source area to drift region being spaced apart from each other, the width of channel can adjust the pinch-off voltage of the JFET device；
The spacer region leads to the grid of the JFET device, and the source area leads to the source electrode of the JFET device, institute
Drift region surface is stated also to form drain region and lead to the drain electrode of the JFET device.
2. JFET device according to claim 1, which is characterized in that the quantity of the spacer region is more than two, and phase
Mutually interval.
3. JFET device according to claim 2, which is characterized in that more than two spacer regions are parallel to each other interval.
4. described in any item JFET devices according to claim 1~3, which is characterized in that the spacer region refers to from channel region
It is upwardly extended to the first party of drift region, and there is fixed width in the second direction vertical with the first direction.
5. JFET device according to claim 1, which is characterized in that first doping type is n-type doping, described the
Two doping types are p-type doping；Or first doping type is p-type doping, second doping type is n-type doping.
6. a kind of manufacturing method of JFET device, comprising:
The first well region is formed on the substrate, first well region has the first doping type；Interval is equipped in first well region
Area；
The second well region is formed on the substrate, second well region has the second doping type；Second well region is equipped with and successively arranges
Source area, channel region and the drift region of column；
The spacer region will be divided into at least two sections channels extended from source area to drift region being spaced apart from each other, channel between channel region
Width can adjust the pinch-off voltage of the JFET device.
7. the manufacturing method of JFET device according to claim 6, which is characterized in that the spacer region quantity be two
More than a, and it is spaced apart from each other.
8. the manufacturing method of JFET device according to claim 7, which is characterized in that more than two spacer regions are mutually flat
Row interval.
9. according to the manufacturing method of the described in any item JFET devices of claim 6~8, which is characterized in that the spacer region exists
The first party for being directed toward drift region from channel region upwardly extends, and has in the second direction vertical with the first direction and fix
Width.
10. the manufacturing method of JFET device according to claim 6, which is characterized in that first doping type is N-type
Doping, second doping type are p-type doping；Or first doping type is p-type doping, second doping type
For n-type doping.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710534151.9A CN109216467B (en) | 2017-07-03 | 2017-07-03 | JFET device and manufacturing method thereof |
| PCT/CN2018/094229 WO2019007320A1 (en) | 2017-07-03 | 2018-07-03 | Jfet device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710534151.9A CN109216467B (en) | 2017-07-03 | 2017-07-03 | JFET device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109216467A true CN109216467A (en) | 2019-01-15 |
| CN109216467B CN109216467B (en) | 2021-01-05 |
Family
ID=64950430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710534151.9A Active CN109216467B (en) | 2017-07-03 | 2017-07-03 | JFET device and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109216467B (en) |
| WO (1) | WO2019007320A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080272395A1 (en) * | 2007-05-03 | 2008-11-06 | Dsm Solutions, Inc. | Enhanced hole mobility p-type jfet and fabrication method therefor |
| US20100032729A1 (en) * | 2008-08-07 | 2010-02-11 | Texas Instruments Incorporated | Integration of high voltage jfet in linear bipolar cmos process |
| CN102254827A (en) * | 2010-05-20 | 2011-11-23 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN103367400A (en) * | 2012-03-30 | 2013-10-23 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN104518034A (en) * | 2014-06-17 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | JFET (junction field-effect transistor) device and manufacturing method thereof |
| CN104900695A (en) * | 2014-03-03 | 2015-09-09 | 无锡华润上华半导体有限公司 | Power-junction-type field effect transistor and manufacturing method thereof |
-
2017
- 2017-07-03 CN CN201710534151.9A patent/CN109216467B/en active Active
-
2018
- 2018-07-03 WO PCT/CN2018/094229 patent/WO2019007320A1/en not_active Ceased
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080272395A1 (en) * | 2007-05-03 | 2008-11-06 | Dsm Solutions, Inc. | Enhanced hole mobility p-type jfet and fabrication method therefor |
| US20100032729A1 (en) * | 2008-08-07 | 2010-02-11 | Texas Instruments Incorporated | Integration of high voltage jfet in linear bipolar cmos process |
| CN102254827A (en) * | 2010-05-20 | 2011-11-23 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN103367400A (en) * | 2012-03-30 | 2013-10-23 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN104900695A (en) * | 2014-03-03 | 2015-09-09 | 无锡华润上华半导体有限公司 | Power-junction-type field effect transistor and manufacturing method thereof |
| CN104518034A (en) * | 2014-06-17 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | JFET (junction field-effect transistor) device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109216467B (en) | 2021-01-05 |
| WO2019007320A1 (en) | 2019-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102714224B (en) | Power semiconductor devices having selectively doped JFET regions and related methods of forming such devices | |
| US8829608B2 (en) | Semiconductor device | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN100550415C (en) | Semiconductor device and manufacture method thereof | |
| JP6588340B2 (en) | Nitride power device and manufacturing method thereof | |
| WO2002103807A1 (en) | Lateral junction type field effect transistor | |
| JPH05259443A (en) | Insulation gate type semiconductor device | |
| CN110459602A (en) | Device with vertical floating field plate and method of making the same | |
| US10290726B2 (en) | Lateral insulated gate bipolar transistor | |
| CN104518034A (en) | JFET (junction field-effect transistor) device and manufacturing method thereof | |
| CN108365007A (en) | Insulated gate bipolar transistor | |
| CN109216431A (en) | The lateral diffusion metal-oxide-semiconductor structure and manufacturing method of completely isolated type | |
| KR101685572B1 (en) | SiC MOSFET for decreasing electric field of bottom oxide and method for manufacturing thereof | |
| US20140197467A1 (en) | High voltage junction field effect transistor structure | |
| CN101364617B (en) | JFET and manufacturing method of the same | |
| CN107785365A (en) | It is integrated with the device and its manufacture method of junction field effect transistor | |
| CN109346525A (en) | A kind of N-type LDMOS device and its manufacturing method | |
| WO2022127165A1 (en) | P-type gate hemt device | |
| CN108063163A (en) | Anode grid MOS thyristor and process method thereof | |
| CN103094319A (en) | Pinch-off voltage reducing structure of dual-channel high voltage junction field effect transistor (FET) and manufacturing method thereof | |
| CN109216467A (en) | JFET device and its manufacturing method | |
| CN103094124B (en) | The structure of fetron and manufacture method | |
| CN102354708B (en) | Tunneling field effect transistor structure with suspended source and drain regions and forming method thereof | |
| KR20190124894A (en) | Semiconductor device and method manufacturing the same | |
| CN117730417A (en) | Power semiconductor devices and manufacturing methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |