CN109272960B - Gate drive circuit and display device - Google Patents
Gate drive circuit and display device Download PDFInfo
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- CN109272960B CN109272960B CN201811345191.XA CN201811345191A CN109272960B CN 109272960 B CN109272960 B CN 109272960B CN 201811345191 A CN201811345191 A CN 201811345191A CN 109272960 B CN109272960 B CN 109272960B
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application discloses gate drive circuit, including cascaded a plurality of gate drive units, its characterized in that, a plurality of gate drive units include respectively: the input module is connected with the first node and charges the first node according to the first starting signal and the second starting signal; the first output module is connected with the input module at a first node, generates a current-stage grid driving signal according to the first clock signal and provides the current-stage grid driving signal at an output end; the second output module is connected with the input module and the first node and generates a current-stage transmission signal according to the first clock signal; the first pull-down module is used for pulling down the first node to a low level signal under the control of the second clock signal; and the stabilizing module is used for maintaining the grid signal at the current level under the control of the first clock signal and the second clock signal, and the grid driving circuit can realize a narrow frame and low power consumption display device and reduce the occurrence of the cross striation phenomenon.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit and a display device.
Background
The liquid crystal display device is a display device in which the light transmittance of a light source is changed by utilizing a phenomenon that the alignment direction of liquid crystal molecules is changed by an electric field. Liquid crystal display devices have been widely used in mobile terminals such as mobile phones and large-sized display panels such as flat panel televisions due to advantages of good display quality, small volume, and low power consumption. Most of the liquid crystal displays in the market are projection type liquid crystal displays (lcds), which include a liquid crystal panel and a backlight module (backlight module). The liquid crystal panel has the working principle that liquid crystal molecules are placed between two parallel glass substrates, and a driving voltage is applied to the two glass substrates to control the rotation direction of the liquid crystal molecules, so that the light emission of the backlight module is modulated to generate a picture.
In recent years, the development of liquid crystal display devices has shown a trend of high integration and low cost, and integrated display driving is becoming a research focus of flat panel display technology. The integrated display driving circuit is realized by using a switching Transistor (TFT) as a peripheral circuit such as a gate driving circuit and a source driving circuit, and is formed on a TFT substrate together with a pixel switching Transistor. Compared with the traditional circuit (IC) driving mode, the method adopting integrated gate driving can not only reduce the number of peripheral driving chips and the press sealing procedure thereof and reduce the cost, but also make the periphery of the display thinner, make the display module more compact and enhance the mechanical and electrical reliability.
The basic working principle of the liquid crystal panel and the driving circuit is as follows: the gate driving circuit sends a gate driving signal to the gate lines through pull-up transistors electrically connected with the gate lines, sequentially turns on the TFTs in each row, and then the source driving circuit simultaneously charges the pixel units in an entire row to respective required voltages to display different gray scales. That is, the gate driving circuit of the first row turns on the thin film transistor of the first row through the pull-up transistor, and then the source driving circuit charges the pixel unit of the first row. When the pixel units in the first row are charged, the grid driving circuit turns off the thin film transistors in the row, then the grid driving circuit in the second row turns on the thin film transistors in the second row through the pull-up transistors of the grid driving circuit in the second row, and then the source driving circuit charges the pixel units in the second row. In this sequence, when the pixel cells in the last row are fully charged, the pixel cells in the first row are charged again.
However, for a large-sized liquid crystal display device, the load driven by the gate driving circuit is large, and the requirement for uniformity of display is high, so that the gate driving circuit is required to output a gate driving signal with a large and stable voltage value.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a gate driving circuit and a display device, which can output a stable gate driving signal with a large voltage value, and which is advantageous for a narrow frame design and has low power consumption.
According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of gate driving units cascaded, the plurality of gate driving units respectively including: the input module is connected with the first node and charges the first node according to the first starting signal and the second starting signal; the first output module is connected with the input module and the first node, generates a current-stage grid driving signal according to a first clock signal, and provides the current-stage grid driving signal at an output end; the second output module is connected with the input module and the first node and generates a current-stage transmission signal according to the first clock signal; the first pull-down module is connected with the first node and pulls down the first node to a low-level signal under the control of a second clock signal; and a stabilizing module, connected to the first node and the output terminal, for maintaining the current-stage gate signal at the low-level signal under the control of the first clock signal and the second clock signal.
Preferably, the plurality of gate driving units include a start-stage gate driving unit cascaded in a first stage and a second stage and a plurality of first intermediate-stage gate driving units outside the start-stage gate driving unit, and the first start signal and the second start signal of each start-stage gate driving unit are first external start signals provided outside the gate driving circuit; the first start signal of each first intermediate stage gate driving unit is the current stage gate driving signal provided by the previous stage gate driving unit separated by one stage, and the second start signal is the current stage transfer signal provided by the previous stage gate driving unit separated by one stage.
Preferably, the input module further receives a third start signal and a fourth start signal, and charges and discharges the first node according to the third start signal and the fourth start signal.
Preferably, the plurality of gate driving units include a termination stage gate driving unit cascaded at a last stage and a penultimate stage and a plurality of second intermediate stage gate driving units outside the termination stage gate driving unit, and a third start signal and a fourth start signal of each of the termination stage gate driving units are respectively second external start signals provided outside the gate driving circuit; the third start signal of each second intermediate-stage gate driving unit is the current-stage gate driving signal provided by the next-stage gate driving unit separated by one stage, and the fourth start signal is the current-stage transfer signal provided by the next-stage gate driving unit separated by one stage.
Preferably, the stabilizing module comprises: a first stabilizing module, configured to maintain the current-stage gate signal at the low-level signal according to the first clock signal; and a second stabilizing module, configured to maintain the current-stage gate signal at the low-level signal according to the second clock signal, where the first stabilizing module and the second stabilizing module are alternately turned on when the gate driving unit operates.
Preferably, the input module includes: and the control end of the first switch tube receives the second starting signal, the first access end receives the first starting signal, and the second access end is connected with the first node.
Preferably, the first output module includes: a control end of the second switch tube is connected with the first node, a first path end is used for receiving the first clock signal, and a second path end is used for generating a current-stage grid driving signal; and the first capacitor is connected between the control end of the second switch tube and the second path end.
Preferably, the second output module includes: and a control end of the sixteenth switching tube is connected with the first node, a first path end is used for receiving the first clock signal, and a second path end is used for generating the current-stage transmission signal.
Preferably, the first pull-down module includes: and a control end of the third switching tube is used for receiving the second clock signal, a first path end is connected with the first node, and a second path end is used for receiving the low-level signal.
Preferably, the second pull-down module includes: a control end of the fourth switching tube is connected to the first node, a first path end is used for receiving the low level signal, and a second path end and the stabilizing module are connected to a second node; and the control end of the fifth switching tube is connected to the first node, the first path end is used for receiving the low-level signal, and the second path end and the stabilizing module are connected to the third node.
Preferably, the first stabilizing module comprises: the control end of the sixth switching tube is in short circuit with the first path end to receive the first clock signal, and the second path end is connected to the second node; the control end of the eighth switching tube is connected to the second node, the first path end is connected with the first node, and the second path end is used for receiving the low-level signal; a ninth switching tube, a control end of which is connected to the second node, a first path end of which is connected with the output end of the current-stage gate driving signal, and a second path end of which is used for receiving the low-level signal; and the control end of the tenth switching tube is connected to the second node, the first path end is connected with the current-stage transmission signal output end, and the second path end is used for receiving the low-level signal.
Preferably, the second stabilizing module comprises: the control end of the eleventh switch tube is in short circuit with the first path end to receive the second clock signal, and the second path end is connected to the third node; a thirteenth switching tube, wherein a control end is connected to the third node, a first path end is connected to the first node, and a second path end is used for receiving the low level signal; a fourteenth switching tube, a control end of which is connected to the third node, a first path end of which is connected to the output end of the current-stage gate driving signal, and a second path end of which is used for receiving the low-level signal; and the control end of the fifteenth switching tube is connected to the third node, the first path end is connected with the current-stage transmission signal output end, and the second path end is used for receiving the low-level signal.
Preferably, the stabilizing module further comprises: a seventh switch tube, a control end receives the first clock signal, a first path end is used for receiving the low level signal, and a second path end is connected to the third node; a twelfth switching tube, wherein the control end receives the second clock signal, the first path end is used for receiving the low level signal, and the second path end is connected to the second node; when the first clock signal is active, the seventh switch tube is turned on to provide the low level signal to the third node, and when the second clock signal is active, the twelfth switch tube is turned on to provide the low level signal to the second node.
According to another aspect of the present invention, there is provided a display device, comprising: the gate driving circuit is used for providing a plurality of gate driving signals; a data driving circuit for providing a plurality of gray scale data; and a display panel including a plurality of pixel units arranged in an array, and a plurality of gate lines and a plurality of data lines, the display panel receiving the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel units by row, and receiving the plurality of gray-scale data via the plurality of data lines by column, to provide to the selected pixel units to implement image display.
The embodiment of the invention discloses a gate driving circuit and a display device. When one of the grid driving units is used for pixel charging, only the pixels separated from the grid driving unit by one level are pre-charged, the number of the grid lines which are simultaneously opened is reduced, the overlapping period of output waveforms of the adjacent grid driving units is reduced, the phenomenon of cross striation during display can be avoided, and the display quality of the display device is improved.
In a preferred embodiment, the gate driving unit provided by the invention only needs two clock signals and one externally provided starting signal, thereby reducing the number of signal lines and the load of the signal lines, reducing the required wiring area, being beneficial to the design of a narrow frame and being beneficial to reducing the power consumption of a circuit.
In a preferred embodiment, the transfer signal and the gate driving signal of each gate driving unit are output through different terminals, so that the influence of signal transfer on gate driving is reduced, and the output capability of the gate driving unit is strong.
In a preferred embodiment, a gate driving circuit capable of bidirectional scanning is provided, which has two modes of forward scanning and reverse scanning, increases the degree of freedom of the display panel, and provides an elastic driving method for the liquid crystal display panel.
In a preferred embodiment, the first stabilizing module and the second stabilizing module are opened alternately, so that the stability is good. Also, power consumption of a display device employing the gate driving unit can be effectively reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating an architecture of an nth-stage gate driving unit in a gate driving circuit according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an nth-stage gate driving unit in the gate driving circuit according to the first embodiment of the present invention.
Fig. 3 shows a circuit diagram of a gate driving unit according to a first embodiment of the present invention.
Fig. 4 shows a schematic block diagram of a 12-stage gate driving unit in the gate driving circuit of the embodiment of the present invention.
Fig. 5 illustrates a timing diagram of clock signals and enable signals of the gate driving circuit of fig. 3.
Fig. 6 shows an operation waveform diagram of the gate driving unit according to the first embodiment of the present invention.
Fig. 7 illustrates waveforms of gate driving signals of a plurality of gate driving units according to the first embodiment of the present invention.
Fig. 8 shows a circuit schematic diagram of a gate driving unit according to a second embodiment of the present invention.
Fig. 9 shows a circuit schematic diagram of a gate driving unit according to a third embodiment of the present invention.
Fig. 10 shows a circuit schematic diagram of a gate driving unit according to a fourth embodiment of the present invention.
Fig. 11 shows a circuit schematic diagram of a gate driving unit according to a fifth embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The gate driving circuit (also referred to as a shift register) of the present invention includes a plurality of stages of gate driving units (also referred to as shift register units), each stage of the gate driving units being electrically connected to each row of the gate lines on the display panel, respectively, so as to sequentially apply a gate driving signal to each row of the gate lines, and a connection relationship between the gate driving units will be described in detail below.
Fig. 1 is a schematic diagram illustrating an architecture of an nth-stage gate driving unit in a gate driving circuit according to a first embodiment of the present invention. The gate driving circuit of the present embodiment includes a plurality of stages of gate driving units as shown in fig. 1, and the nth stage of gate driving unit is used for driving a corresponding gate line on the display panel. As shown in fig. 1, each stage of the gate driving unit includes a previous stage signal input terminal 11, a first clock signal input terminal 12, a second clock signal input terminal 13, a low level signal input terminal 14, and a present stage signal output terminal 15. The previous stage signal input terminal 11 is configured to receive a current stage gate driving signal and a current stage transmission signal of a previous stage gate driving unit. In some embodiments of the present invention, the preceding stage signal input 11 is also used for receiving the enable signal. The first clock signal input 12 and the second clock signal input 13 are for receiving a clock signal. The low level signal input terminal 14 is used for receiving a low level signal. The present-stage signal output terminal 15 is configured to output a present-stage gate driving signal and a present-stage transmission signal, where the present-stage gate driving signal is used to drive a gate line corresponding to the nth-stage gate driving unit, and the present-stage transmission signal is used to control a pre-charging process of the next-stage gate driving unit.
Fig. 2 is a schematic structural diagram of an nth-stage gate driving unit in the gate driving circuit according to the first embodiment of the present invention. As shown in fig. 2, the gate driving unit 100 includes an input module 110, a first output module 120, a second output module 130, a first pull-down module 140, a second pull-down module 150, and a stabilization module 160.
The input module 110 has an input terminal connected to the previous stage signal input terminal in fig. 1 for receiving the upper stage driving signal Gn-2 and the upper stage transfer signal Zn-2, and an output terminal connected to the first node Q for precharging the first node Q according to the upper stage driving signal Gn-2 and the upper stage transfer signal Zn-2. Referring to fig. 1 in combination, the first output module 120 is connected to the first node Q and the first clock signal input terminal 12 to output the received clock signal CLK1 as the present-stage gate driving signal Gn according to the control voltage of the first node Q. The second output module 130 is connected to the first node Q and the first clock signal input terminal to output the received clock signal CLK1 as the present-stage transfer signal Zn according to the control voltage of the first node Q. The first pull-down module 140 is connected to the second clock signal input terminal and the low level signal input terminal to receive the clock signal CLK3 and the low level signal VGL, respectively, for providing the low level signal VGL to the first node Q to pull down the potential of the first node Q according to the received clock signal CLK 3. The second pull-down module 150 is connected to the first node Q, the low level signal input terminal, and the stabilizing module 160, and is configured to provide the low level signal VGL to the stabilizing module 160 according to the control voltage of the first node Q. The stabilizing module 160 is connected to the first clock signal input terminal, the second clock signal input terminal, and the low level signal input terminal, and is configured to alternately provide the low level signal VGL to the first node Q, the present stage gate driving signal output terminal, and the present stage transfer signal output terminal according to the clock signal CLK1 and the clock signal CLK 3.
The gate driving unit of the embodiment of the present invention only needs 3 signal lines connected to the main path for receiving 2 clock signals and the low level signal VGL, respectively, and 1 signal line connected to the adjacent gate driving unit for receiving the previous stage gate driving signal Gn-2 and the previous stage transfer signal Zn-2. The clock signal input end of the adjacent gate driving unit and the clock signal input end of the adjacent gate driving unit receive different clock signals. For example, the first stage gate drive unit receives the clock signal CLK1 and the clock signal CLK3, the third stage gate drive unit receives the clock signal CLK2 and the clock signal CLK4, and so on.
Fig. 3 shows a circuit diagram of a gate driving unit according to a first embodiment of the present invention. As shown in fig. 3, the input module 310 includes a first switch T1, a control terminal of the first switch T1 receives the previous-stage transmission signal Zn-2, a first path terminal receives the previous-stage gate driving signal Gn-2, and a second path terminal is connected to the first node Q.
The first output module 120 includes a second switch transistor T2 and a first capacitor C1, a control terminal of the second switch transistor T2 is connected to the first node Q, a first path terminal is connected to the first clock signal input terminal to receive the clock signal CLK1, a second path terminal is connected to the output terminal to output the present-stage gate driving signal Gn, and the first capacitor C1 is connected between the control terminal of the second switch transistor T2 and the second path terminal.
The first capacitor C1 is a parasitic capacitor between the control terminal of the second switch transistor T2 and the second path terminal. Of course, it will be understood by those skilled in the art that an independent storage capacitor may also be disposed between the control terminal of the second switch transistor T2 and the second path terminal, and in this case, the first capacitor C1 is the sum of the parasitic capacitor and the independent storage capacitor between the control terminal of the second switch transistor T2 and the second path terminal.
The second output module 130 includes a sixteenth switch T16, a control terminal of the sixteenth switch T16 is connected to the first node Q, a first path terminal is connected to the first clock signal input terminal to receive the clock signal CLK1, and a second path terminal is connected to the output terminal to output the present stage transmission signal Zn.
The first pull-down module 140 includes a third switch T3, a control terminal of the third switch T3 is connected to the second clock signal input terminal to receive the clock signal CLK3, a first path terminal is connected to the first node Q, and a second path terminal is connected to the low level signal input terminal to receive the low level signal VGL. It should be noted that the structure of the first pull-down module 330 is not limited to the above structure, and may be other structures combining a plurality of switch tubes, and those skilled in the art may select the structure according to the specific situation.
The second pull-down module 150 includes fourth and fifth switching tubes T4 and T5, control terminals of the fourth switching tube T4 and the fifth switching tube T5 are connected to the first node Q, first pass terminals of the fourth switching tube T4 and the fifth switching tube T5 are connected to the low level signal input terminal to receive the low level signal VGL, and second pass terminals of the fourth switching tube T4 and the fifth switching tube T5 and the stabilizing module 160 are connected to the second node QB1 and the third node QB 2. When the first node Q is at a high level, the fourth switch transistor T4 and the fifth switch transistor T5 are turned on, and a low level signal VGL is provided to the second node QB1 and the third node QB 2.
Specifically, the stabilization module 160 includes a first stabilization module 161 and a second stabilization module 162. The first stabilizing module 161 includes sixth to tenth switching tubes T6-T10. The control terminal of the sixth switch transistor T6 is shorted with the first path terminal to receive the clock signal CLK1, and the second path terminal is connected to the second node QB 1. The control end of the seventh switch tube T7 is connected to the first path end of the sixth switch tube T6, the first path end is connected to the low level signal input end, and the second path end is connected to the third node QB 2. The control end of the eighth switch tube T8 is connected with the second node QB1, the first path end is connected with the first node Q, and the second path end is connected with the low level signal input end. The control end of the ninth switch tube T9 is connected with the second node QB1, the first path end is connected with the current-stage gate drive signal output end, and the second path end is connected with the low-level signal input end. The control end of the tenth switching tube T10 is connected to the second node QB1, the first path end is connected to the present-stage transmission signal output end, and the second path end is connected to the low-level signal input end.
The second stabilizing module 162 includes eleventh to fifteenth switching tubes T11-T15. The control terminal of the eleventh switching tube T11 is shorted with the first path terminal to receive the clock signal CLK3, and the second path terminal is connected to the third node QB 2. A control end of the twelfth switch tube T12 is connected to a first path end of the eleventh switch tube T11, the first path end is connected to the low level signal input end, and the second path end is connected to the second node QB 1. A control end of the thirteenth switching tube T13 is connected to the third node QB2, a second path end is connected to the low level signal input end, and a first path end is connected to the first node Q. The control end of the fourteenth switching tube T14 is connected to the third node QB2, the second path end is connected to the low level signal input end, and the first path end is connected to the present stage gate driving signal output end. The control end of the fifteenth switch tube T15 is connected to the third node QB2, the second path end is connected to the low level signal input end, and the first path end is connected to the present stage transmission signal output end.
Fig. 4 shows a schematic block diagram of a 12-stage gate driving unit in the gate driving circuit of the embodiment of the present invention. The display device 200 includes a gate driving circuit and a plurality of pixel units arranged in an array on the display panel 210, each pixel unit including a pixel electrode and a transistor, such as a thin-film transistor (TFT), for turning on or off the pixel electrode. In the display panel 210, the gates of the transistors in the pixel units located in the same row (the "row" corresponds to, for example, the lateral direction shown in the drawing) are connected and one Gate line is drawn toward the edge area of the display panel 210, thereby forming Gate lines Gate1 to Gate12, as shown in fig. 3.
The Gate driving circuit according to an embodiment of the present invention is, for example, a Gate Driver in Array (GIA) 220, and includes a plurality of Gate driving units cascaded in sequence. The gate driving units are respectively connected to the gate lines on the display panel 210. The pixel units on the display panel 210 are selected by a row via the gate lines. Corresponding gray scale signals are provided in rows through the data lines to realize image display.
In a preferred embodiment, the gate driving circuit 220 of the embodiment of the invention is a double-sided structure, and the plurality of gate driving units include two groups of gate driving units, and the two groups of gate driving units are respectively arranged on the left and right sides of the display panel 210 in a cascade manner, and include a first portion 220a and a second portion 220 b. The first group of gate driving units is disposed in the first portion 220a, and the second group of gate driving units is disposed in the second portion 220 b. As shown in fig. 1, the first group of gate driving units Stage1 to Stage12 is located in the first portion 220a, and the second group of gate driving units Stage1 to Stage12 is located in the second portion 220 b.
In the preferred embodiment of the present invention, each Gate line is charged by two sets of Gate driving units respectively, as shown in fig. 4, the Gate line Gate1 is charged by the Gate driving unit Stage1 in the first portion 220a and the Gate driving unit Stage1 in the second portion 220b together, so that the driving capability of the Gate driving circuit can be further improved.
For the gate driving units of each Stage, the first clock signal input terminal and the second clock signal input terminal are respectively connected with a plurality of clock lines to receive two clock signals from the clock signals CLK1-CLK8, for example, the gate driving unit Stage1 of the first Stage receives the clock signal CLK1 and the clock signal CLK3, and the gate driving unit Stage2 of the second Stage receives the clock signal CLK5 and the clock signal CLK 7.
When the gate driving units are a first stage gate driving unit and a second stage gate driving unit, the previous stage signal input terminal of the gate driving unit is used for inputting the start signal STV 1.
When the gate driving unit is any one of the third-level to nth-level gate driving units, the preceding-stage signal input end of the gate driving unit is electrically connected to the present-stage signal output end of the i-2-level gate driving unit.
According to the gate driving circuit of the embodiment, a plurality of gate driving signals are generated using a plurality of gate driving units connected in cascade for being supplied to the gate lines to select the pixel units of the corresponding row. In the double-sided structure, the gate driving circuit includes a first portion and a second portion for driving the gate lines. The plurality of gate driving units only require 10 signal lines on a main path for transmitting the start signal STV1, the low level signal VGL, and the clock signals CLK1 to CLK8, respectively. Only a narrow wiring area is required on the interconnection path between the adjacent gate driving units for transmitting the preceding-stage signal Qi-2, respectively.
In contrast, in the related art gate driving circuit, if a similar two-sided structure is employed, the plurality of gate driving units respectively require 12 signal lines for transmitting the start signal STV1, the low level signal VGL, the clock signals CLK1 to CLK8, and the first and second stabilization signals V1 and V2 in the main path. A wide wiring area is required on the interconnection path between the adjacent gate driving units, and the wiring area is respectively used for transmitting the present-stage signal Qi-4 of the gate driving unit of the previous four stages.
Compared with the gate drive circuit in the prior art, the gate drive circuit in the embodiment of the invention reduces the number of signal lines required by each stage of gate drive circuit, thereby reducing the corresponding wiring area and signal line load, and realizing a narrow-frame and low-power-consumption display device.
It should be noted that although the gate driving circuit employing the double-sided structure is described in this embodiment, the present invention is not limited thereto. When the gate driving circuit is applied to a gate driving circuit with a single-side structure, the gate driving circuit can also reduce the wiring area on an interconnection path between adjacent gate driving units, reduce the number of signal lines and obtain the beneficial effect of reducing the wiring area.
Fig. 5 illustrates a timing diagram of clock signals and enable signals of the gate driving circuit of fig. 3.
As shown in FIG. 5, the clock signals CLK1-CLK8 are square wave signals with a clock period of 8T and a duty cycle of 1/4, and the start signal STV1 is a single pulse signal with a high level duration of 4T. T is a predetermined clock period, such as the minimum clock period of the system clock signal or an integer multiple thereof.
Referring to fig. 4, the first and second portions of the gate driving circuit each include signal lines for transmitting the start signal STV1 and the clock signals CLK1 to CLK8 on a main path. The clock signals CLK1-CLK4 start at the falling edge of the start signal STV1, with a phase delay of 2T. The clock signals CLK5-CLK8 are sequentially delayed by 1T in phase compared to the clock signals STV1-STV4, and the clock signals CLK5-CLK8 are sequentially delayed by 2T in phase.
Fig. 6 shows an operation waveform diagram of the gate driving unit according to the first embodiment of the present invention, with the abscissa representing time(s) and the ordinate representing signal level (V). The operation principle of the gate driving unit according to the first embodiment of the present invention will be described in detail below with reference to fig. 3 and 6, taking the first Stage gate driving unit Stage1 as an example.
As described above, the previous Stage signal input terminal of the first Stage gate driving unit Stage1 is used for receiving the start signal STV1, and the first clock signal input terminal, the second clock signal input terminal, and the low level signal input terminal respectively receive the clock signals CLK1, CLK3, and the low level signal VGL.
In the first phase, when the start signal STV1 changes from low level to high level, the first switch tube T1 is turned on, the first switch tube T1 provides the start signal STV1 to the first node Q, the first node Q is precharged, the potential of the first node Q changes from low level to high level, the fourth switch tube T4 and the fifth switch tube T5 are turned on, the fourth switch tube T4 and the fifth switch tube T5 provide the low level signal VGL to the second node QB1 and the third node QB2 respectively, the potentials of the second node QB1 and the third node QB2 are pulled down to low level, and the eighth to tenth switch tubes T8-T10 and the thirteenth to fifteenth switch tubes T13-T15 are turned off.
In the second phase, when the clock signal CLK1 is raised from a low level to a high level, the potential of the first node Q continues to rise due to the bootstrap effect of the first capacitor C1, and since the second switch transistor T2 and the sixteenth switch transistor T16 are already turned on in the first phase, the second switch transistor T2 and the sixteenth switch transistor T16 are fully turned on in the second node, and the present-stage gate driving signal Gn and the present-stage transfer signal Zn are output through the second switch transistor T2 and the sixteenth switch transistor T16.
It should be noted that, in the present invention, a parasitic capacitor between the control terminal of the second switch transistor T2 and the second path terminal may be directly used as the first capacitor C1, or an independent storage capacitor may be further disposed between the control terminal of the second switch transistor T2 and the second path terminal in order to enhance the pull-up effect. The independent storage capacitor and the parasitic capacitor of the second switch tube T2 are connected in parallel to form a cylinder as the first capacitor C1, i.e., the first capacitor C1 is equal to the sum of the parasitic capacitor between the control terminal and the second path terminal of the second switch tube T2 and the independent storage capacitor.
In the third phase, when the clock signal CLK1 goes low, the output waveform is pulled low to a low level through the second switch transistor T2 and the sixteenth switch transistor T16, and the potential of the first node Q is pulled low through the coupling effect of the first capacitor C1.
In the fourth stage, when the clock signal CLK3 changes from low level to high level, the third transistor T3 is turned on, and the third transistor T3 provides the low level signal VGL to the first node Q, pulling down the potential of the first node Q to low level. Meanwhile, when the clock signal CLK1 and the clock signal CLK3 are alternately changed from a low level to a high level, the second node QB1 and the third node QB2 are alternately at a high level, and the first stabilizing block 161 and the second stabilizing block 162 are alternately turned on, so that the potentials of the first node Q, the present-stage gate driving signal output terminal, and the present-stage transfer signal output terminal are stabilized at a low level. Specifically, when the clock signal CLK1 is at a high level, the sixth switch transistor T6 and the seventh switch transistor T7 are turned on, the second node QB1 is at a high level, and the eighth to tenth switch transistors T8 to T10 are turned on, so as to respectively provide the low level signal VGL to the first node Q, the present-stage gate driving signal output terminal, and the present-stage transmission signal output terminal. When the clock signal CLK3 is at a high level, the eleventh switch transistor T11 and the twelfth switch transistor T12 are turned on, the third node QB2 is at a high level, and the thirteenth to fifteenth switch transistors T13-T15 are turned on, so as to respectively provide the low level signal VGL to the first node Q, the present stage gate driving signal output terminal and the present stage transfer signal output terminal.
Fig. 7 shows waveforms of gate driving signals of a plurality of gate driving units according to the first embodiment of the present invention, with the abscissa representing time(s) and the ordinate representing signal level (V).
Compared with the gate driving circuit in the prior art, the gate driving circuit reduces the number of signal lines required by each stage of gate driving circuit, and is beneficial to reducing power consumption. In addition, as shown by the curves g1 and g2, when the gate driving circuit charges the pixel, only one period of overlap with the output waveform of the next stage of gate driving unit is provided, which is beneficial to solving the cross striation phenomenon.
Fig. 8 shows a circuit schematic diagram of a gate driving unit according to a second embodiment of the present invention. As shown in fig. 8, in the second embodiment of the present invention, the control terminal and the first path terminal of the sixth switching tube T6 in the control module 360 are shorted to receive the first stabilizing signal V1, and the control terminal and the first path terminal of the eleventh switching tube T11 are shorted to receive the second stabilizing signal V2.
In addition, the structure and connection relationship of the input module 310, the first output module 320, the second output module 330, the first pull-down module 340 and the second pull-down module 350 in this embodiment are the same as those in the first embodiment shown in fig. 3, and are not repeated herein.
Fig. 9 shows a circuit schematic diagram of a gate driving unit according to a third embodiment of the present invention. As shown in fig. 9, in the present embodiment, the control terminal of the third switching transistor T3 in the first pull-down module 440 receives the lower-stage transmission signal Zn +2, and compared with the gate driving unit provided in the second embodiment, the gate driving unit of the present embodiment can further reduce the number of signal lines, so as to reduce the corresponding wiring area and signal line load, thereby implementing a narrow-frame, low-power display device.
In addition, the structures and connection relationships of the input module 410, the first output module 420, the second output module 430, the second pull-down module 450, and the stabilization module 460 in this embodiment are the same as those in the second embodiment shown in fig. 8.
Fig. 10 shows a circuit schematic diagram of a gate driving unit according to a fourth embodiment of the present invention. In a preferred embodiment of the present invention, a gate driving unit for bidirectional scanning is provided, and in particular, the input module 510 includes a first switch T1 and a seventeenth switch T17, a control terminal of the first switch T1 receives a preceding stage transfer signal Zn-2, a first path terminal receives a preceding stage gate driving signal Gn-2, and a second path terminal is connected to the first node Q. A control terminal of the seventeenth switching tube T17 receives the lower stage transmission signal Zn +2, a first path terminal receives the lower stage gate driving signal Gn +2, and a second path terminal is connected to the first node Q.
It should be noted that, for the n-1 st and nth stage gate driving units, the control terminal and the first path terminal of the seventeenth switching tube T17 are shorted to receive the externally provided start signal STV 2.
Fig. 11 shows a circuit schematic diagram of a gate driving unit according to a fifth embodiment of the present invention. Compared with the gate driving unit shown in fig. 10, the fifth embodiment of the present invention provides the gate driving unit in which the control terminal and the first path terminal of the sixth switching transistor T6 in the control module 660 are shorted to receive the first stabilizing signal V1, and the control terminal and the first path terminal of the eleventh switching transistor T11 are shorted to receive the second stabilizing signal V2.
In addition, the structures and connection relationships of the input module 610, the first output module 620, the second output module 630, the first pull-down module 640, and the second pull-down module 650 of the present embodiment are the same as those of the fourth embodiment shown in fig. 10, and are not repeated herein.
The first to seventeenth switching tubes T1-T17 may be implemented by using switching elements such as amorphous silicon TFTs, oxide TFTs, or low temperature polysilicon N-TFTs. For example, in the embodiment of the present invention, the first to seventeenth switching tubes T1-T17 are all N-type thin film transistors, and the first path terminal and the second path terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged), but the implementation of the present invention is not limited thereto.
In summary, the embodiments of the invention provide a gate driving circuit and a display device. When one of the grid driving units is used for pixel charging, only the pixels separated from the grid driving unit by one level are pre-charged, the number of the grid lines which are simultaneously opened is reduced, the overlapping period of output waveforms of the adjacent grid driving units is reduced, the phenomenon of cross striation during display can be avoided, and the display quality of the display device is improved.
The grid driving unit provided by the invention only needs two clock signals and one externally provided starting signal, thereby reducing the number of signal lines and the load of the signal lines, reducing the required wiring area, being beneficial to the design of a narrow frame and simultaneously being beneficial to reducing the power consumption of a circuit.
In a preferred embodiment, the gate driving unit provided by the invention only needs two clock signals and one externally provided starting signal, thereby reducing the number of signal lines and the load of the signal lines, reducing the required wiring area, being beneficial to the design of a narrow frame and being beneficial to reducing the power consumption of a circuit. In a preferred embodiment, the transfer signal and the gate driving signal of each gate driving unit are output through different terminals, so that the influence of signal transfer on gate driving is reduced, and the output capability of the gate driving unit is strong.
In a preferred embodiment, a gate driving circuit capable of bidirectional scanning is provided, which has two modes of forward scanning and reverse scanning, increases the degree of freedom of the display panel, and provides an elastic driving method for the liquid crystal display panel.
In a preferred embodiment, the first stabilizing module and the second stabilizing module are opened alternately, so that the stability is good. Also, power consumption of a display device employing the gate driving unit can be effectively reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (13)
1. A gate driving circuit comprising a plurality of gate driving units connected in cascade, wherein each of the plurality of gate driving units comprises:
the input module is connected with the first node and charges the first node according to the first starting signal and the second starting signal;
the first output module is connected with the input module and the first node, generates a current-stage grid driving signal according to a first clock signal, and provides the current-stage grid driving signal at an output end;
the second output module is connected with the input module and the first node and generates a current-stage transmission signal according to the first clock signal;
the first pull-down module is connected with the first node and pulls down the first node to a low-level signal under the control of a second clock signal;
the stabilizing module is connected with the first node and the output end, and maintains the current-stage grid signal at the low-level signal under the control of the first clock signal and the second clock signal; and
a second pull-down module connected to the first node and the stabilization module, for providing a low level signal to the stabilization module according to a control voltage of the first node,
wherein the plurality of gate driving units include a start-stage gate driving unit cascaded at a first stage and a second stage and a plurality of first intermediate-stage gate driving units outside the start-stage gate driving unit,
the first start signal and the second start signal of each initial stage gate driving unit are first external start signals provided outside the gate driving circuit;
the first start signal of each first intermediate stage gate driving unit is the current stage gate driving signal provided by the previous stage gate driving unit one stage apart, the second start signal is the current stage transfer signal provided by the previous stage gate driving unit one stage apart,
wherein the duty cycle of the first clock signal and the second clock signal is 1/4, and the phase of the second clock signal is delayed 1/2 clock cycles relative to the first clock signal.
2. The gate driving circuit of claim 1, wherein the input module further receives a third enable signal and a fourth enable signal, and the first node is charged and discharged according to the third enable signal and the fourth enable signal.
3. The gate driving circuit according to claim 2, wherein the plurality of gate driving units includes a termination stage gate driving unit cascaded in a last stage and a penultimate stage and a plurality of second intermediate stage gate driving units outside the termination stage gate driving unit,
the third start signal and the fourth start signal of each termination stage gate driving unit are respectively a second external start signal provided outside the gate driving circuit;
the third start signal of each second intermediate-stage gate driving unit is the current-stage gate driving signal provided by the next-stage gate driving unit separated by one stage, and the fourth start signal is the current-stage transfer signal provided by the next-stage gate driving unit separated by one stage.
4. A gate drive circuit as claimed in claim 1, wherein the stabilization module comprises:
a first stabilizing module, configured to maintain the current-stage gate signal at the low-level signal according to the first clock signal;
a second stabilizing module for maintaining the present-stage gate signal at the low-level signal according to the second clock signal,
when the grid driving unit works, the first stabilizing module and the second stabilizing module are alternately started.
5. A gate drive circuit as claimed in claim 1, wherein the input module comprises:
and the control end of the first switch tube receives the second starting signal, the first access end receives the first starting signal, and the second access end is connected with the first node.
6. The gate driving circuit of claim 1, wherein the first output module comprises:
a control end of the second switch tube is connected with the first node, a first path end is used for receiving the first clock signal, and a second path end is used for generating a current-stage grid driving signal;
and the first capacitor is connected between the control end of the second switch tube and the second path end.
7. The gate driving circuit of claim 1, wherein the second output module comprises:
and a control end of the sixteenth switching tube is connected with the first node, a first path end is used for receiving the first clock signal, and a second path end is used for generating the current-stage transmission signal.
8. The gate driving circuit of claim 1, wherein the first pull-down module comprises:
and a control end of the third switching tube is used for receiving the second clock signal, a first path end is connected with the first node, and a second path end is used for receiving the low-level signal.
9. The gate driving circuit of claim 1, wherein the second pull-down module comprises:
a control end of the fourth switching tube is connected to the first node, a first path end is used for receiving the low level signal, and a second path end and the stabilizing module are connected to a second node;
and the control end of the fifth switching tube is connected to the first node, the first path end is used for receiving the low-level signal, and the second path end and the stabilizing module are connected to the third node.
10. The gate driving circuit of claim 4, wherein the first stabilization module comprises:
the control end of the sixth switching tube is in short circuit with the first path end to receive the first clock signal, and the second path end is connected to the second node;
the control end of the eighth switching tube is connected to the second node, the first path end is connected with the first node, and the second path end is used for receiving the low-level signal;
a ninth switching tube, a control end of which is connected to the second node, a first path end of which is connected with the output end of the current-stage gate driving signal, and a second path end of which is used for receiving the low-level signal;
and the control end of the tenth switching tube is connected to the second node, the first path end is connected with the current-stage transmission signal output end, and the second path end is used for receiving the low-level signal.
11. The gate driving circuit of claim 10, wherein the second stabilization module comprises:
the control end of the eleventh switch tube is in short circuit with the first path end to receive the second clock signal, and the second path end is connected to the third node;
a thirteenth switching tube, wherein a control end is connected to the third node, a first path end is connected to the first node, and a second path end is used for receiving the low level signal;
a fourteenth switching tube, a control end of which is connected to the third node, a first path end of which is connected to the output end of the current-stage gate driving signal, and a second path end of which is used for receiving the low-level signal;
and the control end of the fifteenth switching tube is connected to the third node, the first path end is connected with the current-stage transmission signal output end, and the second path end is used for receiving the low-level signal.
12. A gate drive circuit as claimed in claim 11, wherein the stabilization module further comprises:
a seventh switch tube, a control end receives the first clock signal, a first path end is used for receiving the low level signal, and a second path end is connected to the third node;
a twelfth switching tube, wherein the control end receives the second clock signal, the first path end is used for receiving the low level signal, and the second path end is connected to the second node;
wherein when the first clock signal is asserted, the seventh switch is turned on to provide the low level signal to the third node,
when the second clock signal is valid, the twelfth switching tube is turned on, and the low level signal is provided to the second node.
13. A display device, comprising:
a gate drive circuit as claimed in any one of claims 1 to 12, for providing a plurality of gate drive signals;
a data driving circuit for providing a plurality of gray scale data; and
a display panel including a plurality of pixel units arranged in an array, and a plurality of gate lines and a plurality of data lines,
the display panel receives the gate driving signals through the gate lines to select the pixel units according to rows, and receives the gray scale data through the data lines to provide the gray scale data for the selected pixel units to realize image display.
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| CN111354309A (en) * | 2020-04-15 | 2020-06-30 | 京东方科技集团股份有限公司 | Display driving module, display driving method and display device |
| CN112908235B (en) * | 2021-01-26 | 2022-09-23 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN112908276B (en) * | 2021-01-26 | 2022-09-23 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN113628596B (en) * | 2021-07-23 | 2023-02-24 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN113741726B (en) | 2021-07-30 | 2022-06-03 | 惠科股份有限公司 | Drive circuit, four-stage drive circuit and display panel |
| US20250279027A1 (en) * | 2022-06-29 | 2025-09-04 | Wuhan Boe Optoelectronics Technology Co.,Ltd. | Display driving circuit and display device |
| CN119993001B (en) * | 2023-11-09 | 2025-09-19 | 武汉华星光电半导体显示技术有限公司 | Gate driving unit and display panel |
| CN117456924B (en) * | 2023-12-25 | 2024-04-19 | 惠科股份有限公司 | Driving circuit and display device |
| CN119274509A (en) * | 2024-11-21 | 2025-01-07 | 昆山龙腾光电股份有限公司 | A gate transfer circuit and a display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
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