CN109343986B - Method and computer system for handling memory failures - Google Patents

Abstract

The present application provides a method for handling a memory failure, comprising: a first control unit determining an address of a memory with a fault in a first storage space, and the first storage space can store the second control unit in a direct memory access DMA manner in the first storage space. Data backed up in a control unit; the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit; the second control unit obtains the address of the faulty memory in the first storage space; the second control unit The control unit stores the cached data in the first storage space by means of DMA, and isolates the faulty memory in the first storage space when storing the data, wherein the data is sent by the processing unit through the second control unit data to be stored. This method can reduce the probability of OOM caused by memory failure during mirror access.

Description

Method and computer system for handling memory failures

technical field

The present application relates to the field of information technology, and more particularly, to methods and computer systems for handling memory failures.

Background technique

The existence of an exact copy of the data on one disk on another disk is called mirroring. Mirroring is a type of redundancy. On a storage control device, mirroring means that one controller copies the received data on another controller through the mirroring channel.

When mirroring is accessed through direct memory access (DMA), the data in one controller is directly copied from the physical address space of the controller to another controller due to the direct access to the physical address space of the memory. Exactly the same address space.

If the memory of another controller is faulty, it will cause an out of memory (OOM) when data is written to the faulty memory in that controller.

SUMMARY OF THE INVENTION

The present application provides a method for handling memory failures, which can reduce the probability of OOM occurring due to memory failures during mirror access.

In a first aspect, a method for handling memory failures is provided, which is applied to a computer system. The computer system includes a processing unit, a first control unit, and a second control unit. Both the first control unit and the second control unit are connected to The processing unit connection includes: the first control unit determines the address of the faulty memory in the first storage space, the first storage space is the storage space in the first control unit, and the first storage space can store the The second control unit accesses data backed up in the first control unit by direct memory access DMA; the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit; the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit; The second control unit obtains the address of the faulty memory in the first storage space; the second control unit stores the data buffered in the second control unit in the first storage space by means of DMA, and stores the data in the first storage space. A faulty memory in the first storage space is isolated when data is stored, wherein the data is stored by the processing unit through the second control unit.

Optionally, the second control unit stores the data buffered in the second control unit to the first storage space by DMA, and isolates the faulty memory in the first storage space when storing the data , including: the second control unit sends a second write data command to the second DMAC in the second control unit, where the second write data command is used to instruct the second DMAC to buffer the data stored in the second control unit The data is stored in the first storage space, and the storage space indicated by the destination address carried by the second write data instruction is the storage space other than the faulty memory in the first storage space.

By causing the local controller (for example, the first control unit) to perform fault detection on the storage space supporting DMA before or after the OS is started, and notify the controller (for example, the first control unit) of the address of the faulty memory in the storage space to the controller (for example, the first control unit). Two control units), when the data backup is performed in the storage space for the control, the faulty memory in the storage space is isolated, that is, data backup is only performed in the storage space where no memory failure occurs in the control, thereby Reduce the probability of OOM occurrence.

With reference to the first aspect, in some implementations of the first aspect, before the second control unit stores the data buffered in the second control unit to the first storage space in a DMA manner, the method further Including: the second control unit migrates the data cached in the address space corresponding to the address of the faulty memory in the first storage space to other storage spaces in the second storage space; wherein, the second storage space is storage space in the second control unit.

Before the second control unit stores the data buffered in the second control unit in the first storage space by means of DMA, by causing the second control unit to buffer the data in the address corresponding to the address of the faulty memory in the first storage space The data in the address space is migrated to other storage spaces in the second storage space, so that the second control unit can isolate the faulty memory in the first storage space when storing the data in the first storage space, This in turn reduces the probability of OOM occurring.

With reference to the first aspect, in some implementations of the first aspect, the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit, including: the first control unit counts The number of addresses of the faulty memory in the first storage space; if the number is less than or equal to a preset threshold, the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit unit.

Before synchronizing the address of the faulty memory in the first storage space to the control, by counting the number of addresses of the faulty memory in the first storage space, when the number is less than the preset threshold, the first The address of the faulty memory in one storage space is synchronized to the other control, otherwise the storage space for DMA will be re-allocated in this control to avoid that when the fault in the first storage space is serious, there will still be faults. The waste of resources caused by the synchronization of the memory address to the control.

With reference to the first aspect, in some implementations of the first aspect, the first control unit includes a first processor and a first motherboard management controller BMC, the second control unit includes a second BMC, and the first control unit includes a second BMC. Synchronizing the address of the faulty memory in the storage space to the second control unit includes: the first processor writing the address of the faulty memory in the first storage space into a pre-allocated storage space in the first control unit in; the first BMC obtains the address of the faulty memory in the first storage space from the storage space pre-allocated in the first control unit; the first BMC sends the first message to the second BMC, the first A message carries the address of the faulty memory in the first storage space.

With reference to the first aspect, in some implementations of the first aspect, the first control unit further includes a first platform control unit PCH and a first complex programmable logic device CPLD, and a pre-allocated storage space in the first control unit is the storage space in the first CPLD, and the first processor writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the first control unit, including: the first processor The address of the faulty memory in the first storage space is written into the pre-allocated storage space in the first CPLD through the first PCH; the first BMC is loaded from the pre-allocated storage space in the first control unit Acquiring the address of the faulty memory in the first storage space includes: the first BMC acquiring the address of the faulty memory in the first storage space from the pre-allocated storage space in the first CPLD.

With reference to the first aspect, in some implementations of the first aspect, the first control unit includes a first processor and a first direct memory access controller DMAC, the second control unit includes a second processor, and the Synchronizing the address of the faulty memory in the first storage space to the second control unit includes: the first processor sending a first write data command to the first DMAC, where the first write data command carries the first data write command. The address of the faulty memory in the storage space is the storage address in the first storage subspace in the second storage space, where the second storage space is the storage space in the second control unit, and the first storage subspace is used for Store the address of the faulty memory in the first storage space, the second storage space further includes a second storage subspace, and the second storage subspace is used to store the first control unit in the second control unit in a DMA manner. The data backed up in the unit; the first DMAC stores the address of the faulty memory in the first storage space to the storage space corresponding to the storage address in the first storage subspace according to the first write data instruction; the The first processor sends a second message to the second processor, where the second message carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace.

By synchronizing the address of the faulty memory in the first storage space to the peer controller through DMA, the speed of fault synchronization is improved, so that the peer controller can find the address of the faulty memory in the local controller in time. When data access is performed in the space, the faulty memory can be isolated in a timely manner, so as to avoid data access to the faulty storage space in the local control due to untimely synchronization of the fault, which may lead to OOM.

With reference to the first aspect, in some implementations of the first aspect, the second control unit includes a second processor and a second BMC, and the second control unit obtains the address of the faulty memory in the first storage space, Including: the second BMC receives the first message sent by the first BMC, and the first message carries the address of the faulty memory in the first storage space; the second BMC responds to the first message Perform analysis to obtain the address of the faulty memory in the first storage space; the second BMC writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the second control unit; the The second processor acquires the address of the faulty memory in the first storage space from the storage space pre-allocated in the second control unit.

With reference to the first aspect, in some implementations of the first aspect, the second control unit further includes a second PCH and a second CPLD, and the pre-allocated storage space in the second control unit is the storage space in the second CPLD space, the second BMC writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the second control unit, including: the second BMC writes the faulty memory in the first storage space The address of the memory is written into the pre-allocated storage space in the second CPLD; the second processor obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the second CPLD, The method includes: the second processor obtains, through the second PCH, the address of the faulty memory in the first storage space from the pre-allocated storage space in the second CPLD.

With reference to the first aspect, in some implementations of the first aspect, the second control unit includes a second processor, and the second control unit acquires the address of the faulty memory in the first storage space, including: the first The second processor receives the second message sent by the first processor, and the second message carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace; the The second processor acquires, according to the second message, the address of the faulty memory in the first storage space from the storage space corresponding to the storage address in the first storage subspace.

With reference to the first aspect, in some implementations of the first aspect, the first control unit determines the address of the faulty memory in the first storage space, including: the first processor performs an available operation on the first storage space. Correct error ECC detection; the first processor determines the address of the faulty memory in the first storage space according to the detection result of the ECC detection on the first storage space.

With reference to the first aspect, in some implementations of the first aspect, the address of the faulty memory in the first storage space includes the first address of the page frame where the faulty memory in the first storage space is located.

With reference to the first aspect, in some implementations of the first aspect, the computer system further includes a storage unit, the first control unit and the second control unit are both connected to the storage unit, and the method further includes: the processing unit passes the The second control unit stores the data to the storage unit.

In a second aspect, a device for handling a memory failure is provided, which is configured in a computer system, the computer system further includes a processing unit, the device is connected to the processing unit, the device includes a first control unit and a second control unit, the first The control unit is configured to execute the operation steps of the method performed by the first control unit in the first aspect or any possible implementation manner of the first aspect, and the second control unit is configured to execute the first aspect or any of the first aspect. Operation steps of the method performed by the second control unit in a possible implementation.

In a third aspect, a computer system is provided, the computer system includes a processing unit and a storage control unit, the storage control unit is connected to the processing unit, and the storage control unit includes: a first control unit for determining a faulty device in the first storage space The address of the memory, the first storage space is the storage space in the first control unit, and the first storage space can store the data backed up by the second control unit in the first control unit by means of direct memory access DMA; a control unit, which is also used for synchronizing the address of the faulty memory in the first storage space to the second control unit; the second control unit is used for acquiring the address of the faulty memory in the first storage space; The second control unit is further configured to store the data buffered in the second control unit in the first storage space by means of DMA, and isolate the faulty memory in the first storage space when storing the data, wherein , the data is stored by the processing unit through the second control unit.

In the computer system provided by the present application, the local control (for example, the first control unit) performs fault detection on the storage space that supports DMA before or after the OS is started, and notifies the address of the faulty memory in the storage space. For the control (for example, the second control unit), when the control performs data backup in the storage space, isolate the faulty memory in the storage space, that is, only the storage without memory failure in this control Data backup is performed in the space, thereby reducing the probability of OOM.

With reference to the third aspect, in some implementations of the third aspect, the second control unit is further configured to store the data buffered in the second control unit in the first storage space in a DMA manner, Migrate the data cached in the address space corresponding to the address of the faulty memory in the first storage space to other storage spaces in the second storage space; wherein, the second storage space is in the second control unit. storage.

Before the second control unit stores the data buffered in the second control unit in the first storage space by means of DMA, by causing the second control unit to buffer the data in the address corresponding to the address of the faulty memory in the first storage space The data in the address space is migrated to other storage spaces in the second storage space, so that the second control unit can isolate the faulty memory in the first storage space when storing the data in the first storage space, and further Reduce the probability of OOM occurrence.

With reference to the third aspect, in some implementations of the third aspect, the first control unit is further configured to count the number of addresses of the faulty memory in the first storage space; if the number is less than or equal to a preset threshold , synchronizing the address of the faulty memory in the first storage space to the second control unit.

Before synchronizing the address of the faulty memory in the first storage space to the control, by counting the number of addresses of the faulty memory in the first storage space, when the number is less than the preset threshold, the first The address of the faulty memory in one storage space is synchronized to the other control, otherwise the storage space for DMA will be re-allocated in this control to avoid that when the fault in the first storage space is serious, there will still be faults. The waste of resources caused by the synchronization of the memory address to the control.

With reference to the third aspect, in some implementations of the third aspect, the first control unit includes a first processor and a first motherboard management controller BMC, the second control unit includes a second BMC, the first processor, and the Write the address of the faulty memory in the first storage space into the storage space pre-allocated in the first control unit; the first BMC is used to obtain the storage space from the pre-allocated storage space in the first control unit The address of the faulty memory in the first storage space; the first BMC is also used to send a first message to the second BMC, where the first message carries the address of the faulty memory in the first storage space .

With reference to the third aspect, in some implementations of the third aspect, the first control unit further includes a first platform control unit PCH and a first complex programmable logic device CPLD, and a pre-allocated storage space in the first control unit is the storage space in the first CPLD, and the first processor is also used to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the first CPLD through the first PCH ; The first BMC is also used to obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the first control unit, including: the first BMC is also used to obtain the address of the faulty memory in the first storage space from the first CPLD. The address of the faulty memory in the first storage space is obtained from the pre-allocated storage space.

With reference to the third aspect, in some implementations of the third aspect, the first control unit includes a first processor and a first direct memory access controller DMAC, the second control unit includes a second processor, and the first process The device is also used to send a first write data command to the first DMAC, where the first write data command carries the address of the faulty memory in the first storage space in the first storage subspace in the second storage space The storage address in the second storage space is the storage space in the second control unit, the first storage subspace is used to store the address of the faulty memory in the first storage space, and the second storage space also includes The second storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA; the first DMAC is used to store the data backed up in the second control unit according to the first write data instruction. The address of the faulty memory in the first storage space is stored in the storage space corresponding to the storage address in the first storage subspace; the first processor is further configured to send a second message to the second processor, The second message carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace.

By synchronizing the address of the faulty memory in the first storage space to the peer controller through DMA, the speed of fault synchronization is improved, so that the peer controller can find the address of the faulty memory in the local controller in time. When data access is performed in the space, the faulty memory can be isolated in a timely manner, so as to avoid data access to the faulty storage space in the local control due to untimely synchronization of the fault, which may lead to OOM.

With reference to the third aspect, in some implementations of the third aspect, the second control unit includes a second processor and a second BMC, and the second BMC is configured to receive the first message sent by the first BMC, the The first message carries the address of the faulty memory in the first storage space; the second BMC is also used to parse the first packet to obtain the address of the faulty memory in the first storage space; The second BMC is further configured to write the address of the faulty memory in the first storage space into the storage space pre-allocated in the second control unit; the second processor is configured to pre-register from the second control unit The address of the faulty memory in the first storage space is obtained from the allocated storage space.

In conjunction with the third aspect, in some implementations of the third aspect, the second control unit further includes a second PCH and a second CPLD, and the pre-allocated storage space in the second control unit is the storage space in the second CPLD, The second BMC is further configured to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the second CPLD; the second processor is further configured to obtain the The address of the faulty memory in the first storage space is obtained from the pre-allocated storage space in the second CPLD.

With reference to the third aspect, in some implementations of the third aspect, the second control unit includes a second processor, and the second processor is further configured to receive the second message sent by the first processor, the first The second message carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace; the second processor is further configured to, according to the second message, retrieve the address from the storage address in the first storage subspace. The corresponding storage space in the first storage subspace acquires the address of the faulty memory in the first storage space.

With reference to the third aspect, in some implementations of the third aspect, the address of the faulty memory in the first storage space includes the first address of the page frame where the faulty memory in the first storage space is located.

With reference to the third aspect, in some implementations of the third aspect, the first processor is further configured to perform correctable error ECC detection on the first storage space; according to a detection result of performing ECC detection on the first storage space , and determine the address of the faulty memory in the first storage space.

With reference to the third aspect, in some implementations of the third aspect, the second control unit is further configured to send a second write data command to the second DMAC in the second control unit, where the second write data command is used for Instruct the second DMAC to store the data buffered in the second control unit into the first storage space, and the storage space indicated by the destination address carried by the second write data instruction is faulty in the first storage space storage space outside of memory.

With reference to the third aspect, in some implementations of the third aspect, the computer system further includes a storage unit, both the first control unit and the second control unit are connected to the storage unit, the processing unit is further configured to pass the second control unit This data is stored in the storage unit.

It should be noted that, in this computer system, the processing unit, the storage control unit and the storage unit may be implemented by the same computing device; or, the processing unit, the storage control unit and the storage unit may be implemented by three independent devices, for example , the processing unit can be implemented by an independent server, the storage control unit can be implemented by an independent storage control device, the storage unit can be implemented by an independent storage device, and the server, the storage control device and the storage device can be connected through a network. Alternatively, the processing unit and the storage control unit may be implemented by an independent computing device, and the storage unit may be implemented by another independent computing device. Alternatively, the storage control unit and the storage unit may be implemented by an independent computing device, and the processing unit may be implemented by another independent computing device.

In a fourth aspect, a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium, and when the instructions are executed on a computer, the computer can execute the first aspect or any possible implementation manner of the first aspect. method in .

In a fifth aspect, there is provided a computer program product comprising instructions that, when run on a computer, cause the computer to perform the method of the first aspect or any possible implementation of the first aspect.

Description of drawings

FIG. 1 is a schematic block diagram of a computer system provided by the present application.

FIG. 2 is another schematic block diagram of the computer system provided by the present application.

FIG. 3 is another schematic block diagram of the computer system provided by the present application.

FIG. 4 is a schematic flowchart of a DMA transmission process provided by the present application.

FIG. 5 is a schematic interactive flowchart of the method for handling a memory fault provided by the present application.

FIG. 6 is a schematic diagram of the flow of the address of the faulty memory in the computer system when the addresses of the faulty memory are synchronized according to the present application.

FIG. 7 is another schematic block diagram of the computer system provided by the present application.

Detailed ways

The technical solutions in the present application will be described below with reference to the accompanying drawings.

First, the computer system 100 will be introduced with reference to FIG. 1 .

As shown in FIG. 1 , the computer system 100 includes a processing unit 101 , a storage control unit 102 and a storage unit 103 .

The storage control unit 102 is equipped with a first control unit 1021 and a second control unit 1022, the first control unit is equipped with a central processing unit (CPU) 10211 and a memory 10212, and the second control unit is equipped with a CPU 10221 and a memory 10212. Memory 10222.

The memory 10212 and the memory 10222 may be the third-generation double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM).

The communication between the first control unit 1021 and the processing unit 101 is through the front-end interface 10213 (for example, the interface between the processor 10211 and the processing unit 101), and the communication between the second control unit 1022 and the processing unit 101 is through the front-end port 10223 (for example, The interface between the processor 10221 and the processing unit 101) communicates with the first control unit 1021 and the second storage control unit 1022 through the mirror interface 10214 and the mirror interface 10224, and between the first control unit 1021 and the storage unit 103 through the mirror interface 10214. The back-end interface 10215 (for example, the interface between the processor 10211 and the storage unit 103 ) communicates with the second control unit 1022 and the storage unit 103 through the back-end interface 10225 (for example, the interface between the processor 10221 and the storage device 103 ) ) communication.

As an example and not a limitation, in the computer system 100, the processing unit 101, the storage control unit 102 and the storage unit 103 may be implemented by the same computing device; or, the processing unit 101, the storage control unit 102 and the storage unit 103 may be implemented by independent For example, the processing unit 101 can be implemented by an independent server, the storage control unit 102 can be implemented by an independent storage control device, the storage unit 103 can be implemented by an independent storage device, the server, the storage control device and the storage device. can be connected through a network; alternatively, the processing unit 101 and the storage control unit 102 can be implemented by an independent computing device, and the storage unit 103 can be implemented by another independent computing device; or, the storage control unit 102 and the storage unit 103 can be implemented by Implemented by an independent computing device, the processing unit 101 may be implemented by another independent computing device.

The processing unit 101 may be a processor or a computer device including a processor in specific implementation, and the storage unit 103 may be a solid state drive (solid state drives, SSD) or a storage device including SSD in specific implementation.

Hereinafter, the general method of image storage will be introduced by taking the example that the processing unit 101 is located in the server, the storage control unit 102 is located in the storage control device, and the storage unit 103 is located in the storage device.

When the processing unit 101 is located in the server, the storage control unit 102 is located in the storage control device, and the storage unit 103 is located in the storage device, the corresponding schematic block diagram of the computer system 100 is shown in FIG. 2 .

The processor 10211 in the first control unit 1021 stores the data received from the processing unit 101 in the memory 10212, and then stores the data in the memory 10222 through the processor 10221 in the second control unit 1022, wherein the data is stored in the memory 10222. Memory 10212 is in exactly the same address space as memory 10222. That is, the data is backed up in the second control unit.

The reason why the data is stored in two identical address spaces is to ensure that if the data stored in one of the control units is lost due to the failure of the control unit, an identical copy of the data can be saved in the other control unit. data.

Finally, the processor 10211 saves the data cached in the memory 10212 to the storage unit 103;

Direct memory access (DMA) is described below.

DMA is a hardware mechanism that allows the direct transfer of their input/output (I/O) data between peripheral devices and main memory without the involvement of the processor. Throughput of device communication.

For example, when using the DMA mechanism for data access, a direct memory access controller (DMAC) 10216 and a DMAC 10226 need to be added to the first control unit 1021 and the second control unit 1022, respectively, as shown in FIG. 3 .

At this time, there is no need for the processor 10211 in the first control unit 1021 to store the data in the memory 10222 through the processor 10221 in the second control unit 1022, but the DMAC 10216 in the first control unit 1021 directly controls the second control unit The memory 10222 in the middle 1022 is accessed, and the data is stored in the memory 10222 in the second control unit 1022.

A complete DMA transmission process mainly includes the following steps, and FIG. 4 shows a schematic flow chart of the DMA transmission process, which will be described separately below.

(1) DMA request

The processor initializes the DMAC and issues an operation command to the I/O interface, and the I/O interface makes a DMA request to the DMAC. After receiving the request, the DMAC sends a request to the processor, and adds the request signal to the hold (HOLD) request input of the processor.

(2) DMA response

After receiving the request, the processor responds to the DMAC, adds its response signal to the DMAC's hold acknowledgement (HLDA) response output, and at the same time presets the first address of the storage space to be accessed and the number of exchanged data to the DMAC. And read and write commands, and give up the control of the system bus, at this time, DMAC obtains the control of the system bus.

(3) DMA transfer

After the DMAC obtains control of the system bus, the processor suspends immediately or only performs internal operations, and the DMAC performs data transmission.

(4) DMA ends

After completing the specified batch data transfer, the DMAC releases the bus control right and sends an end signal to the I/O interface.

It can be seen that the DMA transmission method does not require the processor to directly control the transmission, which greatly improves the efficiency of the processor.

However, for the computer system shown in FIG. 3, when the mirror storage is performed by DMA transmission, since the data needs to be stored in the exact same physical address space as the memory 10212 and the memory 10222, for example, the DMAC10216 transfers the data from the memory 10212 The physical address space is copied directly into the exact same physical address space in memory 10222.

If the memory space in the memory 10222 is faulty, and the DMAC10216 directly copies the data from the physical address space of the memory 10212 to the exact same physical address space in the memory 10222, it does not perceive the memory failure in the memory 10222. When the memory 10212 copies the data When writing to a faulty memory space in the memory 10222, an out of memory (OOM) may result.

The so-called memory overflow is usually a situation where there is insufficient memory to store the data that needs to be stored. For example, when running large-scale software or games, the memory required by the software or games far exceeds the capacity of the memory installed in the host, which is called memory overflow. At this point, the software or game cannot run, and the system will prompt a memory overflow.

In response to this problem, an embodiment of the present invention proposes a method for handling a memory failure, by enabling the local control (for example, the first control unit) to perform fault detection on the storage space supporting DMA before or after the OS is started, and The address of the faulty memory in the storage space is notified to the controller (for example, the second control unit), so that when the controller performs data backup in the storage space, the faulty memory can be isolated, thereby reducing the occurrence of OOM The probability.

The following describes the method 200 for handling a memory fault provided by the embodiment of the present invention. Figure 5 shows a schematic interaction flow diagram of the method. The method 200 may be applied in the computer system 100 .

201, the first control unit determines the address of the faulty memory in the first storage space, the first storage space is the storage space in the first control unit, and the first storage space can store the second control unit in a direct memory access DMA manner Data backed up in the first control unit.

Specifically, the first control unit (eg, the first control unit 1021 ) determines that the memory 10212 is configured to be able to store the second control unit (eg, the second control unit 1022 ) backed up in the first control unit 1021 in a DMA manner The address of the faulty memory in the storage space of the data (for example, the first storage space).

As an example and not a limitation, the first control unit determines the address of the faulty memory in the first storage space, including: the first processor performs an error correcting check (ECC) detection on the first storage space; the The first processor determines the address of the faulty memory in the first storage space according to the detection result of the ECC detection on the first storage space.

Specifically, the processor 10211 (eg, the first processor) in the first control unit 1021, when the computer system is powered on (ie, during the basic input output system (BIOS) startup), makes an impact on the memory 10212 ECC detection is performed on the first storage space in the ECC, that is, the ECC detection occurs before the operating system OS is started. According to the detection result of the ECC detection performed on the first storage space, the address of the faulty memory in the first storage space is determined.

In addition, the processor 10211 may also perform detection on the first storage space after the OS is started, that is, the ECC detection may also occur after the OS is started.

The processor 10211 may perform detection on the first storage space in a minimum unit of bytes; or, may also perform detection in a minimum unit of a certain number of bits.

For example, the processor 10211 performs ECC detection on the first storage space in units of bytes. After detection, the processor 10211 determines that the location of the faulty memory in the first storage space corresponds to the bytes whose index numbers are 4, 7, and 9. the location of the memory.

When page management is performed on the first storage space, page ECC detection may be performed on the first storage space. The so-called paging management refers to treating several bytes in the first storage space as a page (page), for example, each page includes 4 kilobits (Kbyte), at this time, the first storage space becomes a continuous page, That is, the first storage space is a page array, and each page of physical memory is called a page frame. The first storage space is numbered with the page as the smallest unit. The number can be used as the index number of the page array, also known as the page frame number.

That is, when page management is performed on the first storage space, ECC detection may be performed on the first storage space in units of pages.

For example, the processor 10211 performs ECC detection on the first storage space in units of pages. After detection, the processor 10211 determines that the location of the faulty memory in the first storage space is the page with the page frame numbers of 3, 8, 10, and 11. The corresponding memory location.

It should be noted that the above-mentioned solution of determining the location of the faulty memory in the first storage space by performing ECC detection on the first storage space is only an exemplary illustration, and does not constitute any limitation to the embodiments of the present invention. The solution in which the detection method determines the location of the faulty memory in the first storage space falls within the protection scope of the embodiments of the present invention.

202. The first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit.

Specifically, the processor 10211 determines the address of the faulty memory in the first storage space, and synchronizes the address of the faulty memory in the first storage space to the processor 10221 in the second control unit 1022 (for example, the second processor )middle.

For example, if the processor 10211 detects that the faulty memory in the first storage space is a continuous storage space, the processor 10211 can synchronize the start address and end address of the continuous storage space to the processor 10221.

For another example, if the processor 10211 detects that the byte with index number 6 to the byte with index number 8 in the first storage space is faulty, the processor 10211 will change the byte with index number 6 to the byte with index number 8. The start address and end address of the storage space corresponding to the bytes of , are synchronized to the processor 10221.

For another example, if the processor 10211 detects that the faulty memory in the first storage space is several discrete bytes, the processor 10211 can synchronize the addresses of the memory corresponding to the several bytes to the processor 10221.

In addition, the address of the faulty memory in the first storage space synchronized by the processor 10211 to the processor 10221 may also be the first address of the page frame where the faulty memory in the first storage space is located.

Specifically, when performing paging management on the first storage space, the processor 10211 synchronizes, to the processor 10221, the first address of the page where the detected faulty memory is located in the first storage space.

For example, the first addresses of pages with page frame numbers 1, 2, and 4 where the faulty memory is located in the first storage space detected by the processor 10211 are synchronized to the processor 10221.

It should be noted that, when the ECC detection performed by the processor 10211 on the first storage space occurs during the BIOS startup, if the processor 10211 determines that the memory in the first storage space is faulty, it can immediately delete the memory in the first storage space. The address of the failed memory is synchronized to the processor 10221.

In addition, before synchronizing the addresses of the faulty memory in the first storage space to the processor 10221, the processor 10211 may first count the number of addresses of the faulty memory in the first storage space, and calculate the number of addresses of the faulty memory in the first storage space. Compare with a preset threshold:

When the number is less than or equal to the preset threshold, the processor 10211 synchronizes the address of the faulty memory in the first storage space to the processor 10221;

When the number is greater than the preset threshold, the processor 10211 reallocates the storage space for DMA in the memory 10212.

For example, the processor 10211 detects the first storage space in bytes as the smallest unit, and the preset threshold is 10 bytes. After detection, the processor 10211 determines that the number of addresses of the faulty memory in the first storage space is 12 bytes, since the number of addresses of the faulty memory in the first storage space is greater than the preset threshold, the processor 10211 reallocates the memory 10212 that can store the second control unit 1022 in the first control unit 1021 in a DMA manner. Storage space for data backed up in .

It should be noted that, in this embodiment of the present invention, the storage space reallocated by the processor 10211 in the memory 10212 is usually a fault-free storage space.

However, in subsequent operations, the reallocated storage space may fail. Therefore, the processor 10211 can detect the reallocated storage space. When detecting that the memory in the reallocated storage space is faulty, The processor 10211 can synchronize the address of the memory in the reallocated storage space to the processor 10221.

Before synchronizing the address of the faulty memory in the first storage space to the control, by counting the number of addresses of the faulty memory in the first storage space, when the number is less than the preset threshold, the first The address of the faulty memory in one storage space is synchronized to the peer control, otherwise the memory space that can store the data backed up by the peer control in the local control by DMA will be re-allocated in the local control to avoid memory failure in the first storage space When the situation is more serious, it is still a waste of resources caused by synchronizing the faulty memory address to the control.

203. The second control unit acquires the address of the faulty memory in the first storage space.

Specifically, the processor 10221 obtains the address of the faulty memory in the first storage space synchronized by the processor 10211 to the processor 10221, and writes the address of the faulty memory in the first storage space into the isolation address table, the isolation address Tables may be stored in memory 10222.

For example, the address of the faulty memory in the first storage space obtained by the processor 10221 is the start address and end address of a continuous storage space, and the connected storage space is the byte with index number 6 to the index number of 8 bytes of storage space, the processor 10221 writes the start address and end address of the continuous storage space into the isolation address table, that is, the processor 10221 marks the faulty memory in the first storage space.

205. The second control unit stores the data buffered in the second control unit in the first storage space by means of DMA, and isolates the faulty memory in the first storage space when storing the data, wherein the data is stored in the first storage space. The processing unit performs the stored data through the second control unit.

Optionally, the second control unit stores the data cached in the second control unit in a storage space other than the faulty memory in the first storage space by means of DMA, including: the second control unit sends the data to the second control unit. The second DMAC in the device sends the second write data command, the second write data command is used to instruct the second DMAC to store the data buffered in the second control unit into the first storage space, and the destination address carried by the second write data command The indicated storage space is a storage space other than the faulty memory in the first storage space.

Specifically, if the processor 10221 needs to back up data in the memory 10212, the processor 10221 first checks the isolation address table, and determines the first storage space according to the address of the faulty memory in the first storage space recorded in the isolation address table. The address in memory that can be used for DMA.

The processor 10221 can send a write data access instruction (for example, the second write data instruction) to the DMAC 10226 (for example, the second DMAC), and the destination address carried in the data access instruction does not include the address of the faulty memory in the first storage space That is, the processor 10221 isolates the faulty memory in the first storage space.

After the DMAC10226 obtains the bus control right, according to the destination address carried by the second write data command, the data carried in the second write data command is written into the storage location indicated by the destination address in the first storage space by means of DMA.

For example, the processor 10221 determines that the faulty memory space in the first storage space is a continuous storage space, and the continuous storage space is the storage space corresponding to the byte with index number 6 to the byte with index number 8.

Assuming that the processor 10221 caches the data received from the server in the storage space corresponding to the byte with index number 4 in the memory 10222, the processor 10221 can send the second write data command to the DMAC 10226, and the second write data command carries the The destination address may correspond to the storage space corresponding to the byte whose index number is 4 in the first storage space.

After the DMAC10226 obtains the bus control right, according to the destination address carried in the second write data instruction, the data is written into the storage space corresponding to the byte with index number 4 in the first storage space by means of DMA.

Optionally, before the second control unit stores the data buffered in the second control unit to the first storage space in a DMA manner, the method 200 further includes:

204. The second control unit migrates the data cached in the address space corresponding to the address of the faulty memory in the first storage space to other storage spaces in the second storage space; wherein, the second storage space is the first storage space. 2. Storage space in the control unit.

Specifically, before the processor 10221 stores the data buffered in the second control unit in the first storage space by DMA, the processor 10221 also needs to determine the storage address of the data in the memory 10222 and the first storage space. Is the address of the faulty memory the same:

If the storage address of the data in the memory 10222 is completely different from the address of the faulty memory in the first storage space, the processor 10221 may store the data in the first storage space and the data in the second control unit Storage space with the same storage address;

If the storage address of the data in the memory 10222 corresponds to the address of the faulty memory in the first storage space, the storage address of the data here in the storage 10222 corresponds to the address of the faulty memory in the first storage space , and some or all of the storage addresses including data in the memory 10222 correspond to the addresses of the faulty memory in the first storage space.

When a partial storage address of the data in the memory 10222 corresponds to the address of the faulty memory in the first storage space, the processor 10221 can migrate the data stored in the storage space corresponding to the partial storage address to the second control unit A storage space corresponding to a storage address different from the faulty memory address in the first storage space. For example, the data is migrated to other storage spaces in the second storage space in the second control unit, or the processor 10221 can also migrate the data stored in the storage spaces corresponding to all the storage addresses, the present invention Examples are not particularly limited thereto.

In the following, an example will be given for the case where some or all of the storage addresses of the data in the memory 10222 correspond to the addresses of the faulty memory in the first storage space.

For example, the processor determines that the faulty memory in the first storage space is several discrete bytes, and the index numbers of the several discrete bytes may be 2, 6, 8, and 9.

Assuming that the processor 10221 caches the data received from the server in the storage space corresponding to the byte with index number 6 in the memory 10222, that is, the storage address of the data in the memory 10222 (the byte with the index number 6) is the same as the first The address of the faulty memory in the storage space (byte with index number 6) corresponds to, since the data needs to be stored in the exact same address space in the first control unit and the second control unit, however, the index in the first storage space The storage space corresponding to byte number 6 is faulty.

At this time, the processor 10221 needs to migrate the data in the memory 10222. For example, the processor 10221 migrates the data from the storage space corresponding to the byte with index number 6 to the storage space corresponding to the byte with index number 7, The destination address carried in the second write data instruction sent by the processor 10221 to the DMAC 10226 corresponds to the storage space corresponding to the byte whose index number is 7 in the first storage space. That is, the faulty memory in the first storage space is isolated.

DMAC10226 writes the data into the storage space corresponding to the byte whose index number is 7 in the first storage space by means of DMA according to the destination address carried in the second write data instruction.

For another example, the processor determines that the faulty memory in the first storage space is several discrete bytes, and the index numbers of the several discrete bytes may be 4, 5, 6, and 9.

It is assumed that the processor 10221 caches the data received from the server in the memory 10222 in the storage space corresponding to the byte with index number 6, the byte with index number 7, and the byte with index number 8, that is, the index number is 6 The data is stored in the storage space corresponding to the byte with index number 7, the byte with index number 7, and the byte with index number 8, respectively. The partial storage address of the data in memory 10222 (byte with index number 6) is the same as the The address of the faulty memory in the first storage space (byte with index number 6) corresponds to, because the data needs to be stored in the exact same address space in the first control unit and the second control unit, however, the first storage space The storage space corresponding to the byte with index number 6 is faulty.

At this time, the processor 10221 needs to migrate the data in the memory 10222. For example, the processor 10221 migrates the data stored in the storage space corresponding to the byte with the index number 6 to the one corresponding to the byte with the index number 3. Storage space, the destination address carried in the second write data instruction sent by the processor 10221 to the DMAC10226 corresponds to the byte with index number 3, the byte with index number 7 and the byte with index number 8 in the first storage space corresponding storage space. That is, the faulty memory in the first storage space is isolated. It should be noted that, when the processor 10221 migrates the data, it can only migrate the data stored in the storage space corresponding to the byte whose index number is 6. As another implementation manner, in order to ensure the continuity of the data storage address, the byte with index number 6, the byte with index number 7, and the byte with index number 8 may be stored in the storage spaces corresponding to the byte with index number 8, respectively. The data is migrated, which is not particularly limited in this embodiment of the present invention. For example, the processor 10221 migrates the data stored in the storage spaces corresponding to the byte with index number 6, the byte with index number 7, and the byte with index number 8, respectively, to the byte with index number 1 to The storage space corresponding to the byte with index number 3. Since there is no fault in the storage space corresponding to the byte with index number 1 to the byte with index number 3, the destination address carried in the second write data command sent by the processor 10221 to the DMAC 10226 corresponds to the index number in the first storage space It is the storage space corresponding to the bytes whose index number is 1 to 3, that is, the isolation of the faulty memory in the first storage space is realized.

The DMAC10226 writes the data into the storage space corresponding to the byte with index number 1 to the byte with index number 3 in the first storage space by DMA according to the destination address carried in the second write data instruction.

For another example, when performing paging management on the storage space, the processor 10221 determines that the first addresses of the pages where the faulty memory in the first storage space is located are d ₁ , d ₃ , and d ₅ , respectively.

Assuming that the processor 10221 caches the data received from the server in the page with the first address of d ₅ in the memory 10222, since the data needs to be stored in the exact same address space in the first control unit and the second control unit, however, the first A page in the memory space with address d ₅ is faulty.

At this time, the processor 10221 needs to migrate the data in the memory 10222. For example, the processor 10221 migrates the data from the page whose first address is d ₅ to the byte whose index number is 8 in the page whose first address is d ₄ For the corresponding storage space, the destination address carried in the second write data instruction sent by the processor 10221 to the DMAC 10226 corresponds to the storage space corresponding to the byte with index number 8 in the page whose first address is d ₄ in the first storage space. That is, the faulty memory in the first storage space is isolated.

The DMAC10226 writes the data into the storage space corresponding to the byte whose index number is 8 in the page with the first address of _d4 in the first storage space by means of DMA according to the destination address carried in the second write data instruction.

It should be noted that the storage addresses of the data listed above before or after the migration in the memory 10222, for example, the storage space corresponding to the byte with the index number 8 in the paging of d ₄ , are only exemplary descriptions, not No limitation is imposed on the embodiments of the present invention.

In addition, in this embodiment of the present invention, the processor 10211 can also repeatedly detect the faulty memory in the first storage space, and if it is found that the original faulty memory has been recovered, it is determined that the original faulty memory is a soft failure, Further, the address of the recovered memory in the first storage space can be synchronized to the processor 10221 .

By causing the local controller (for example, the first control unit) to perform fault detection on the storage space supporting DMA before or after the OS is started, and notify the controller (for example, the first control unit) of the address of the faulty memory in the storage space to the controller (for example, the first control unit). Two control units), so that when the control performs data backup in the storage space, it can isolate the faulty memory, thereby reducing the probability of OOM.

The following is a method for synchronizing the address of the faulty memory in the first storage space to the processor 10221 for the processor 10211 and the method for the processor 10221 to respectively use the ECC detection when the computer system is powered on or after the ECC detection occurs after the OS is started. The method for obtaining the address of the faulty memory in the first storage space will be described.

Scenario 1: ECC detection occurs when the computer system is powered on, and the number of addresses of faulty memory in the first storage space is less than or equal to a preset threshold.

The first control unit includes a first processor and a first motherboard management controller (baseboard management controller, BMC), the second control unit includes a second BMC, and synchronizes the address of the faulty memory in the first storage space to the second control unit , including: the first processor writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the first control unit; the first BMC obtains the first BMC from the pre-allocated storage space in the first control unit The address of the faulty memory in a storage space; the first BMC sends a first message to the second BMC, and the first packet carries the address of the faulty memory in the first storage space.

The second control unit includes a second processor and a second BMC, and the second control unit obtains the address of the faulty memory in the first storage space, including: the second BMC receives the first message sent by the first BMC, and the first message The text carries the address of the faulty memory in the first storage space; the second BMC parses the first message and obtains the address of the faulty memory in the first storage space; the second BMC parses the faulty memory in the first storage space; The address of the faulty memory is written into the pre-allocated storage space in the second control unit; the second processor obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the second control unit.

Specifically, when the processor 10211 performs ECC detection on the first storage space, when detecting a faulty memory in the first storage space, the processor 10211 writes the address of the detected faulty memory in the first storage space into the first storage space. In the pre-allocated storage space in the control unit 1021, the pre-allocated storage space in the first control unit 1021 may be the storage space in the memory 10212, or the pre-allocated storage space in the first control unit 1021 may also be the first storage space. A storage space in a complex programmable logic device (CPLD) 10218 (eg, the first CPLD) in the control unit 1021 .

The BMC10219 (for example, the first BMC) in the first control unit 1021 obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the first control unit 1021, and the BMC10219 will obtain the first storage The address of the faulty memory in the space is encapsulated in a message (for example, the first message), and the message is transmitted to the BMC10229 (for example, the second BMC) in the second control unit 1022 through the heartbeat channel, wherein the The message can be an Ethernet message.

The BMC10229 parses the received message, obtains the address of the faulty memory in the first storage space carried in the message, and writes the address of the faulty memory in the first storage space into the second control unit 1022 In the pre-allocated storage space in the second control unit 1022, the pre-allocated storage space in the second control unit 1022 may be the storage space in the memory 10222, or the pre-allocated storage space in the second control unit 1021 may also be the second control unit Storage space in CPLD 10228 (eg, second CPLD) in 1022.

The processor 10212 acquires the address of the faulty memory in the first storage space from the storage space pre-allocated in the second control unit 1022 .

Taking the pre-allocated storage space in the first control unit 1021 as the storage space in the CPLD 10218, and the pre-allocated storage space in the second control unit 1022 as the storage space in the CPLD 10228 as an example, the processor 10211 assigns the first storage space to the The method for synchronizing the address of the faulty memory in the processor 10221 and the method for the processor 10221 to obtain the address of the faulty memory in the first storage space will be described in detail.

When the pre-allocated storage space in the first control unit 1021 is the storage space in the CPLD 10218, the first control unit 1021 further includes a platform control unit (platform controller hub, PCH) 10217 (for example, the first PCH), wherein the PCH 10217 is an interface for communication between the processor 10211 and the CPLD10218; when the pre-allocated storage space in the second control unit 1022 is the storage space in the CPLD10227, the second control unit 1022 also includes a platform control unit (platform controller hub, PCH) 10227 (eg, the first PCH), wherein the PCH 10227 is an interface for communication between the processor 10221 and the CPLD 10228.

As shown in Figure 6, PCH10217 in Figure 6 is connected to the processor 10211 shown in Figures 1 to 3, CPLD10218 is connected to PCH10217, BMC10219 respectively, PCH10227 is connected to the processor 10221 shown in Figures 1 to 3, CPLD10228 is connected with PCH10227 and BMC10229 respectively. Among them, PCH can also be called bridge slice.

When the processor 10211 performs ECC detection on the first storage space and detects a faulty memory in the first storage space, the processor 10211 writes the address of the detected faulty memory in the first storage space to the address in the CPLD10218 through PCH10217. In the pre-allocated storage space, the storage space is dedicated to storing the address of the faulty memory in the first storage space, and both the PCH10217 and the BMC10219 can know the address of the storage space.

The CPLD10218 reports the interruption to the BMC10219, and at this time, the BMC10219 obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10218.

After the BMC10219 successfully obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10218, the BMC10219 will write the default fields (for example, write All 0 or all 1), that is, the address of the faulty memory in the first storage space stored in the pre-allocated storage space in the CPLD10218 is erased, so that the PCH10217 will subsequently detect the faulty memory in the first storage space. The address of the memory is written to the pre-allocated storage space in the CPLD10218.

In addition, the BMC10219 can also obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10218 by polling. For example, the BMC10219 can periodically perform a periodic Monitoring, when new information is written into the pre-allocated storage space, the BMC10219 can obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10218.

Similarly, after the BMC10219 successfully obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10218, it will store the address in the first storage space stored in the pre-allocated storage space in the CPLD10218. The address of the faulty memory is erased.

The BMC10219 encapsulates the acquired address of the faulty memory in the first storage space into a message (for example, the first message), and transmits the message to the BMC10229 through the heartbeat channel, where the message can be an Ethernet network message.

The BMC10229 parses the received message, obtains the address of the faulty memory in the first storage space carried in the message, and writes the address of the faulty memory in the first storage space into the pre-allocated memory in the CPLD10228 In the storage space, CPLD10228 reports an interruption to PCH10227, PCH10227 obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in CPLD10228, and sends the address of the faulty memory in the first storage space to processor 10221.

After PCH10227 successfully obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in CPLD10228, PCH10227 will write default fields (for example, write All 0 or all 1), that is, the address of the faulty memory in the first storage space stored in the pre-allocated storage space in the CPLD10228 is erased, so that the BMC10229 will subsequently detect the faulty memory in the first storage space. The address of the memory is written to the pre-allocated storage space in the CPLD10228.

In addition, the PCH10227 can also obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD10228 by polling. For example, the PCH10227 can periodically perform a periodic Monitoring, when new information is written in the pre-allocated storage space, the PCH10227 can obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the CPLD 10228.

Similarly, after PCH10227 successfully obtains the address of the faulty memory in the first storage space from the pre-allocated storage space in CPLD10228, it will store the address in the first storage space stored in the pre-allocated storage space of CPLD10228. The address of the faulty memory is erased.

It should be noted that, in addition to synchronizing the address of the faulty memory in the first storage space to the processor 10221 in the manner described above, the processor 10211 can also encapsulate the address of the faulty memory in the first storage space by the PCH10217 In the message, the message is sent to the PCH 10227, and after parsing the message, the PCH 10227 sends the obtained address of the faulty memory in the first storage space to the processor 10221.

Scenario 2: ECC detection happens after OS boot.

The first control unit includes a first processor and a first direct memory access controller DMAC, the second control unit includes a second processor, and synchronizes the address of the faulty memory in the first storage space to the second control unit, including: The first processor sends a first write data instruction to the first DMAC, where the first write data instruction carries the storage of address information of the faulty memory in the first storage space in the first storage subspace in the second storage space address, the second storage space is the storage space in the second control unit, the first storage subspace is used to store the address of the faulty memory in the first storage space, the second storage space also includes a second storage subspace, the second storage subspace The storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA; the first DMAC stores the address of the faulty memory in the first storage space to the first DMAC according to the first write data instruction. A storage subspace; the first processor sends a second message to the second processor, and the second message carries the storage address in the first storage subspace of address information of the faulty memory in the first storage space.

The second control unit includes a second processor, and the second control unit obtains the address of the faulty memory in the first storage space, including: the second processor receives the second message sent by the first processor, and the second message The storage address in the first storage subspace that carries the address information of the faulty memory in the first storage space; the second processor obtains the first storage subspace from the first storage subspace according to the storage address in the second message The address of the faulty memory in the space.

Specifically, after the OS system is started, the processor 10211 may continue to perform ECC detection on the first storage space. After detection, if the processor 10211 finds that the first storage space includes a faulty memory, the processor 10211 may The address of the faulty memory in one storage space is DMA-synchronized to the storage space in memory 10222 configured to store the address of the faulty memory in the first storage space (eg, the first storage space in the second storage space storage subspace).

For example, the processor 10211 can synchronize the address of the faulty memory in the first storage space to the first storage subspace in the memory 10222 in a DMA manner, that is, the DMAC 10216 (for example, the first DMAC) in the processor 10211 uses DMA to The first storage subspace in the memory 10222 is accessed by means of DMA, and the address of the faulty memory in the first storage space is written into the first storage subspace in the memory 10222 .

The first storage subspace may be a storage space divided in the memory 10222 in the BIOS stage. In addition, a second storage subspace may also be divided in the memory 10222, where the second storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA.

That is, the processor 10211 sends a data write command (eg, the first data write command) to the DMAC 10216, and the first write data command carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace , after the DMAC10216 obtains the bus control right, the DMAC10216 stores the address of the faulty memory in the first storage space to the first storage subspace in the storage 10222 according to the first write data instruction.

After the processor 10211 restores the control of the bus, it sends a message (for example, a second message) to the processor 10221, and the message carries the address of the memory in the first storage subspace that stores the faulty memory in the first storage space. address of the storage space.

The processor 10221 parses the message, obtains the address of the storage space in the first storage subspace that stores the address of the faulty memory in the first storage space, and obtains the address of the first storage space at the corresponding storage location in the storage 10222 The address of the faulty memory.

So far, the processor 10211 has synchronized the address of the faulty memory in the first storage space to the processor 10221.

It should be noted that the above-mentioned second storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA, which is only an exemplary illustration, and is not particularly limited in this embodiment of the present invention. For example, The second storage subspace may also be used for buffering the data received by the second control unit from the server and which needs to be backed up in the first control unit by means of DMA.

It should also be noted that, in this embodiment of the present invention, the address of the faulty memory in the first storage space may also be referred to as address information of the faulty memory in the first storage space, which is not particularly limited in the embodiment of the present invention. . By synchronizing the address of the faulty memory in the first storage space to the peer controller through DMA, the speed of fault synchronization is improved, so that the peer controller can find the address of the faulty memory in the local controller in time. When data access is performed in the space, the faulty memory can be isolated in a timely manner, so as to avoid data access to the faulty storage space in the local control due to untimely synchronization of the fault, which may lead to OOM.

It should be noted that when the ECC detection occurs after the OS is started, the method in the above-mentioned scenario 2 of the embodiment of the present invention is taken as an example, and the processor 10211 synchronizes the address of the faulty memory in the first storage space to the address of the processor 10221. The method is described, but the embodiment of the present invention is not limited to this. For example, when the ECC detection occurs after the OS is started, the processor 10211 can also follow the method described in Scenario 1. The address is synchronized into the processor 10221.

It should also be noted that, for the method for the processor 10211 to synchronize the address of the recovered memory in the first storage space to the processor 10221, please refer to the relevant descriptions in the above scenarios 1 and 2. For brevity, details are not repeated here. .

It should also be noted that, in the embodiment of the present invention, only the method in which the processor 10211 synchronizes the address of the faulty memory in the first storage space to the processor 10221 is used as an example for description. In the scenario where the address of the faulty memory in the storage space that supports DMA in the memory 10222 is synchronized to the processor 10211, the processor 10221 synchronizes the address of the faulty memory in the storage space for DMA in the memory 10222 to the processor 10211. For the method in the device 10211, please refer to the above related description, and for brevity, it will not be repeated here.

An embodiment of the present invention further provides an apparatus for handling a memory failure. The apparatus is configured in the computer system 100 and includes a first control unit and a second control unit. The first control unit is used to execute the method 200 by the first control unit. The operation steps of the method performed by the second control unit 1021 are used to perform the steps performed by the second control unit 1022 in the method 200 , and the second control unit includes the operation steps of the method performed by the second control unit 1022 .

The apparatus for handling memory failures provided by the embodiments of the present invention enables the local control (for example, the first control unit) to perform failure detection on the storage space supporting DMA before or after the OS is started, and detects the failure in the storage space. The address of the memory is notified to the controller (for example, the second control unit), and when the controller performs data backup in the storage space, the faulty memory in the storage space is isolated, that is, only in this controller Data backup is performed in the storage space where memory failure occurs, thereby reducing the probability of OOM.

An embodiment of the present invention further provides a computer system 300. As shown in FIG. 7, the computer system 300 includes a processing unit 301 and a storage control unit 302, the storage control unit 302 is connected to the processing unit 301, and the storage control unit 302 include:

The first control unit 3021 is used to determine the address of the faulty memory in the first storage space, where the first storage space is the storage space in the first control unit 3021, and the first storage space can store the second control unit 3022 Data backed up in the first control unit 3021 by means of direct memory access DMA;

The first control unit 3021 is further configured to synchronize the address of the faulty memory in the first storage space to the second control unit 3022;

The second control unit 3022 is configured to obtain the address of the faulty memory in the first storage space;

The second control unit 3022 is further configured to store the data buffered in the second control unit 3022 in the first storage space in a DMA manner, and isolate a fault in the first storage space when storing the data memory, wherein the data is the data stored by the processing unit through the second control unit 3022.

Optionally, the second control unit 3022 is further configured to, before storing the data cached in the second control unit 3022 to the first storage space by DMA, store the data cached in the faulty memory with the first storage space. The data in the address space corresponding to the address of , is migrated to other storage spaces in the second storage space; wherein, the second storage space is the storage space in the second control unit 3022 .

Optionally, the first control unit 3021 includes a first processor and a first motherboard management controller BMC, and the second control unit 3022 includes a second BMC, the first processor, for storing in the first storage space The address of the faulty memory is written into the storage space pre-allocated in the first control unit 3021; the first BMC is used to obtain the fault in the first storage space from the storage space pre-allocated in the first control unit 3021 The address of the memory; the first BMC is further configured to send a first message to the second BMC, where the first message carries the address of the faulty memory in the first storage space.

Optionally, the first control unit 3021 further includes a first platform control unit PCH and a first complex programmable logic device CPLD, and the pre-allocated storage space in the first control unit 3021 is the storage space in the first CPLD, and the first A processor is further configured to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the first CPLD through the first PCH; the first BMC is further configured to retrieve the address from the first storage space The address of the faulty memory in the first storage space is obtained from the pre-allocated storage space in a CPLD.

Optionally, the first control unit 3021 includes a first processor and a first direct memory access controller DMAC, and the second control unit 3022 includes a second processor, the first processor, and is further configured to send the first DMAC to the first DMAC. A write data command, the first write data command carries the storage address of the address of the faulty memory in the first storage space in the first storage subspace in the second storage space, and the second storage space is the The storage space in the second control unit 3022, the first storage subspace is used to store the address of the faulty memory in the first storage space, the second storage space further includes a second storage subspace, the second storage subspace The space is used to store the data backed up by the first control unit 3021 in the second control unit 3022 by means of DMA; the first DMAC is used to store the faulty data in the first storage space according to the first write data instruction. The address of the memory is stored in the storage space corresponding to the storage address in the first storage subspace;

The first processor is further configured to send a second message to the second processor, where the second message carries the storage of the address of the faulty memory in the first storage space in the first storage subspace address.

Optionally, the second control unit 3022 includes a second processor and a second BMC, and the second BMC is used to receive the first message sent by the first BMC, where the first message carries the first storage The address of the faulty memory in the space; the second BMC is also used to parse the first message to obtain the address of the faulty memory in the first storage space; the second BMC is also used to The address of the faulty memory in the storage space is written into the storage space pre-allocated in the second control unit 3022; the second processor is configured to obtain the first The address of the faulty memory in the storage space.

Optionally, the second control unit 3022 further includes a second PCH and a second CPLD, and the pre-allocated storage space in the second control unit 3022 is the storage space in the second CPLD, and the second BMC is also used to store the first The address of the faulty memory in the storage space is written into the pre-allocated storage space in the second CPLD; the second processor is further configured to obtain the first storage space from the pre-allocated storage space in the second CPLD The address of the faulty memory in the space, including: a second processor, further configured to obtain the address of the faulty memory in the first storage space from the pre-allocated storage space in the second CPLD through the second PCH .

Optionally, the second control unit 3022 includes a second processor, and the second processor is further configured to receive the second message sent by the first processor, where the second message carries the information in the first storage space. The storage address of the address of the faulty memory in the first storage subspace; the second processor is further configured to obtain from the storage space corresponding to the storage address in the first storage subspace according to the second message The address of the faulty memory in the first storage space.

Optionally, the first processor is further configured to perform correctable error ECC detection on the first storage space; according to the detection result of performing ECC detection on the first storage space, determine the faulty memory in the first storage space. address.

Optionally, the first control unit 3021 is also used to count the number of addresses of the faulty memory in the first storage space; if the number is less than or equal to a preset threshold The address of the memory is synchronized to the second control unit 3022 .

Optionally, the address of the faulty memory in the first storage space includes the first address of the page frame where the faulty memory in the first storage space is located.

Optionally, the second control unit 3022 is further configured to send a second write data instruction to the second DMAC in the second control unit 3022, where the second write data instruction is used to instruct the second DMAC to cache in the second DMAC. The data in the second control unit is stored in the first storage space, and the storage space indicated by the destination address carried by the second write data instruction is the storage space other than the faulty memory in the first storage space.

Optionally, the computer system 300 further includes a storage unit 303, the first control unit 3021 and the second control unit 3022 are both connected to the storage unit 303, and the processing unit 301 is further configured to store the data in the storage unit through the second control unit 3022 303.

In the computer system provided by the embodiments of the present invention, the local control (for example, the first control unit) performs fault detection on the storage space that supports DMA before or after the OS is started, and records the faulty memory in the storage space. The address is notified to the controller (for example, the second control unit), and when the controller performs data backup in the storage space, it isolates the faulty memory in the storage space, that is, only in this controller, no memory failure occurs. Data backup is performed in the storage space, thereby reducing the probability of OOM.

An embodiment of the present invention provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the instructions are executed on a computer, the computer executes the steps in the foregoing method 200 .

An embodiment of the present invention provides a computer program product containing instructions, when the instructions are run on a computer, the computer causes the computer to execute the steps in the above method 200 .

Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, removable hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (20)

1. A method for handling memory failure, applied in a computer system, wherein the computer system comprises a processing unit, a first control unit, a second control unit, the first control unit and the second control unit The units are all connected to the processing unit, including: The first control unit determines the address of the faulty memory in the first storage space, the first storage space is the storage space in the first control unit, and the first storage space can store the second control the data backed up by the unit in the first control unit by means of direct memory access DMA; the first control unit synchronizes the address of the faulty memory in the first storage space to the second control unit; The second control unit acquires the address of the faulty memory in the first storage space; The second control unit stores the data buffered in the second control unit to the first storage space in a DMA manner, and isolates a fault in the first storage space when storing the data memory, wherein the data is data stored by the processing unit through the second control unit. 2. The method according to claim 1, wherein before the second control unit stores the data buffered in the second control unit to the first storage space in a DMA manner, The method also includes: The second control unit migrates the data cached in the address space corresponding to the address of the faulty memory in the first storage space to other storage spaces in the second storage space; wherein the second storage space is the storage space in the second control unit. 3. The method according to claim 1 or 2, wherein the first control unit includes a first processor and a first BMC, the second control unit includes a second BMC, and the first control unit includes a second BMC. The address of a faulty memory in a storage space is synchronized to the second control unit, including: The first processor writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the first control unit; The first BMC obtains the address of the faulty memory in the first storage space from the storage space pre-allocated in the first control unit; The first BMC sends a first packet to the second BMC, where the first packet carries an address of a faulty memory in the first storage space. 4. The method according to claim 3, wherein the first control unit further comprises a first PCH and a first CPLD, and the pre-allocated storage space in the first control unit is the storage space in the first CPLD. The first processor writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the first control unit, including: The first processor writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the first CPLD through the first PCH; The first BMC obtains the address of the faulty memory in the first storage space from the storage space pre-allocated in the first control unit, including: The first BMC acquires, from the pre-allocated storage space in the first CPLD, the address of the faulty memory in the first storage space. 5. The method according to claim 1 or 2, wherein the first control unit comprises a first processor and a first DMAC, the second control unit comprises a second processor, and the The address of the faulty memory in the first storage space is synchronized to the second control unit, including: The first processor sends a first write data instruction to the first DMAC, where the first write data instruction carries the address of the faulty memory in the first storage space in the second storage space. A storage address in a storage subspace, the second storage space is a storage space in the second control unit, and the first storage subspace is used to store the address of the faulty memory in the first storage space , the second storage space further includes a second storage subspace, and the second storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA; The first DMAC stores the address of the faulty memory in the first storage space to the storage space corresponding to the storage address in the first storage subspace according to the first write data instruction; The first processor sends a second message to the second processor, where the second message carries the address of the faulty memory in the first storage space in the first storage subspace storage address. 6 . The method according to claim 3 , wherein the second control unit comprises a second processor and a second BMC, and the second control unit obtains the data of the faulty memory in the first storage space. 7 . address, including: The second BMC receives the first message sent by the first BMC, where the first message carries the address of the faulty memory in the first storage space; The second BMC parses the first message, and obtains the address of the faulty memory in the first storage space; The second BMC writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the second control unit; The second processor acquires the address of the faulty memory in the first storage space from the storage space pre-allocated in the second control unit. 7. The method according to claim 6, wherein the second control unit further comprises a second PCH and a second CPLD, and the pre-allocated storage space in the second control unit is the storage space in the second CPLD. storage space, The second BMC writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the second control unit, including: The second BMC writes the address of the faulty memory in the first storage space into the pre-allocated storage space in the second CPLD; The second processor obtains, from the pre-allocated storage space in the second control unit, the address of the faulty memory in the first storage space, including: The second processor obtains, by using the second PCH, an address of the faulty memory in the first storage space from a pre-allocated storage space in the second CPLD. 8. The method according to claim 5, wherein the second control unit comprises a second processor, and the second control unit obtains the address of the faulty memory in the first storage space, comprising: The second processor receives the second message sent by the first processor, where the second message carries the address of the faulty memory in the first storage space in the first storage space storage address in the subspace; The second processor acquires, according to the second message, an address of a memory having a fault in the first storage space from a storage space corresponding to the storage address in the first storage subspace. 9. The method according to claim 1 or 2, wherein the second control unit stores the data buffered in the second control unit to the first storage space in a DMA manner, and isolating the faulty memory in the first storage space when storing the data, including: The second control unit sends a second write data command to the second DMAC in the second control unit, where the second write data command is used to instruct the second DMAC to buffer in the second control unit The data stored in the first storage space is stored in the first storage space, and the storage space indicated by the destination address carried by the second write data instruction is the storage space other than the faulty memory in the first storage space. 10. The method according to claim 1 or 2, wherein the computer system further comprises a storage unit, the first control unit and the second control unit are both connected to the storage unit, and the method Also includes: The processing unit stores the data to the storage unit through the second control unit. 11. A computer system, characterized in that the computer system comprises a processing unit and a storage control unit, the storage control unit is connected to the processing unit, and the storage control unit comprises: a first control unit, configured to determine an address of a faulty memory in a first storage space, where the first storage space is a storage space in the first control unit, and the first storage space can store a second control unit Data backed up in the first control unit by means of direct memory access DMA; the first control unit, further configured to synchronize the address of the faulty memory in the first storage space to the second control unit; the second control unit, configured to obtain the address of the faulty memory in the first storage space; The second control unit is further configured to store the data buffered in the second control unit to the first storage space in a DMA manner, and isolate the first storage space when storing the data There is a faulty memory in the space, wherein the data is data stored by the processing unit through the second control unit. 12. The computer system of claim 11, wherein The second control unit is further configured to, before storing the data buffered in the second control unit to the first storage space in a DMA manner, store the data buffered in the first storage space with the data The data in the address space corresponding to the address of the faulty memory is migrated to other storage spaces in the second storage space; wherein the second storage space is the storage space in the second control unit. 13. The computer system according to claim 11 or 12, wherein the first control unit comprises a first processor and a first BMC, the second control unit comprises a second BMC, the first processor, configured to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the first control unit; The first BMC is used to obtain the address of the faulty memory in the first storage space from the storage space pre-allocated in the first control unit; The first BMC is further configured to send a first message to the second BMC, where the first message carries the address of the faulty memory in the first storage space. 14. The computer system according to claim 13, wherein the first control unit further comprises a first PCH and a first CPLD, and the pre-allocated storage space in the first control unit is the first CPLD storage space in The first processor is further configured to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the first CPLD through the first PCH; The first BMC is further configured to obtain the address of the faulty memory in the first storage space from the storage space pre-allocated in the first control unit, including: The first BMC is further configured to acquire, from the pre-allocated storage space in the first CPLD, the address of the faulty memory in the first storage space. 15. The computer system according to claim 11 or 12, wherein the first control unit comprises a first processor and a first DMAC, the second control unit comprises a second processor, The first processor is further configured to send a first write data instruction to the first DMAC, where the first write data instruction carries the address of the faulty memory in the first storage space in the second storage space. The storage address in the first storage subspace in the space, the second storage space is the storage space in the second control unit, and the first storage subspace is used to store the fault in the first storage space address of the memory, the second storage space further includes a second storage subspace, and the second storage subspace is used to store the data backed up by the first control unit in the second control unit by means of DMA ; The first DMAC is configured to store the address of the faulty memory in the first storage space to the storage space corresponding to the storage address in the first storage subspace according to the first write data instruction ; The first processor is further configured to send a second packet to the second processor, where the second packet carries the address of the faulty memory in the first storage space in the first storage space. The storage address in the storage subspace. 16. The computer system according to claim 13, wherein the second control unit comprises a second processor and a second BMC, The second BMC is configured to receive the first message sent by the first BMC, where the first message carries the address of the faulty memory in the first storage space; The second BMC is further configured to parse the first message, and obtain the address of the faulty memory in the first storage space; The second BMC is further configured to write the address of the faulty memory in the first storage space into a pre-allocated storage space in the second control unit; The second processor is configured to acquire the address of the faulty memory in the first storage space from the storage space pre-allocated in the second control unit. 17. The computer system according to claim 16, wherein the second control unit further comprises a second PCH and a second CPLD, and the pre-allocated storage space in the second control unit is the second CPLD storage space in The second BMC is further configured to write the address of the faulty memory in the first storage space into the pre-allocated storage space in the second CPLD; the second processor is further configured to pass The second PCH acquires the address of the faulty memory in the first storage space from the pre-allocated storage space in the second CPLD. 18. The computer system of claim 15, wherein the second control unit comprises a second processor, The second processor is further configured to receive the second message sent by the first processor, where the second message carries the address of the faulty memory in the first storage space at the location. Describe the storage address in the first storage subspace; The second processor is further configured to acquire, according to the second message, the address of the memory with the fault in the first storage space from the storage space corresponding to the storage address in the first storage subspace . 19. The computer system according to claim 11 or 12, wherein the second control unit is further configured to send a second write data instruction to the second DMAC in the second control unit, the second control unit The second write data instruction is used to instruct the second DMAC to store the data buffered in the second control unit into the first storage space, and the destination address carried by the second write data instruction indicates the The storage space is a storage space other than the faulty memory in the first storage space. 20. The computer system according to claim 11 or 12, wherein the computer system further comprises a storage unit, the first control unit and the second control unit are both connected to the storage unit, The processing unit is further configured to store the data in the storage unit through the second control unit.

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