CN109411561B - A layout design method, production process and optocoupler of a phototransistor chip - Google Patents
A layout design method, production process and optocoupler of a phototransistor chip Download PDFInfo
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- CN109411561B CN109411561B CN201811155931.3A CN201811155931A CN109411561B CN 109411561 B CN109411561 B CN 109411561B CN 201811155931 A CN201811155931 A CN 201811155931A CN 109411561 B CN109411561 B CN 109411561B
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000002513 implantation Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 9
- 230000003321 amplification Effects 0.000 claims description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 241000409201 Luina Species 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- -1 phosphorus ions Chemical class 0.000 claims description 3
- 238000001556 precipitation Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 230000035945 sensitivity Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000011160 research Methods 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
The invention discloses a layout design method of a phototriode chip, which comprises the following steps: arranging a single photosensitive triode chip on a silicon chip, and arranging the single photosensitive triode chip on the silicon chip in an array mode, wherein the photosensitive triode chip after the array arrangement is a chip array; a test point region is arranged on the chip array, a base PAD is arranged on the base region of the single photosensitive triode chip in the test point region, and the base PAD does not need to be arranged on the base region of the single photosensitive triode chip in the non-test point region. Compared with the prior art, the invention can meet the test requirement and increase the light receiving area of the photosensitive triode chip in the non-test point region, thereby improving the current conversion ratio of the photoelectric coupler.
Description
Technical Field
The invention relates to the technical field of electronic elements, in particular to a layout design method and a production process of a phototriode chip and an optical coupler.
Background
Photoelectric coupler as a kind of electro-optical-to-electric conversion isolated safety device, has extensive market application field and environment, and some high-power products use, because circuit board design factor, need more efficient current conversion ratio, and for improving the CTR value, the manufacturer has to adopt following mode:
1. the power of the emission chip is improved, the light emission quantity is increased, but the mode can cause the increase of the heat productivity of the chip, the light emission attenuation of the chip is serious, and the service life is reduced;
2. the amplification factor of the photosensitive triode chip is improved, but the mode can cause the increase of the leakage current of the chip, the reduction of reverse voltage and the reduction of reaction sensitivity, even exceeds the standard parameter range of a photoelectric coupler product when the chip is serious, and the product performance and the service life of the photoelectric coupler are influenced.
According to researches, under the condition that other parameters are not changed, the light receiving area of the photosensitive triode chip is increased, and the current conversion ratio of the photoelectric coupler can be improved. Please refer to fig. 1, when the conventional photo triode chip is designed in the production layout, a base PAD for performing the amplification test is disposed in a base region of each photo triode chip, the base region is a light receiving region of the photo triode chip, the base PAD can reduce the area of the light receiving region, and in the actual production test, because the size of a single photo triode chip is small, about 100000 photo triode chips are disposed on each silicon chip, the amplification test is performed on 200 photo triode chips therein generally in a sampling inspection mode, the layout design method that each photo triode chip is provided with the base PAD reduces the area of the base region of the photo triode chip, thereby reducing the current conversion ratio of the photoelectric coupler.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a layout design method of a phototriode chip, which is used for solving the problem that the area of a base region of the phototriode chip is reduced by the layout design method that each phototriode chip is provided with a base PAD.
The invention comprises the following contents:
a layout design method of a photo triode chip comprises the following steps:
arranging a single-chip phototriode chip on a silicon chip, wherein the single-chip phototriode chip comprises a base region, an emission region, an emitting electrode PAD and a collector electrode, the emission region is arranged on the surface layer of the base region, an anti-leakage ring is arranged on the outer side of the emission region, the emitting electrode PAD is arranged in the anti-leakage ring and connected with the anti-leakage ring, and the collector electrode is arranged at the bottom of the chip;
arranging the single-chip photosensitive triode chips on a silicon chip in an array mode, wherein the photosensitive triode chips after the array arrangement are chip arrays;
a test point region is arranged on the chip array, a base PAD is arranged on the base region of the single photosensitive triode chip in the test point region, and the base PAD does not need to be arranged on the base region of the single photosensitive triode chip in the non-test point region.
Preferably, the anti-leakage ring is a square anti-leakage ring or a square anti-leakage ring with a round angle.
Preferably, the width of the anti-leakage ring is less than or equal to 0.012 mm.
Preferably, the emitter PAD is a circular PAD.
Preferably, the diameter of the circular PAD is less than or equal to 0.112 mm.
Preferably, the base PAD is a square PAD.
Preferably, the base PAD is a square PAD, and the side length of the base PAD is less than or equal to 0.05 mm.
The invention also provides a production process of the light-sensitive triode chip, which comprises the following steps:
determining the photoetching position of the photosensitive triode chip by adopting the layout design method of the photosensitive triode chip;
selecting a silicon wafer and coating an oxide layer on the surface of the silicon wafer to isolate a subsequent anti-leakage ring on the surface of the chip from the silicon wafer;
photoetching the base region, and doping the base region by boron ion implantation with an implantation energy of 100-150keV and an implantation boron dose of 1e14～2e15cm-2The base regions are redistributed and pushed after ion implantation, and the distance between the independent base regions is ensured to be 5-10 mu m after the base regions are photoetched and diffused and doped;
photoetching the emitter region, implanting phosphorus ions into the emitter region with implantation energy of 80-120keV and phosphorus implantation dose of 5e14～5e15cm-2After ion implantation, the emitter region is redistributed and knotted;
photoetching and developing the diffused base region and the diffused emitter region, and cleaning redundant parts to ensure that the shape and the size meet the design requirements;
covering a metal layer on the surface of the corroded area of the chip by adopting a metal evaporation and precipitation method, and tightly combining the metal layer covered on the functional area of the chip with the chip;
carrying out amplification factor test on the chip, reducing the thickness of the chip to ensure that the thickness meets the design requirement, and carrying out gold or silver back treatment on the chip;
the chip is cut and packaged.
The invention also provides an optical coupler which comprises a shell, an emission chip and a photosensitive triode chip, wherein the emission chip and the photosensitive triode chip are packaged in the shell, the emission chip and the photosensitive triode chip are both connected with lead frames, the photosensitive triode chip is manufactured by adopting the production process of the photosensitive triode chip, and a light emitting area of the emission chip is right opposite to a base area of the photosensitive triode chip.
Preferably, a first alloy wire is connected between the emission chip and the lead frame, a second alloy wire is connected between the photo-triode chip and the lead frame, and epoxy resin glue is packaged between the emission chip and the photo-triode chip.
The invention has the beneficial effects that: compared with the prior art, the invention can meet the test requirement and increase the light receiving area of the photosensitive triode chip in the non-test point region, thereby improving the current conversion ratio of the photoelectric coupler.
Drawings
FIG. 1 is a layout diagram of a prior art photo-transistor chip;
FIG. 2 is a layout diagram of a phototransistor chip according to an embodiment of the present invention;
fig. 3 is a structural diagram of an optocoupler according to an embodiment of the invention.
Detailed description of the invention
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Referring to fig. 2, a layout design method of a photo triode chip disclosed in this embodiment includes the following steps:
arranging a single-chip phototriode chip on a silicon chip, wherein the single-chip phototriode chip comprises a base region 1, an emission region, an emitting electrode PAD 2 and a collector electrode, the emission region is arranged on the surface layer of the base region 1, an anti-leakage ring 3 is arranged on the outer side of the emission region, the emitting electrode PAD 2 is arranged in the anti-leakage ring 3 and connected with the anti-leakage ring 3, and the collector electrode is arranged at the bottom of the chip;
arranging the single-chip photosensitive triode chips on a silicon chip in an array mode, wherein the photosensitive triode chips after the array arrangement are chip arrays;
set up the test point region on the chip array, set up base PAD 4 on the base region 1 of the regional monolithic photosensitive triode chip of test point, base PAD 4 is used for carrying out the magnification test, need not set up base PAD 4 on the base region 1 of the regional monolithic photosensitive triode chip of non-test point, compare with prior art, both can satisfy the test requirement, also can increase the regional photosensitive triode chip's of non-test point area of receiving light, under the condition that does not improve the magnification, improve photoelectric coupler's current conversion ratio, under photoelectric coupler's current conversion ratio and other parameter the same conditions promptly, the photoelectric triode chip magnification that this implementation provided is lower, be favorable to improving photoelectric coupler's sensitivity.
The anti-leakage ring 3 adopts square anti-leakage ring or square anti-leakage ring with round angle, the width of the anti-leakage ring 3 is less than or equal to 0.012mm, and compared with 0.022mm in the prior art, the embodiment can increase the area of the light receiving area inside the anti-leakage ring 3 on the premise of ensuring the anti-leakage function.
The emitting electrode PAD 2 is a circular PAD, the diameter of the circular PAD is less than or equal to 0.112mm, the emitting electrode PAD 2 in the prior art is a rounded square with the side length of 0.132mm, the emitting electrode PAD 2 in the embodiment can meet the size requirement of a bonding solder ball, the area is smaller, and the area of a light receiving area can be indirectly increased.
The base PAD 4 is a square PAD or a square PAD, the side length of the base PAD 4 is less than or equal to 0.05mm, and compared with 0.072mm in the prior art, the area of the base PAD 4 is smaller, and the area of the base region 1 is larger.
This embodiment reduces the width of anticreep ring through the overall arrangement design that changes photosensitive triode chip, reduces the area of projecting pole PAD and base PAD, under the condition that does not change chip size, increases the area of receiving the light zone, is favorable to under the condition of equal current conversion ratio requirement and equal emission chip power, reduces photosensitive triode chip's magnification, can effectively improve photoelectric coupler's reaction sensitivity.
The embodiment further provides a manufacturing process of the photo triode chip, which comprises the following steps:
determining the photoetching position of the photosensitive triode chip by adopting the layout design method of the photosensitive triode chip;
selecting a silicon wafer and coating an oxide layer on the surface of the silicon wafer to isolate a subsequent anti-leakage ring on the surface of the chip from the silicon wafer;
photoetching the base region, and doping the base region by boron ion implantation with an implantation energy of 100-150keV and an implantation boron dose of 1e14～2e15cm-2The base regions are redistributed and pushed after ion implantation, and the distance between the independent base regions is ensured to be 5-10 mu m after the base regions are photoetched and diffused and doped;
photoetching the emitter region, implanting phosphorus ions into the emitter region with implantation energy of 80-120keV and phosphorus implantation dose of 5e14～5e15cm-2After ion implantation, the emitter region is redistributed and knotted;
photoetching and developing the diffused base region and the diffused emitter region, and cleaning redundant parts to ensure that the shape and the size meet the design requirements;
covering a metal layer on the surface of the corroded area of the chip by adopting a metal evaporation and precipitation method, and tightly combining the metal layer covered on the functional area of the chip with the chip;
carrying out amplification factor test on the chip, reducing the thickness of the chip to ensure that the thickness meets the design requirement, and carrying out gold or silver back treatment on the chip;
the chip is cut and packaged.
The embodiment also provides an optical coupler, which comprises a shell 61, and an emission chip 62 and a photo triode chip 63 which are packaged in the shell 61, wherein the emission chip 62 and the photo triode chip 63 are both connected with a lead frame 64, the photo triode chip 63 is manufactured by adopting the production process of the photo triode chip, the requirements for improving the power of the emission chip and the amplification factor of the photo triode chip can be effectively reduced, the product limitation is reduced, the possibility of weakening of the basic electrical property parameters of the photo triode chip caused by excessive improvement of the power and the amplification factor is reduced, and the reliability of the product of the photoelectric coupler is improved. The light emitting area of the emitting chip 62 is right opposite to the base area of the photo triode chip 63, which is beneficial to increasing the light receiving quantity of the photo triode chip and improving the sensitivity of the optical coupler.
A first alloy wire 65 is connected between the emission chip 62 and the lead frame 64, a second alloy wire 66 is connected between the phototriode chip 63 and the lead frame 64, and white epoxy glue 67 is packaged between the emission chip 62 and the phototriode chip 63.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above implementation method, and the present invention shall fall within the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The technical solution and/or the implementation method thereof may be variously modified and varied within the scope of the present invention.
Claims (10)
1. A layout design method of a photo triode chip is characterized by comprising the following steps:
arranging a single-chip phototriode chip on a silicon chip, wherein the single-chip phototriode chip comprises a base region (1), an emitting region, an emitting electrode PAD (2) and a collector electrode, the emitting region is arranged on the surface layer of the base region (1), an anti-leakage ring (3) is arranged on the outer side of the emitting region, the emitting electrode PAD (2) is arranged in the anti-leakage ring (3) and is connected with the anti-leakage ring (3), and the collector electrode is arranged at the bottom of the chip;
arranging the single-chip photosensitive triode chips on a silicon chip in an array mode, wherein the photosensitive triode chips after the array arrangement are chip arrays;
a test point region is arranged on the chip array, a base PAD (4) is arranged on a base region (1) of the single photosensitive triode chip in the test point region, and the base PAD (4) is not required to be arranged on the base region (1) of the single photosensitive triode chip in the non-test point region.
2. The layout design method of a phototransistor chip as set forth in claim 1, wherein: the anti-leakage ring (3) is a square anti-leakage ring or a square anti-leakage ring with a round angle.
3. The layout design method of a phototransistor chip as set forth in claim 2, wherein: the width of the anti-creeping ring (3) is less than or equal to 0.012 mm.
4. The layout design method of a phototransistor chip as set forth in claim 1, wherein: the emitter PAD (2) adopts a circular PAD.
5. The layout design method of a phototransistor chip as set forth in claim 4, wherein: the diameter of the circular PAD is less than or equal to 0.112 mm.
6. The layout design method of a phototransistor chip as set forth in claim 1, wherein: the base PAD (4) adopts a square PAD.
7. The layout design method of a phototransistor chip as set forth in claim 6, wherein: the base PAD (4) is a square PAD, and the side length of the base PAD (4) is less than or equal to 0.05 mm.
8. A production process of a photosensitive triode chip is characterized by comprising the following steps:
determining the photoetching position of the light sensitive triode chip by adopting the layout design method of the light sensitive triode chip as claimed in any one of claims 1 to 7;
selecting a silicon wafer and coating an oxide layer on the surface of the silicon wafer to isolate a subsequent anti-leakage ring on the surface of the chip from the silicon wafer;
photoetching the base region, and doping the base region by boron ion implantation with an implantation energy of 100-150keV and an implantation boron dose of 1e14～2e15cm-2The base regions are redistributed and pushed after ion implantation, and the distance between the independent base regions is ensured to be 5-10 mu m after the base regions are photoetched and diffused and doped;
photoetching the emitter region, implanting phosphorus ions into the emitter region with implantation energy of 80-120keV and phosphorus implantation dose of 5e14～5e15cm-2After ion implantation, the emitter region is redistributed and knotted;
photoetching and developing the diffused base region and the diffused emitter region, and cleaning redundant parts to ensure that the shape and the size meet the design requirements;
covering a metal layer on the surface of the corroded area of the chip by adopting a metal evaporation and precipitation method, and tightly combining the metal layer covered on the functional area of the chip with the chip;
carrying out amplification factor test on the chip, reducing the thickness of the chip to ensure that the thickness meets the design requirement, and carrying out gold or silver back treatment on the chip;
the chip is cut and packaged.
9. An optocoupler comprising a casing (61), an emitting chip (62) and a phototriode chip (63) enclosed inside the casing (61), the emitting chip (62) and the phototriode chip (63) being connected to a lead frame (64), characterized in that: the process for manufacturing a light-sensitive triode chip (63) according to claim 8, the light-emitting region of the emitter chip (62) being directly opposite the base region of the light-sensitive triode chip (63).
10. The optical coupler of claim 9, wherein: a first alloy wire (65) is connected between the emission chip (62) and the lead frame (64), a second alloy wire (66) is connected between the phototriode chip (63) and the lead frame (64), and epoxy resin glue is packaged between the emission chip (62) and the phototriode chip (63).
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| CN201811155931.3A CN109411561B (en) | 2018-09-30 | 2018-09-30 | A layout design method, production process and optocoupler of a phototransistor chip |
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| CN205104488U (en) * | 2015-11-02 | 2016-03-23 | 华润半导体（深圳）有限公司 | Opto -coupler packaging structure , voltage feedback circuit, system and equipment |
| CN105590972A (en) * | 2014-11-11 | 2016-05-18 | 株式会社理光 | Semiconductor device, manufacturing method thereof and imaging apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7317204B2 (en) * | 2005-01-13 | 2008-01-08 | Samsung Electronics Co., Ltd. | Test structure of semiconductor device |
| JP4970787B2 (en) * | 2005-12-14 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2010040889A (en) * | 2008-08-07 | 2010-02-18 | Nec Electronics Corp | Semiconductor device and inspection method of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1694255A (en) * | 2004-03-17 | 2005-11-09 | 夏普株式会社 | Bidirectional light-controlled thyristor chip, light-starting arc coupler and solid-state relay |
| CN105590972A (en) * | 2014-11-11 | 2016-05-18 | 株式会社理光 | Semiconductor device, manufacturing method thereof and imaging apparatus |
| CN104505371A (en) * | 2014-12-10 | 2015-04-08 | 深圳市华星光电技术有限公司 | Method for forming test pads and method for performing array test by utilizing test pads |
| CN205104488U (en) * | 2015-11-02 | 2016-03-23 | 华润半导体（深圳）有限公司 | Opto -coupler packaging structure , voltage feedback circuit, system and equipment |
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